片上网络路由算法和映射算法研究
|
摘要
片上网络(NoC)已经成为微电子和通讯方面的热点研究,它的主要思想是将互联网络上的技术引入到片上网络中来。随着片上系统(System on chip,SoC)集成度的逐步提高,传统的总线结构的弊端逐渐暴露出来,比如总线带宽、全局同步等,而片上网络可以有效的解决这些问题。
在片上网络研究的关键技术中,路由算法决定了分组发送的选择路径,对网络的吞吐、时延、服务质量等将产生很大的影响。映射算法决定每个处理单元在NoC的位置,根据其优化的目的不同,它将对NoC系统的功耗、时延、面积、负载均衡等产生重大的影响。
本文主要针对片上网络的路由算法和映射算法两方面进行了研究,主要的工作包括如下两个方面：
1.在研究现有互联网络和片上网络确定性和适应性路由的基础上,提出了一种确定性和适应性相结合的路由算法DRM。该算法主要用于解决不规则2Dmesh拓扑结构中面向规则的拓扑的路由算法无法保证连通性,而现有算法为了保证连通性而使用了较多的虚信道的问题。仿真结果表明,DRM路由算法相比Boppana算法和VirtualNetwork算法,具有一定的性能优势。
2.在研究现有片上网络映射算法、全局优化算法的基础上,设计了一种结合了任务分配与任务调度的面向低能耗的多步映射算法。与传统的映射算法相比,该算法将片上网络设计中的任务调度与分配的因素结合到片上网络的映射算法中来,该映射算法分为三个阶段分别是：任务调度、IP核映射、数据模块映射。仿真结果表明,该映射方法可使Noc系统的功耗得到有效的减少。
Recently, the technology called Network-on-Chip(NoC) has aroused wide public concern. The reason for NoC has been designed is that with the steady growth of integration of System-on-Chip(SoC), the shortcomings of the traditional bus architecture have been exposed gradually. Such as bus bandwidth, global synchronization and so on. So NoC has been designed to solve the problem which is caused by development of SoC.
Routing algorithm determines the path by which the packets are sent. The choice of the path will produce a significant impact on network throughput, delay, quality of service and so on. Mapping algorithm was decided that each processing unit in the NoC position, according to the different purpose of optimizing, it will have a significant impact on NoC system's power consumption, delay, area, load balancing, etc.
In this paper, routing algorithm and mapping algorithm have been mainly studied. The main work and contribution have been generalized as follows:
1.Through the research of Internet and NoC's deterministic and adaptive routing, DRM algorithm which is combined deterministic and adaptive routing algorithm has been designed,which not only ensures connectivity of any couple of communication nodes but also just requires only two virtual channels.Furthermore, in the DRM routing algorithm, the method have been designed which is used for the choice of path.Simulation results show that, DRM routing algorithm compares with Boppana and VirtualNetwork algorithm has certain performance advantages.
2.Through the research of existing on-chip network mapping algorithm and global optimization algorithm, a multi-step mapping algorithm for low-power consumption have been designed which is combined with task allocation and task scheduling. Compared with the traditional mapping algorithm, the algorithm in this paper takes the factors of task scheduling and allocation into account, mapping algorithm is three steps: task scheduling, IP core mapping, data block mapping.The simulation results show that the mapping method in this paper can effectively reduce NoC power consumption.
在片上网络研究的关键技术中,路由算法决定了分组发送的选择路径,对网络的吞吐、时延、服务质量等将产生很大的影响。映射算法决定每个处理单元在NoC的位置,根据其优化的目的不同,它将对NoC系统的功耗、时延、面积、负载均衡等产生重大的影响。
本文主要针对片上网络的路由算法和映射算法两方面进行了研究,主要的工作包括如下两个方面：
1.在研究现有互联网络和片上网络确定性和适应性路由的基础上,提出了一种确定性和适应性相结合的路由算法DRM。该算法主要用于解决不规则2Dmesh拓扑结构中面向规则的拓扑的路由算法无法保证连通性,而现有算法为了保证连通性而使用了较多的虚信道的问题。仿真结果表明,DRM路由算法相比Boppana算法和VirtualNetwork算法,具有一定的性能优势。
2.在研究现有片上网络映射算法、全局优化算法的基础上,设计了一种结合了任务分配与任务调度的面向低能耗的多步映射算法。与传统的映射算法相比,该算法将片上网络设计中的任务调度与分配的因素结合到片上网络的映射算法中来,该映射算法分为三个阶段分别是：任务调度、IP核映射、数据模块映射。仿真结果表明,该映射方法可使Noc系统的功耗得到有效的减少。
Recently, the technology called Network-on-Chip(NoC) has aroused wide public concern. The reason for NoC has been designed is that with the steady growth of integration of System-on-Chip(SoC), the shortcomings of the traditional bus architecture have been exposed gradually. Such as bus bandwidth, global synchronization and so on. So NoC has been designed to solve the problem which is caused by development of SoC.
Routing algorithm determines the path by which the packets are sent. The choice of the path will produce a significant impact on network throughput, delay, quality of service and so on. Mapping algorithm was decided that each processing unit in the NoC position, according to the different purpose of optimizing, it will have a significant impact on NoC system's power consumption, delay, area, load balancing, etc.
In this paper, routing algorithm and mapping algorithm have been mainly studied. The main work and contribution have been generalized as follows:
1.Through the research of Internet and NoC's deterministic and adaptive routing, DRM algorithm which is combined deterministic and adaptive routing algorithm has been designed,which not only ensures connectivity of any couple of communication nodes but also just requires only two virtual channels.Furthermore, in the DRM routing algorithm, the method have been designed which is used for the choice of path.Simulation results show that, DRM routing algorithm compares with Boppana and VirtualNetwork algorithm has certain performance advantages.
2.Through the research of existing on-chip network mapping algorithm and global optimization algorithm, a multi-step mapping algorithm for low-power consumption have been designed which is combined with task allocation and task scheduling. Compared with the traditional mapping algorithm, the algorithm in this paper takes the factors of task scheduling and allocation into account, mapping algorithm is three steps: task scheduling, IP core mapping, data block mapping.The simulation results show that the mapping method in this paper can effectively reduce NoC power consumption.
引文
[1]杨敏华,谷建华,周兴社,片上网络,[J]《微处理机》2006.10第五期:28-34
[2]谭耀东1,刘有耀2NoC系统研究综述[N]《西安邮电学院学报》2008.1,卷13,第一期
[3]Luca Benini, Giovanni De Micheli. Network on chips:a new SoC paradigm[J]. IEEE Computer,2002,35 (1):70-78.
[4]Axel Jantsch, Hannu Tenhunen (Editors). Networks on Chip[M]. Boston Kluwer Academic Publishers,2003:3-18.
[5]Shashi Kumar et al. A network on chip architecture and design methodology VLSI'02 [C]. Pittsburgh, Pennsylvania,USA:IEEE,2002:105-112.
[6]周干民,片上网络_下一代技术,[J]商业文化.学术探讨2007.6:193-197.
[7]李丽,许居衍,片上网络技术发展现状及趋势浅析,[J]电子产品世界2009.1：32-38
[8]杨晓强,片上网络关键技术研究,[J]微型计算机信息(嵌入式与SoC)2008.24：173-176
[9]W. J. Dally. Scalable Switching Fabrics for Internet Routers, White paper, Avici Systems Inc.2001.
[10]Tobias Bjerregaard, Shankar Mahadevan, A Survey of Research and Practices of Network-on-Chip, ACM Computing Surveys, Vol.38, Issue 1,2006.
[11]S. Kumar et al., A Network on Chip Architecture and Design Methodology, Proc. Int'l Symp.VLSI (ISVLSI), pp:117-124,2002.
[12]W. J. Dally and B. Towles. Route packets, not wires:On-chip interconnection networks. In Design Automation Conf, pp:684-689,2001.
[13]W.J. Dally and C.L. Seitz, The Torus Routing Chip, Technical Report 5208:TR:86, Computer Science Dept., California Inst. Of Technology, pp:1-19,1986.
[14]S.R. Ohring, M. Ibel, S.K. Das, and M.I. Kumar, "On Generalized Fat Trees", Proceedings of 9th International Parallel Processing Symposium, pp.37-44,1995.
[15]Pierre Guerrier and Alain Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections", Proceedings of the Conference on Design, automation and test in Europe, pp.250-256,2000.
[16]P.P. Pande, C. Grecu, A. Ivanov and R. Saleh, "Design of a Switch for Network on Chip Applications", Proceedings of Int'l Symposium on Circuits and Systems (ISCAS), vol.5, pp.217-220, May,2003.
[17]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi, "Low-power and Low-latency Cluster Topology for Local Traffic NoCs", Proceedings of 2006 IEEE International Symposium on Circuits and Systems (ISCAS), vol.4, pp.1-5, May 2006.
[18]Vasilis F. Pavlidis and Eby G. Friedman, "3-D Topologies for Networks-on-Chip", Proceedings of International SOC Conference,2006 IEEE, pp.285-288, Sept. 2006.
[19]F. Karim et al., "An Interconnect Architecture for Networking Systems on Chips", IEEE Micro, vol.22, no.5, pp.36-45, Oct,2002.
[20]Jim Ammon, "Hypercube Connectivity within ccNUMA Architecture", Silicon Graphics Company,1998
[21]Tobias Bjerregaard and Shankar Mahadevan, "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys (CSUR), Volume 38, Issue 1, 2006.
[22]Kermani P and Kleinrock I, "Virtual cut-through:A new computer communication switching technique", Computer Network, col.3, pp.267-286,1979.
[23]W.J.Dally and C.L.Seitz, "The Torus Routing Chip", Journal of Distributed Computing, vol.3, no.3, pp.466-475, Aprial 1986.
[24]W.J.Dally and C.L.Seitz, "Deadlock-free Message Routing in Multiprocessor Interconnection Networks", IEEE Transactions on Computers, vol.C-36, no.5, pp.547-553, May 1987.
[25]W.J. Dally and C.L. Seitz, The Torus Routing Chip, Technical Report 5208:TR:86, Computer Science Dept., California Inst. Of Technology, pp:1-19,1986.
[26]Ye T T,Benini L,Micheli G De. Analysis of power consumption on switch fabrics in network routers [A]. DAC'02 [C].New Orleans,LA:ACM Press,2002.524-529.
[27]HuJ,MarculescuR.Energy-aware communication and taskscheduling for network-on-chip architectures under real-time constraints [A]. Proc DATE'04[C]. Paris:IEEE,2004.234-239.
[28]杨盛光,李 丽,高明伦,张宇昂,面向能耗和延时的NoC映射方法[J]电子学报.2008.5937-942.
[29]古海云1,李长文2,孙姝2不规则2D Mesh NoC映射算法研究[J]微电子学与计算机.2008.7 pp56-65
[30]Murali S, Micheli G De. Bandwidth2constrained mapping of cores onto NoC architectures [A]. DATE'04[C]. Pairs:IEEE,2004.896-901.
[31]J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, C.R. Das, A Low Latency Router Supporting Adaptivity for On-Chip Interconnects, the 42nd Design Automation. Conference, pp.559-564, June 2005.
[32]Nickray M,Dehyadgari M,Afzali2kusha. Power and delay opti-mization for network on chip [A]. ECCTD'05 [C]. Cork, Ire-land:IEEE,2005.273-276.
[33]Tang Lei,Shashi Kumar. A two2step genetic algorithm for mapping task graphs to a network on chip architecture [A]. DSD'03[C]. Antalya, Turkey:IEEE,2003. 180-187.
[34]Zhou W B, Zhang Y,Mao Z G. An application specific NoC mapping for optimized delay[A]. DTIS 2006[C]. Gammarth,Tunisia:IEEE,2006.184-188.
[35]Sttltzle T,Dorigo M. ACO Algorithms for the Quadratic Assignment Problem,New Ideas in Optimization [M]. McGrawHill,1999.
[36]吴春明,陈治,姜明.蚁群算法中系统初始化及系统参数的研究[J].电子学报,2006,34(8)：1530-1533.
[37]玄光男,程润伟.遗传算法与工程优化[M].北京：清华大学出版社,2004.
[38]E.G.Coffman, Jr.M.J.Elphic and A.Shoshani, "System Deadlocks", Computing Surveys, Vol.3, No.2, pp.67-78, June 1971.
[39]J.M.Duato,S.Yalamanchili, and L. Ni, "Interconnection Networks:An Engineering Approach (the Morgan Kaufmann Series in Computer Architecture and Design)", Publisher:Institute of Electrical& Electronics Enginee,2002.
[40]Ville Rantala, Teijo Lehtonen, and Juha Plosila, "Network on Chip Routing Algorithms", TUCS Technical Report No.779, University of Turku, August 2006.
[41]M. Chiu, The odd-even turn model for adaptive routing., IEEE Trans. on Parallel and Distributed Systems, pp.729-738, July 2000.
[42]Ming Li, Qing-An Zeng, Wen-Ben Jone, DyXY:a proximity congestion-aware deadlock-free dynamic routing method for network on chip, the 43rd annual conference on Design automation, July 2006:849-852
[43]Martin K-F Schafer, Thomas Hollstein. Deadlock-free routing and component placement for irregular mesh-based networks-on-chip[C].Proceedings of the 2005 IEEE International conference on Computer-aided design, Nov.2005:238-245.
[44]Sudhakar Yalamanchili Lionel Ni.Interconnection Networks An Engineering Approach[M]Publishing House of Electronics Industry.2004.4:58-148.
[45]Dong Wu, Bashir M.Al-Hashimi and Marcus T.Schmitz, Improving routing efficiency for network on chip through contention-aware input selection[C], the 2006 conference on Asia South Pacific design automation,2006.
[46]L.Schwieber and D.N.Jayasimha,"optimal fully adaptive wormhole routing for meshes,"[C]proceedings of supercomputing'93,November 1993.:782-791
[47]M. Dehyadgari, M. Nickray, A. Afzali-kusha, et al.Evaluation of Pseudo Adaptive XY Routing Using an Object Oriented Model for NoC[C]. The 17th Interna-tional Conference on Micro electronics,13-15 December 2005:204-208.
[48]段新明,杨愚鲁,基于不规则mesh的NoC无死锁路由,[J]小型微型计算机系统,2008.7:1215-121945
[49]OPNET-Modeler-documentation.-OPNET-Technologies.Inc.http://www.opnet.com /,2004
[50]Ville Rantala, Teijo Lehtonen, Juha Plosila, Network on Chip Routing Algorithms, Technical Report, No 779, University of Turku, August 2006.
[51]Terry Tao Ye, Luca Benini and Giovanni De Micheli, Packetization and routing analysis of on-chip multiprocessor networks, Journal of Systems Architecture, Vol 50, pp.81-104, Feb 2004.
[52]周干民,尹勇生,胡永华高,明伦, 《基于蚁群优化算法的Noc映射》[J]计算机工程与应用2005.186-12
[53]J. M. Anderson. Automatic Computation and Data Decomposition for Multiprocessors. Ph.D. Thesis,[J] Computer Science Department, Stanford University, March 1997.
[54]E.Ayguade.etal.A research tool for automatic data distribution in HPF.[J]Scientific Programming,1997 Vol.6, No.1:73-95,
[55]M. Gupta and P. Banerjee. Demonstration Automatic data partitioning techniques for parallelizing compilers on multi-computers[J]. IEEE TPDS, March 1992.
[56]S. P. Amarasinghe, J. M. Anderson, M. S. Lam, and C. W. Tseng. The SUIF com-piler for scalable parallel machines. In Proc. Seventh SIAM Conference on Parallel Processing for Scientific Computing, Feb.1995.
[2]谭耀东1,刘有耀2NoC系统研究综述[N]《西安邮电学院学报》2008.1,卷13,第一期
[3]Luca Benini, Giovanni De Micheli. Network on chips:a new SoC paradigm[J]. IEEE Computer,2002,35 (1):70-78.
[4]Axel Jantsch, Hannu Tenhunen (Editors). Networks on Chip[M]. Boston Kluwer Academic Publishers,2003:3-18.
[5]Shashi Kumar et al. A network on chip architecture and design methodology VLSI'02 [C]. Pittsburgh, Pennsylvania,USA:IEEE,2002:105-112.
[6]周干民,片上网络_下一代技术,[J]商业文化.学术探讨2007.6:193-197.
[7]李丽,许居衍,片上网络技术发展现状及趋势浅析,[J]电子产品世界2009.1：32-38
[8]杨晓强,片上网络关键技术研究,[J]微型计算机信息(嵌入式与SoC)2008.24：173-176
[9]W. J. Dally. Scalable Switching Fabrics for Internet Routers, White paper, Avici Systems Inc.2001.
[10]Tobias Bjerregaard, Shankar Mahadevan, A Survey of Research and Practices of Network-on-Chip, ACM Computing Surveys, Vol.38, Issue 1,2006.
[11]S. Kumar et al., A Network on Chip Architecture and Design Methodology, Proc. Int'l Symp.VLSI (ISVLSI), pp:117-124,2002.
[12]W. J. Dally and B. Towles. Route packets, not wires:On-chip interconnection networks. In Design Automation Conf, pp:684-689,2001.
[13]W.J. Dally and C.L. Seitz, The Torus Routing Chip, Technical Report 5208:TR:86, Computer Science Dept., California Inst. Of Technology, pp:1-19,1986.
[14]S.R. Ohring, M. Ibel, S.K. Das, and M.I. Kumar, "On Generalized Fat Trees", Proceedings of 9th International Parallel Processing Symposium, pp.37-44,1995.
[15]Pierre Guerrier and Alain Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections", Proceedings of the Conference on Design, automation and test in Europe, pp.250-256,2000.
[16]P.P. Pande, C. Grecu, A. Ivanov and R. Saleh, "Design of a Switch for Network on Chip Applications", Proceedings of Int'l Symposium on Circuits and Systems (ISCAS), vol.5, pp.217-220, May,2003.
[17]Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi, "Low-power and Low-latency Cluster Topology for Local Traffic NoCs", Proceedings of 2006 IEEE International Symposium on Circuits and Systems (ISCAS), vol.4, pp.1-5, May 2006.
[18]Vasilis F. Pavlidis and Eby G. Friedman, "3-D Topologies for Networks-on-Chip", Proceedings of International SOC Conference,2006 IEEE, pp.285-288, Sept. 2006.
[19]F. Karim et al., "An Interconnect Architecture for Networking Systems on Chips", IEEE Micro, vol.22, no.5, pp.36-45, Oct,2002.
[20]Jim Ammon, "Hypercube Connectivity within ccNUMA Architecture", Silicon Graphics Company,1998
[21]Tobias Bjerregaard and Shankar Mahadevan, "A Survey of Research and Practices of Network-on-Chip", ACM Computing Surveys (CSUR), Volume 38, Issue 1, 2006.
[22]Kermani P and Kleinrock I, "Virtual cut-through:A new computer communication switching technique", Computer Network, col.3, pp.267-286,1979.
[23]W.J.Dally and C.L.Seitz, "The Torus Routing Chip", Journal of Distributed Computing, vol.3, no.3, pp.466-475, Aprial 1986.
[24]W.J.Dally and C.L.Seitz, "Deadlock-free Message Routing in Multiprocessor Interconnection Networks", IEEE Transactions on Computers, vol.C-36, no.5, pp.547-553, May 1987.
[25]W.J. Dally and C.L. Seitz, The Torus Routing Chip, Technical Report 5208:TR:86, Computer Science Dept., California Inst. Of Technology, pp:1-19,1986.
[26]Ye T T,Benini L,Micheli G De. Analysis of power consumption on switch fabrics in network routers [A]. DAC'02 [C].New Orleans,LA:ACM Press,2002.524-529.
[27]HuJ,MarculescuR.Energy-aware communication and taskscheduling for network-on-chip architectures under real-time constraints [A]. Proc DATE'04[C]. Paris:IEEE,2004.234-239.
[28]杨盛光,李 丽,高明伦,张宇昂,面向能耗和延时的NoC映射方法[J]电子学报.2008.5937-942.
[29]古海云1,李长文2,孙姝2不规则2D Mesh NoC映射算法研究[J]微电子学与计算机.2008.7 pp56-65
[30]Murali S, Micheli G De. Bandwidth2constrained mapping of cores onto NoC architectures [A]. DATE'04[C]. Pairs:IEEE,2004.896-901.
[31]J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, C.R. Das, A Low Latency Router Supporting Adaptivity for On-Chip Interconnects, the 42nd Design Automation. Conference, pp.559-564, June 2005.
[32]Nickray M,Dehyadgari M,Afzali2kusha. Power and delay opti-mization for network on chip [A]. ECCTD'05 [C]. Cork, Ire-land:IEEE,2005.273-276.
[33]Tang Lei,Shashi Kumar. A two2step genetic algorithm for mapping task graphs to a network on chip architecture [A]. DSD'03[C]. Antalya, Turkey:IEEE,2003. 180-187.
[34]Zhou W B, Zhang Y,Mao Z G. An application specific NoC mapping for optimized delay[A]. DTIS 2006[C]. Gammarth,Tunisia:IEEE,2006.184-188.
[35]Sttltzle T,Dorigo M. ACO Algorithms for the Quadratic Assignment Problem,New Ideas in Optimization [M]. McGrawHill,1999.
[36]吴春明,陈治,姜明.蚁群算法中系统初始化及系统参数的研究[J].电子学报,2006,34(8)：1530-1533.
[37]玄光男,程润伟.遗传算法与工程优化[M].北京：清华大学出版社,2004.
[38]E.G.Coffman, Jr.M.J.Elphic and A.Shoshani, "System Deadlocks", Computing Surveys, Vol.3, No.2, pp.67-78, June 1971.
[39]J.M.Duato,S.Yalamanchili, and L. Ni, "Interconnection Networks:An Engineering Approach (the Morgan Kaufmann Series in Computer Architecture and Design)", Publisher:Institute of Electrical& Electronics Enginee,2002.
[40]Ville Rantala, Teijo Lehtonen, and Juha Plosila, "Network on Chip Routing Algorithms", TUCS Technical Report No.779, University of Turku, August 2006.
[41]M. Chiu, The odd-even turn model for adaptive routing., IEEE Trans. on Parallel and Distributed Systems, pp.729-738, July 2000.
[42]Ming Li, Qing-An Zeng, Wen-Ben Jone, DyXY:a proximity congestion-aware deadlock-free dynamic routing method for network on chip, the 43rd annual conference on Design automation, July 2006:849-852
[43]Martin K-F Schafer, Thomas Hollstein. Deadlock-free routing and component placement for irregular mesh-based networks-on-chip[C].Proceedings of the 2005 IEEE International conference on Computer-aided design, Nov.2005:238-245.
[44]Sudhakar Yalamanchili Lionel Ni.Interconnection Networks An Engineering Approach[M]Publishing House of Electronics Industry.2004.4:58-148.
[45]Dong Wu, Bashir M.Al-Hashimi and Marcus T.Schmitz, Improving routing efficiency for network on chip through contention-aware input selection[C], the 2006 conference on Asia South Pacific design automation,2006.
[46]L.Schwieber and D.N.Jayasimha,"optimal fully adaptive wormhole routing for meshes,"[C]proceedings of supercomputing'93,November 1993.:782-791
[47]M. Dehyadgari, M. Nickray, A. Afzali-kusha, et al.Evaluation of Pseudo Adaptive XY Routing Using an Object Oriented Model for NoC[C]. The 17th Interna-tional Conference on Micro electronics,13-15 December 2005:204-208.
[48]段新明,杨愚鲁,基于不规则mesh的NoC无死锁路由,[J]小型微型计算机系统,2008.7:1215-121945
[49]OPNET-Modeler-documentation.-OPNET-Technologies.Inc.http://www.opnet.com /,2004
[50]Ville Rantala, Teijo Lehtonen, Juha Plosila, Network on Chip Routing Algorithms, Technical Report, No 779, University of Turku, August 2006.
[51]Terry Tao Ye, Luca Benini and Giovanni De Micheli, Packetization and routing analysis of on-chip multiprocessor networks, Journal of Systems Architecture, Vol 50, pp.81-104, Feb 2004.
[52]周干民,尹勇生,胡永华高,明伦, 《基于蚁群优化算法的Noc映射》[J]计算机工程与应用2005.186-12
[53]J. M. Anderson. Automatic Computation and Data Decomposition for Multiprocessors. Ph.D. Thesis,[J] Computer Science Department, Stanford University, March 1997.
[54]E.Ayguade.etal.A research tool for automatic data distribution in HPF.[J]Scientific Programming,1997 Vol.6, No.1:73-95,
[55]M. Gupta and P. Banerjee. Demonstration Automatic data partitioning techniques for parallelizing compilers on multi-computers[J]. IEEE TPDS, March 1992.
[56]S. P. Amarasinghe, J. M. Anderson, M. S. Lam, and C. W. Tseng. The SUIF com-piler for scalable parallel machines. In Proc. Seventh SIAM Conference on Parallel Processing for Scientific Computing, Feb.1995.
© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号 地址：北京市海淀区学院路29号 邮编：100083 电话：办公室：(+86 10)66554848；文献借阅、咨询服务、科技查新：66554700 |