牺牲氧化层的湿法蚀刻对栅氧化层影响的研究
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摘要
硅片清洗对半导体工业的重要性早在50年代初即已引起人们的高度重视,这是由于硅片表面的污染物会严重影响器件的性能、可靠性和成品率。随着集成电路由大规模向超大规模(VLSI)和甚大规模(ULSI)发展,电路的集成度日益提高、特征尺寸日益缩小,污染物对器件的影响也愈加突出。目前半导体行业中广泛使用的清洗工艺仍是以沃纳·克恩(Werner Kern)于1970年提出的标准RCA清洗法为基础框架,经过多年不断改进形成的[1]。
硅片表面的洁净度及表面态对高质量的硅器件工艺是至关重要的。如果表面质量达不到要求,无论其它工艺步骤控制得多么完美,也是不可能获得高质量的半导体器件的。除去硅片表面上的沾污已不再是最终的要求,在清洗过程中所形成的表面化学态(终止态)及粗糙度已成为同样重要的参数[2]。这些新的考虑改变了关于“晶片清洗”的观念由单纯的去除沾污转变到真正的“表面工程”。对于随着线宽不断减小,同时不断变薄的栅氧化层来说,生长前的预清洗尤其如此。
本文主要的研究内容是栅氧化层预清洗工艺中牺牲氧化层(Sacrificial Oxide)的过蚀刻率对有源区(Active Area)的表面化学态、后续栅氧化层生长、器件的电性特征参数以及产品良率的影响。
相对于0.18微米技术,0.13微米技术节点下,由于对有源区边缘倒角(Divot)提出了更高的要求,牺牲氧化层的过蚀刻率必须要减小。但是如果牺牲氧化层的过蚀刻率设置过低,就会导致下限工艺窗口不足,引起栅氧化层预清洗后有源区硅表面氢终止程度的波动,使后续栅氧化层生长的厚度以及器件的电性特征参数产生了过大波动,进而导致产品良率下降。
本课题从量产工厂的实际出发,通过工程试验设计方法,利用一组试验成功找出了0.13微米CMOS (Complementary Metal Oxide Semiconductor)技术栅氧化层预清洗工艺中牺牲氧化层过蚀刻率的工艺窗口(Process Window),从而得到了牺牲氧化层过蚀刻率的优化条件。优化方案既解决了量产中由于稀释氢氟酸蚀刻率的波动所带来的下限工艺窗口不足的问题,又避免了由于过蚀刻率的升高而使倒角(Divot)(?)司题恶化,从而导致器件的电性特征参数出现双驼峰(Double Hump)现象。优化方案实施后,大大减少了生产中人为控制压力,并极大地降低了由于人为因素引起操作失误的风险；大大提高了产能利用率,及明显地缩短了生产周期(Cycle Time);稳定了器件的电学特征参数,大大提高了工艺精密度,同时明显提高了产品良率。
The importance of clean substrate surfaces in the fabrication of semiconductor microelectronic devices has been recognized since the early days of the 1950s. As the requirements for increased device performance and reliability have become more stringent in the era of VLSI and ULSI silicon circuit technology, techniques to avoid contamination and processes to generate very clean wafer surfaces have become critically important. Besides, over 50% of yield losses in integrated circuit fabrication are generally accepted to be due to micro-contamination.
Many wafer cleaning techniques have been tested and several are being used. The generally most successful approach for silicon wafers without metallization uses wet chemical treatments. This process has remained essentially unchanged during the past several decades and is developed base on hot alkaline and acidic hydrogen peroxide solutions, a process known as "RCA Standard Clean," which was developed at RCA, introduced to device production in 1965, and published in 1970.
Impurities on silicon wafer surfaces occur in essentially three forms: (i) contaminant films, (ii) discrete particles, and (iii) adsorbed gases that are of little practical consequence in wafer processing. But, the purity of wafer surfaces is not the only requirement any more, the surface state and micro-roughness after cleaning treatment become quite important for the successful fabrication of ULSI silicon circuits.
It is revealed that the ratio of over etch for sacrificial oxide has the determining influence on the surface state during the processing of gate oxide pre-cleaning. At 0.13um technology node, the ratio of over etch for sacrificial oxide must be decreased for the concern of divot at the corner of active area. But too low ratio of over etch will result in the insufficient termination of hydrogen. In this case, the variation of etching rate of dilute HF will bring much higher fluctuation on the following gate oxide growth, then the electrical performance of device, the final production yield.
This article studies the process window of the over etching ratio for the sacrificial oxide during gate oxide pre-cleaning process and works out the best solution under the consideration of both the divot concern and the sufficient hydrogen termination base on 0.13um CMOS (Complementary Metal Oxide Semiconductor) technology. After the best solution implementation, it brings the great reduction of engineering loading, the remarkable improvement of tool efficiency and process precision capability and yield gain.
硅片表面的洁净度及表面态对高质量的硅器件工艺是至关重要的。如果表面质量达不到要求,无论其它工艺步骤控制得多么完美,也是不可能获得高质量的半导体器件的。除去硅片表面上的沾污已不再是最终的要求,在清洗过程中所形成的表面化学态(终止态)及粗糙度已成为同样重要的参数[2]。这些新的考虑改变了关于“晶片清洗”的观念由单纯的去除沾污转变到真正的“表面工程”。对于随着线宽不断减小,同时不断变薄的栅氧化层来说,生长前的预清洗尤其如此。
本文主要的研究内容是栅氧化层预清洗工艺中牺牲氧化层(Sacrificial Oxide)的过蚀刻率对有源区(Active Area)的表面化学态、后续栅氧化层生长、器件的电性特征参数以及产品良率的影响。
相对于0.18微米技术,0.13微米技术节点下,由于对有源区边缘倒角(Divot)提出了更高的要求,牺牲氧化层的过蚀刻率必须要减小。但是如果牺牲氧化层的过蚀刻率设置过低,就会导致下限工艺窗口不足,引起栅氧化层预清洗后有源区硅表面氢终止程度的波动,使后续栅氧化层生长的厚度以及器件的电性特征参数产生了过大波动,进而导致产品良率下降。
本课题从量产工厂的实际出发,通过工程试验设计方法,利用一组试验成功找出了0.13微米CMOS (Complementary Metal Oxide Semiconductor)技术栅氧化层预清洗工艺中牺牲氧化层过蚀刻率的工艺窗口(Process Window),从而得到了牺牲氧化层过蚀刻率的优化条件。优化方案既解决了量产中由于稀释氢氟酸蚀刻率的波动所带来的下限工艺窗口不足的问题,又避免了由于过蚀刻率的升高而使倒角(Divot)(?)司题恶化,从而导致器件的电性特征参数出现双驼峰(Double Hump)现象。优化方案实施后,大大减少了生产中人为控制压力,并极大地降低了由于人为因素引起操作失误的风险；大大提高了产能利用率,及明显地缩短了生产周期(Cycle Time);稳定了器件的电学特征参数,大大提高了工艺精密度,同时明显提高了产品良率。
The importance of clean substrate surfaces in the fabrication of semiconductor microelectronic devices has been recognized since the early days of the 1950s. As the requirements for increased device performance and reliability have become more stringent in the era of VLSI and ULSI silicon circuit technology, techniques to avoid contamination and processes to generate very clean wafer surfaces have become critically important. Besides, over 50% of yield losses in integrated circuit fabrication are generally accepted to be due to micro-contamination.
Many wafer cleaning techniques have been tested and several are being used. The generally most successful approach for silicon wafers without metallization uses wet chemical treatments. This process has remained essentially unchanged during the past several decades and is developed base on hot alkaline and acidic hydrogen peroxide solutions, a process known as "RCA Standard Clean," which was developed at RCA, introduced to device production in 1965, and published in 1970.
Impurities on silicon wafer surfaces occur in essentially three forms: (i) contaminant films, (ii) discrete particles, and (iii) adsorbed gases that are of little practical consequence in wafer processing. But, the purity of wafer surfaces is not the only requirement any more, the surface state and micro-roughness after cleaning treatment become quite important for the successful fabrication of ULSI silicon circuits.
It is revealed that the ratio of over etch for sacrificial oxide has the determining influence on the surface state during the processing of gate oxide pre-cleaning. At 0.13um technology node, the ratio of over etch for sacrificial oxide must be decreased for the concern of divot at the corner of active area. But too low ratio of over etch will result in the insufficient termination of hydrogen. In this case, the variation of etching rate of dilute HF will bring much higher fluctuation on the following gate oxide growth, then the electrical performance of device, the final production yield.
This article studies the process window of the over etching ratio for the sacrificial oxide during gate oxide pre-cleaning process and works out the best solution under the consideration of both the divot concern and the sufficient hydrogen termination base on 0.13um CMOS (Complementary Metal Oxide Semiconductor) technology. After the best solution implementation, it brings the great reduction of engineering loading, the remarkable improvement of tool efficiency and process precision capability and yield gain.
引文
[1]Werner Kern. "HANDBOOK OF SEMICONDUCTOR WAFER CLEANING TECHNOLOGY. " NOYES PUBLICATIONS, (1993). Page(s):3-22
[2]D. M. Knotter, S. De Gendt, P. W. Mertens, and M. M. Heyns, "Silicon surface roughning mechanisms in ammonia hydrogen peroxide mixtures. " J. Electrochem. Soc.147 (2), (2000). Page (s):736-740
[3]Werner Kern. "Overview and Evolution of Semiconductor Wafer Contamination and Cleaning Technology," Werner Kern ed., Noyes Publications (1993). Page(s):119-120.
[4]Werner Kern. "Handbook of Semiconductor Wafer Cleaning Technology: Science, Technology, and Applications, " Werner Kern ed., Noyes Publications (1993).Page(s):18-50.
[5]张开华编.半导体集成电路[M].南京：东南大学出版社,1995：1-20.
[6]Scotten W.Jones. "Integrated Circuit Technology [C] ". IC Knowledge LLC, Version 2006 Page(s):42-57.
[7]David J. Mount, Laura B. Rothman, Raymond J. Robey, Mir K. Ali, "The technology behind cleaning with supercritical fluids, " Sol. State Tech, Jul. (2002). Page(s):103
[8]Paul W. Mertens and Els Parton, "Sub-100nm technologies drive: single-wafer cleaning," Sol. State Tech., Feb. (2002). Page(s):51.
[9][美]毕查德.拉扎维著,陈贵灿,张瑞智译.模拟CMOS集成电路设计[M].西安：西安交通大学出版社,2003：105-176
[10][美]Robert F.Pierret. "Semicondutor Device Fundamentals. " Publishing House of Electronics Industry, November 2004. Page (s):50-100
[11][美]Stephen A. Campbell著,曾莹,严利人,王纪民,张伟译.微电子制造科学原理与工程技术[M].北京：电子工业出版社,2003：50-150
[12]莊达人编.VLSI制造技术[M].台北：高立图书有限公司,2002：349-375
[13]章小鸽编.硅及其氧化物的电化学[M].北京：化学工业出版社,2004：30-70
[14]无机化学教研室编.无机化学上册[M].北京：高等教育出版社,2002.8：215319.
[15]史保华,贾新章,张德胜编.微电子器件可靠性[M].西安：西安电子科技大学出版社,1999：25-100
[2]D. M. Knotter, S. De Gendt, P. W. Mertens, and M. M. Heyns, "Silicon surface roughning mechanisms in ammonia hydrogen peroxide mixtures. " J. Electrochem. Soc.147 (2), (2000). Page (s):736-740
[3]Werner Kern. "Overview and Evolution of Semiconductor Wafer Contamination and Cleaning Technology," Werner Kern ed., Noyes Publications (1993). Page(s):119-120.
[4]Werner Kern. "Handbook of Semiconductor Wafer Cleaning Technology: Science, Technology, and Applications, " Werner Kern ed., Noyes Publications (1993).Page(s):18-50.
[5]张开华编.半导体集成电路[M].南京：东南大学出版社,1995：1-20.
[6]Scotten W.Jones. "Integrated Circuit Technology [C] ". IC Knowledge LLC, Version 2006 Page(s):42-57.
[7]David J. Mount, Laura B. Rothman, Raymond J. Robey, Mir K. Ali, "The technology behind cleaning with supercritical fluids, " Sol. State Tech, Jul. (2002). Page(s):103
[8]Paul W. Mertens and Els Parton, "Sub-100nm technologies drive: single-wafer cleaning," Sol. State Tech., Feb. (2002). Page(s):51.
[9][美]毕查德.拉扎维著,陈贵灿,张瑞智译.模拟CMOS集成电路设计[M].西安：西安交通大学出版社,2003：105-176
[10][美]Robert F.Pierret. "Semicondutor Device Fundamentals. " Publishing House of Electronics Industry, November 2004. Page (s):50-100
[11][美]Stephen A. Campbell著,曾莹,严利人,王纪民,张伟译.微电子制造科学原理与工程技术[M].北京：电子工业出版社,2003：50-150
[12]莊达人编.VLSI制造技术[M].台北：高立图书有限公司,2002：349-375
[13]章小鸽编.硅及其氧化物的电化学[M].北京：化学工业出版社,2004：30-70
[14]无机化学教研室编.无机化学上册[M].北京：高等教育出版社,2002.8：215319.
[15]史保华,贾新章,张德胜编.微电子器件可靠性[M].西安：西安电子科技大学出版社,1999：25-100
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