可重构SoC设计技术研究
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摘要
PC市场日渐成熟,以个人信息助理为代表的“数码消费品”终将主导半导体应用市场的下一轮增长,数码消费品的一大特征就是频繁地更新换代。可重构SoC结合了指令集处理器的存贮软编程和可重构逻辑器件的硬布线编程的优点,既具有很强的计算能力、又具有灵活的重构特点;既内涵很宽的通信协议、又有足够的“净空”留给用户去应用创新。也就是说,基于某一个应用领域的可重构SoC架构形成后,用户可以仅仅通过软件编程就能达到重构特定应用功能的目的,这一特点不仅大大适应了后PC时代“数码消费品”应用市场对硅产品既要求高度复杂,又要求较低成本和快速更新上市的要求,而且还因此推动着半导体产业结构的进一步分化,催生“不搞芯片设计、专事平台上创新应用”的Designless模式的涌现。
本论文针对“数码消费品”将主导未来半导体应用市场的发展趋势,研究动态重构SoC的设计方法和实现技术。鉴于可重构SoC既是产业界的热点,又是学术研究的前沿,因而论文特别在“直接影响动态重构SoC可实现性和系统成本的FPGA配置数据压缩技术”和“可重构技术与片上通信网络(NoC)技术相结合”两个方面做了重点研究。主要研究工作与取得的创新成果如下:
(1)系统总结了业界从ASIC和FPGA两个方向实现可重构SoC所取得的研究成果,并讨论可重构SoC的未来发展方向。尝试以“谁来控制重构、配置何时生成、重构粒度如何”三个问题为轴,建立了动态重构的三维分类法。提出了可涵盖所有动态重构模式的通用DRSoC(动态重构SoC)体系结构,并初步探讨其计算模型和设计流程。以基于Xilinx 32位软核Microblaze的SoPC为目标平台,研究DRSoC实现技术,总结两种动态重构设计方案:“System ACE方案”和“ICAP方案”,并将两种实现方案相结合,实现对通用DRSoC体系结构的模拟,示例其设计流程。
(2)研究FPGA配置数据的无损压缩技术,以FPGA配置数据的“帧间数据规律性”和“帧内数据规律性”概念作为算法改进的基础,提出了改进型LZW压缩算法,采用5种通用电路模块为例,以5种不同规模的Xilinx Virtex系列FPGA为目标器件,改进后的算法对配置数据的压缩率在45.63%～67.38%之间,比基本LZW算法压缩率平均提高了10%。在此基础上进一步抽象出片上动态重构通用设计方法,提出了实用的工程目录范例。该设计方法和工程目录范例在11种实用电路模块上进行了实验验证,基于“配置间规律性”的实时压缩技术对动态重构中的部分配置数据取得了43.69%的压缩效果,同时也检验了可重构设计方法的工程实用性。
(3)在总结和分析NoC映射算法相关研究的基础上,针对实际系统中各IP核通常在规模上会有很大差异的特点,选择不规则2D Mesh作为动态重构NoC的拓扑结构,建立了NoC拓扑结构的映射算法数学模型和优化目标函数,提出了保证网格不重叠约束条件的数学表达和IP间通信距离的求解方法。以一个视频解码器为例验证了该映射算法的可行性,并给出了FPGA布局结果的实现示例。
The market of PC tends to be saturated.“Digital consumables”, PDA mainly, will lead the next generation semiconductor product, the most apparent character of these digital consumables is the continual updating which will cause huge amounts of electronic landfills. Reconfigurable SoC combined the hardware high performance and software flexibility, which can be compatible with multiple protocols and simultaneously give user enough space for individuation and updating. Moreover, reconfigurable SoC can meet the time-to-market requirement of digital consumable products, and will drive the divide of“chip design”and“product developing”.
The design methodology and implement technology of dynamically reconfigurable SoC is researched. A compressing algorithm for FPGA bitstream is proposed, and the combination of reconfigurable SoC and Network-on-Chip technology is studied. The main work and achievements are as follows:
1. Taxonomy of reconfiguration mode is proposed based on the conclusion and analysis of present research results on RSoC (Reconfigurable System-on-Chip) and SoPC (System on Programmable Chip). The future direction of reconfigurable SoC is discussed. A 3-D space of dynamic reconfiguration is built. A general architecture of dynamic reconfigurable SoC is presented, and its compute model and design flow are discussed. Three kinds of solutions of dynamic reconfiguration are proposed and illustrated, taking use of the Xilinx Microblaze-based SoPC and its development tools kit.
2. An adaptive LZW algorithm for compressing global and partial bitstreams of FPGA is presented. The adaptations of algorithm are based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams are created through Xilinx module-based partial reconfiguration flow. The experiment demonstrates down to 45.63% compression rate for global configuration bitstreams and 43.69% compression ratio for partial configuration bitstreams of several real-world applications implemented on Virtex series FPGAs.
3. A mathematic model of NoC based on irregular 2D mesh topology is built for reconfigurable device. The mathematic expression of grid overlapping constrain is presented, and the problem of calculating the communicating distance between IPs is resolved. The experiment with a video object plane decoder demonstrated the efficiency of the algorithm. An FPGA implementation example of placement result is given.
本论文针对“数码消费品”将主导未来半导体应用市场的发展趋势,研究动态重构SoC的设计方法和实现技术。鉴于可重构SoC既是产业界的热点,又是学术研究的前沿,因而论文特别在“直接影响动态重构SoC可实现性和系统成本的FPGA配置数据压缩技术”和“可重构技术与片上通信网络(NoC)技术相结合”两个方面做了重点研究。主要研究工作与取得的创新成果如下:
(1)系统总结了业界从ASIC和FPGA两个方向实现可重构SoC所取得的研究成果,并讨论可重构SoC的未来发展方向。尝试以“谁来控制重构、配置何时生成、重构粒度如何”三个问题为轴,建立了动态重构的三维分类法。提出了可涵盖所有动态重构模式的通用DRSoC(动态重构SoC)体系结构,并初步探讨其计算模型和设计流程。以基于Xilinx 32位软核Microblaze的SoPC为目标平台,研究DRSoC实现技术,总结两种动态重构设计方案:“System ACE方案”和“ICAP方案”,并将两种实现方案相结合,实现对通用DRSoC体系结构的模拟,示例其设计流程。
(2)研究FPGA配置数据的无损压缩技术,以FPGA配置数据的“帧间数据规律性”和“帧内数据规律性”概念作为算法改进的基础,提出了改进型LZW压缩算法,采用5种通用电路模块为例,以5种不同规模的Xilinx Virtex系列FPGA为目标器件,改进后的算法对配置数据的压缩率在45.63%～67.38%之间,比基本LZW算法压缩率平均提高了10%。在此基础上进一步抽象出片上动态重构通用设计方法,提出了实用的工程目录范例。该设计方法和工程目录范例在11种实用电路模块上进行了实验验证,基于“配置间规律性”的实时压缩技术对动态重构中的部分配置数据取得了43.69%的压缩效果,同时也检验了可重构设计方法的工程实用性。
(3)在总结和分析NoC映射算法相关研究的基础上,针对实际系统中各IP核通常在规模上会有很大差异的特点,选择不规则2D Mesh作为动态重构NoC的拓扑结构,建立了NoC拓扑结构的映射算法数学模型和优化目标函数,提出了保证网格不重叠约束条件的数学表达和IP间通信距离的求解方法。以一个视频解码器为例验证了该映射算法的可行性,并给出了FPGA布局结果的实现示例。
The market of PC tends to be saturated.“Digital consumables”, PDA mainly, will lead the next generation semiconductor product, the most apparent character of these digital consumables is the continual updating which will cause huge amounts of electronic landfills. Reconfigurable SoC combined the hardware high performance and software flexibility, which can be compatible with multiple protocols and simultaneously give user enough space for individuation and updating. Moreover, reconfigurable SoC can meet the time-to-market requirement of digital consumable products, and will drive the divide of“chip design”and“product developing”.
The design methodology and implement technology of dynamically reconfigurable SoC is researched. A compressing algorithm for FPGA bitstream is proposed, and the combination of reconfigurable SoC and Network-on-Chip technology is studied. The main work and achievements are as follows:
1. Taxonomy of reconfiguration mode is proposed based on the conclusion and analysis of present research results on RSoC (Reconfigurable System-on-Chip) and SoPC (System on Programmable Chip). The future direction of reconfigurable SoC is discussed. A 3-D space of dynamic reconfiguration is built. A general architecture of dynamic reconfigurable SoC is presented, and its compute model and design flow are discussed. Three kinds of solutions of dynamic reconfiguration are proposed and illustrated, taking use of the Xilinx Microblaze-based SoPC and its development tools kit.
2. An adaptive LZW algorithm for compressing global and partial bitstreams of FPGA is presented. The adaptations of algorithm are based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams are created through Xilinx module-based partial reconfiguration flow. The experiment demonstrates down to 45.63% compression rate for global configuration bitstreams and 43.69% compression ratio for partial configuration bitstreams of several real-world applications implemented on Virtex series FPGAs.
3. A mathematic model of NoC based on irregular 2D mesh topology is built for reconfigurable device. The mathematic expression of grid overlapping constrain is presented, and the problem of calculating the communicating distance between IPs is resolved. The experiment with a video object plane decoder demonstrated the efficiency of the algorithm. An FPGA implementation example of placement result is given.
引文
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