集成电路单粒子效应建模与加固方法研究
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摘要
辐射环境中的高能粒子入射半导体材料时,其轨迹上淀积的电荷将被敏感节点收集,引发单粒子效应。单粒子效应将引起存储数据错误,影响后续计算,甚至半导体器件永久损坏,从而导致整个系统崩溃,造成严重的后果。国内外的航天器故障统计表明,单粒子效应是航天器电子系统中主要可靠性问题之一。
随着集成电路工艺的不断进步,SEU引起的软错误率在持续上升,SET和MBU等二次效应逐渐成为重要的失效模式。在当前的工艺条件下,传统的单粒子效应建模方法在精度和速度上,传统的加固方法在性能和代价上体现出来越来越多的不足。本文针对当前工艺下单粒子效应的特点,对单粒子效应的建模和加固方法进行了深入研究,取得的主要研究成果如下:
(1)提出了一种SEU加固的存储单元结构。通过对电荷收集敏感区域特点的分析以及合理的电路设计,提出了一种新型的抗SEU加固的存储单元结构,该存储单元可以自行从单个翻转中恢复。该存储单元可以使用商用的CMOS工艺线,从而极大的降低了抗辐照芯片的成本,并且有较高的性能、集成度和较低的功耗。(2)开展了电荷共享收集以及对存储单元的影响的研究。使用器件模拟的手段分析了电荷共享收集量的温度相关性,发现了温度对电荷共享受有显著的影响。并详细分析了电荷共享引起SRAM单元MBU和加固存储单元MNU的过程。进而提出了增加敏感节点对的距离、背靠背结构以及在敏感节点对之间插入保护环等抑制电荷共享的方法。
(3)提出了电路级耦合SET脉冲注入方法。传统的独立电流源SET模型在超深亚微米工艺下有较大误差。本文探讨了各种影响SET脉冲的因素,通过合理的假设,将SET电流脉冲简化为电荷收集量和PN结偏压的二维查找表模型,并且在开源的SPICE软件中实现了这一模型。该方法相比独立电流源模型的精度有很大提高。
(4)提出了组合逻辑SET脉冲重汇聚的分析方法。本文提出了脉冲传播过程中的重汇聚分析框架SERAR。其中将重汇聚分为4种模式:ROR、RSUB、RAND和RXOR,对每一种模式都提出了基于布尔差分的敏化条件。实验表明重汇聚对SER计算结果和节点敏感性有显著影响。
(5)设计实现了一款基于SOI工艺的SRAM。本设计采用全定制设计方法,基于0.5 m PD SOI工艺实现,容量256 32。完成了从逻辑设计、版图设计以及投片的完整流程。对于抗辐照加固,除了依赖SOI工艺本身的能力,还采用了体引出等技术降低对单粒子效应的敏感性,采用环形栅等技术改善其总剂量的敏感性。
最后本文单粒子效应建模和加固技术未来的研究方向进行了展望。
In radiation environment when high energy ion strikes at semiconductor material charge will deposit along its track. Sensitive nodes collect the charge and induce single event effect. SEE will induce data error and even semiconductor device damage, which will affect the following computing and cause the collapse of the whole system. Statistic of failure shows that SEE is the one of the main reliability challenges in spacecraft electric system.
With the advancing of integrate circuit technology, SEU error rate is ever increasing, SET and MBU become important failure modes. The accuracy and speed of traditional modeling technique and the performance and cost of traditional hardening technique show more and more insufficiency. In this dissertation, we aim at the feature of SEE under present semiconductor technology, and study the modeling and hardening of SEE thoroughly. The main works and contributions of the dissertation are as follows
1) We propose a novel SEU hardened storage cell. Base on the analysis of chare collection sensitive area and appropriate circuit design, a novel SEU hardening storage cell is presented, which can recovery automatically from single node upset. The storage cell can be fabricated in commercial CMOS process. Therefore it achieves low cost, low power, high speed and high integrity.
2) We study the charge sharing collection and its effect to storage cells. By three-dimensional device simulation method, we study the temperature dependency of charge sharing. The simulation results show that the charge sharing collection rise significantly with temperature rising. MBU in SRAM cells and MNU in hardened storage cells induced by charge sharing is analysed in detail. Furthermore, three methods to restrain charge sharing is presented: Enlarging the distance between sensitive nodes, insert guard ring and back-to-back layout style.
3) We propose a circuit level coupled SET pulse injection method. Traditional SET independent current source will introduce great error in ultra deep submicro technology. We explored the factors which affect the SET pulse shape and model the SET pulse as a two-dimension lookup table. This method is implemented in open sourced SPICE tool. This method is a well tradeoff between speed and accuracy comparing with independent models and circuit/device mix-mode simulation.
4) We propose the SET reconvegence analyse framework in combinational logic, SERAR. In SERAR, reconvergence is classified into 4 mode, ROR, RSUB, RAND and RXOR. For each mode, the sensitized condition based on Boolean difference is presented. Experiments on ISCAS’85 benchmark circuit show reconvergence has significant effect on SER and node sensitivity estimation.
5) We design a radiation hardened SRAM based on SOI technology. The design and implement of a 256 32 SRAM with full custom method based on 0.5 m PD SOI technology is described. We complete the whole flow including circuit design, layout design, timing modeling. For radiation hardening, besides the intrinsic ability of SOI, we employ the body tie to improve SEE sensitivity, and edgeless gate to improve TID sensitivity.
Finally we forecast the research area of SEE in the future.
随着集成电路工艺的不断进步,SEU引起的软错误率在持续上升,SET和MBU等二次效应逐渐成为重要的失效模式。在当前的工艺条件下,传统的单粒子效应建模方法在精度和速度上,传统的加固方法在性能和代价上体现出来越来越多的不足。本文针对当前工艺下单粒子效应的特点,对单粒子效应的建模和加固方法进行了深入研究,取得的主要研究成果如下:
(1)提出了一种SEU加固的存储单元结构。通过对电荷收集敏感区域特点的分析以及合理的电路设计,提出了一种新型的抗SEU加固的存储单元结构,该存储单元可以自行从单个翻转中恢复。该存储单元可以使用商用的CMOS工艺线,从而极大的降低了抗辐照芯片的成本,并且有较高的性能、集成度和较低的功耗。(2)开展了电荷共享收集以及对存储单元的影响的研究。使用器件模拟的手段分析了电荷共享收集量的温度相关性,发现了温度对电荷共享受有显著的影响。并详细分析了电荷共享引起SRAM单元MBU和加固存储单元MNU的过程。进而提出了增加敏感节点对的距离、背靠背结构以及在敏感节点对之间插入保护环等抑制电荷共享的方法。
(3)提出了电路级耦合SET脉冲注入方法。传统的独立电流源SET模型在超深亚微米工艺下有较大误差。本文探讨了各种影响SET脉冲的因素,通过合理的假设,将SET电流脉冲简化为电荷收集量和PN结偏压的二维查找表模型,并且在开源的SPICE软件中实现了这一模型。该方法相比独立电流源模型的精度有很大提高。
(4)提出了组合逻辑SET脉冲重汇聚的分析方法。本文提出了脉冲传播过程中的重汇聚分析框架SERAR。其中将重汇聚分为4种模式:ROR、RSUB、RAND和RXOR,对每一种模式都提出了基于布尔差分的敏化条件。实验表明重汇聚对SER计算结果和节点敏感性有显著影响。
(5)设计实现了一款基于SOI工艺的SRAM。本设计采用全定制设计方法,基于0.5 m PD SOI工艺实现,容量256 32。完成了从逻辑设计、版图设计以及投片的完整流程。对于抗辐照加固,除了依赖SOI工艺本身的能力,还采用了体引出等技术降低对单粒子效应的敏感性,采用环形栅等技术改善其总剂量的敏感性。
最后本文单粒子效应建模和加固技术未来的研究方向进行了展望。
In radiation environment when high energy ion strikes at semiconductor material charge will deposit along its track. Sensitive nodes collect the charge and induce single event effect. SEE will induce data error and even semiconductor device damage, which will affect the following computing and cause the collapse of the whole system. Statistic of failure shows that SEE is the one of the main reliability challenges in spacecraft electric system.
With the advancing of integrate circuit technology, SEU error rate is ever increasing, SET and MBU become important failure modes. The accuracy and speed of traditional modeling technique and the performance and cost of traditional hardening technique show more and more insufficiency. In this dissertation, we aim at the feature of SEE under present semiconductor technology, and study the modeling and hardening of SEE thoroughly. The main works and contributions of the dissertation are as follows
1) We propose a novel SEU hardened storage cell. Base on the analysis of chare collection sensitive area and appropriate circuit design, a novel SEU hardening storage cell is presented, which can recovery automatically from single node upset. The storage cell can be fabricated in commercial CMOS process. Therefore it achieves low cost, low power, high speed and high integrity.
2) We study the charge sharing collection and its effect to storage cells. By three-dimensional device simulation method, we study the temperature dependency of charge sharing. The simulation results show that the charge sharing collection rise significantly with temperature rising. MBU in SRAM cells and MNU in hardened storage cells induced by charge sharing is analysed in detail. Furthermore, three methods to restrain charge sharing is presented: Enlarging the distance between sensitive nodes, insert guard ring and back-to-back layout style.
3) We propose a circuit level coupled SET pulse injection method. Traditional SET independent current source will introduce great error in ultra deep submicro technology. We explored the factors which affect the SET pulse shape and model the SET pulse as a two-dimension lookup table. This method is implemented in open sourced SPICE tool. This method is a well tradeoff between speed and accuracy comparing with independent models and circuit/device mix-mode simulation.
4) We propose the SET reconvegence analyse framework in combinational logic, SERAR. In SERAR, reconvergence is classified into 4 mode, ROR, RSUB, RAND and RXOR. For each mode, the sensitized condition based on Boolean difference is presented. Experiments on ISCAS’85 benchmark circuit show reconvergence has significant effect on SER and node sensitivity estimation.
5) We design a radiation hardened SRAM based on SOI technology. The design and implement of a 256 32 SRAM with full custom method based on 0.5 m PD SOI technology is described. We complete the whole flow including circuit design, layout design, timing modeling. For radiation hardening, besides the intrinsic ability of SOI, we employ the body tie to improve SEE sensitivity, and edgeless gate to improve TID sensitivity.
Finally we forecast the research area of SEE in the future.
引文
[1] www.aero.org/conferences/mrqw/2002-papers/A_Burcin.pdf
[2] Gaisler J. A portable fault-tolerant microprocessor based on the SPARC V8 architecture, In Proc. of the Conference on Data systems in aerospace (DASIA 99), May 1999, Lisbon, Portugal; NETHERLANDS: IEEE CS, 1999. 173~177
[3] Gaisler J. A portable and fault-tolerant microprocessor based on the SPARC v8 architecture, In Proc. of International Conference on Dependable Systems and Networks (DSN 2002), June 2002, Bethesda, MD, USA: IEEE CS, 2002. 409~ 415
[4] http://www.atmel.com/dyn/resources/prod_documents/doc4226.pdf
[5] focus.ti.com.cn/cn/lit/ml/sgzm004/sgzm004.pdf
[6] www.xilinx.com/support/documentation/data_sheets/ds028.pdf
[7] http://www.ssec.honeywell.com/aerospace/datasheets/ HXSR01608.pdf
[8] http://www.actel.com/products/milaero/rtaxs/default.aspx
[9]辛明瑞,面向空间应用的容错RISC处理器体系结构研究,博士学位论文,西北工业大学,2006
[10]邢克飞,王跃科,扈啸.银河飞腾DSP芯片总剂量辐照试验研究,半导体技术,31(7): 493-495, 2006年07期
[11]赖祖武等,抗辐照电子学——辐射效应及加固原理,北京,国防工业出版社,1998.7
[12] Ziegler J F. Terrestrial cosmic rays. IBM Journal of Research and Development, 1996, 40(1):19~39
[13]王长河,单粒子效应对卫星空间运行可靠性影响,半导体情报,1998,35(1):1～8
[14]贺朝会,单粒子研究的现状和动态,http://www.paper.edu.cn,2005
[15] Mavis D. G., Eaton. P. H., SEU and SET modeling and mitigation in deep submicron technologies IEEE 45th Annual International Reliability Physics Symposium, Phoenix, 2007
[16] C.Lage, D.Burnett, T.McNelly, K.Baker, A.Borman, D.Dreier, V.Soorhotz,“Soft Error Rate and Stored Charge Requirements in Advanced High-Density SRAMs,”1993 IEDM Technocal Digest, pp.821.
[17] E. Dupont, M. Nicolaidis, and P. Rohr. Embedded robustness IPs for transient error-free ICs. IEEE Design & Test of Computers, 19(3):56–70, May/June 2002.
[18] T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar. Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18μ. In Proc. Symp. VLSI Circ., pages 61–62, 2001.
[19] Shivakumar P, Kistler M, Keckler S W, et al. Modeling the Effect of TechnologyTrends on the Soft Error Rate of Combinational Logic. In Proc. of the 2002 International Conference on Dependable Systems and Networks (DSN 2002). Bethesda, MD, USA:IEEE CS, 2002. 389~398
[20] P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, and T. Turflinger,“Single event transient pulse width measurements using a variable temporal latch technique,”IEEE Trans. Nucl. Sci., vol. 51, pp. 3365–3368, Dec. 2004.
[21] Daniele Radaelli,“Investigation of Multi-Bit Upsets in a 150 nm Technology SRAM Device”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 52, NO. 6, DECEMBER 2005
[22] Y. Kawakami et al.,“Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3-D mixed-mode device simulation,”in Proc. IEDM, 2004, pp.945–948.
[23] A. M. Chugg,“A statistical technique to measure the proportion of MBU’s in SEE testing,”IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp.3139–3144, Dec. 2006.
[24] P. Hazucha, C. Svensson, Impact of CMOS technology scaling on the atmospheric neutron soft error rate, IEEE Transactions on Nuclear Science, Vol. 47, No. 6, July, 2000
[25] P. Hazucha, T. Karnik, J. Maiz, et al., Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25 m to 90nm generation, IEEE International Electron Devices Meeting (IEDM '03), 2003
[26] Grubin H L, Kreskovsky J P, and Weinberg B C. Numerical Studies of Charge Collection and Funneling in Silicon Device. IEEE Trans. Nuclear Science, 1984, 31(6):1161～1166
[27] Hu C.αParticle Induced Field Enhanced Collection of Carriers. IEEE E.D. Letters, 1982, 3(2):31～34
[28] Compbell A B, Knudson A R, Shapiro P, et al. Charge Collection in Test Structures. IEEE Trans. Nuclear Science 1983, 30(6): 44864492
[29] Hauser J R, Diehl-Nagle S E, Knudson A R, et al. Ion Track Shunt Effects in Multi-Junction Structures. IEEE Trans. Nuclear Science, 1985, 32(6): 4115～4121
[30] Y. Yanagawa, K. Hirose, H. Saito, et al., Direct Measurement of SET Pulse Widths in 0.2μm SOI Logic Cells Irradiated by Heavy Ions, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[31] D. Kobayashi, M. Aimi, H. Saito, et al., Time-Domain Component Analysis of Heavy-Ion-Induced Transient Currents in Fully-Depleted SOI MOSFETs, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[32] P.E. Dodd, et al.,“Production and propagation of single-event transients in high-speed digital logic ICs”, IEEE Trans. Nucl. Sci., VOL. 51, NO. 6, Dec. 2004
[33] V. Ferlet-Cavrois, P. Palliet, M. Gaillardin, D. Lambert, J. Baggio, J. R. Schwank, G. Vizkelethy, M. R. Shaneyfelt, K. Hirose, E. W. Blackmore, O. Faynot, C. Jahan, and L. Tosti,“Statistical analysis of the charge collected in soi and bulk devices under heavy lon and proton irradiation implications for digital SETs”, IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3242–3252, Dec. 2006.
[34] Zoutendyk J A, Schwartz H R, and Nevill L R. Lateral Charge Transport from Heavy-ion Tracks in Integrated Circuits. IEEE Trans. Nuclear Science, 1988, 35(6):1644～1647
[35] Zoutendyk J A, Edmonds L D, and Smith L S. Characterization of Multiple-bit errors from Single-ion Tracks in integrated circuits. IEEE Trans. Nuclear Science, 1989, 36(6):2267～2274
[36] Olson, B.D.; Ball, D.R.; Warren, K.M.; Massengill, L.W.; Haddad, N.F.; Doyle, S.E.; McMorrow, D., Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design, IEEE Transactions on Nuclear Science, Volume 52, Issue 6, Dec. 2005 Page(s): 2132– 2136
[37] Oluwole A. Amusan, Arthur F. Witulski, et al., Charge Collection and Charge Sharing in a 130 nm CMOS Technology, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[38] Sandeepan DasGupta,“Trends in Single Event Pulse Widths and Pulse Shapes in Deep Submicron CMOS”, Thesis for the Master Degree, Vanderbilt University, December, 2007
[39] Matthew J. Gadlage, Ronald D. Schrimpf, Balaji Narasimham, et al., Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[40] S. DasGupta, A. F. Witulski, Senior Member, B. L. Bhuva, et al., Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[41]温度对数字电路中单粒子瞬态脉冲的影响,2008年第29卷第7期,pp.1407~1411
[42] V. Ferlet-Cavrois, P. Paillet, D. McMorrow, et al., New Insights Into Single Event Transient Propagation in Chains of Inverters—Evidence for Propagation-Induced Pulse Broadening, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[43] K. Castellani-Coulié, D. Munteanu, J. L. Autran, et al., Analysis of 45-nm Multi- Gate Transistors Behavior Under Heavy Ion Irradiation by 3-D Device Simulation, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[44] Jain P., Vasi J., Lal R.K., SEU reliability analysis of advanced deep-submicron transistors, IEEE Transactions on Device and Materials Reliability, Vol.5, No.2, 2005, pp.289~295
[45] K. Blotekjaer,“Transport equations for electrons in two-valley semiconductors”, IEEE Trans. Electron Devices, vol. ED-17, pp. 38-47, 1970
[46]郭红霞,集成电路电离辐射效应数值模拟及X射线剂量增强效应研究,西安电子科技大学,博士学位论文,2000
[47] P.E. Dodd, et al.,“Charge collection and SEU from angled ion strikes”, IEEE Trans. Nucl. Sci., VOL.44, 1997
[48] K.Castellani, et al.,“Comparison of NMOS and PMOS transistor sensitivity to SEU in SRAMs by device simulation”, IEEE Trans. Nucl. Sci., VOL. 50, NO. 6, Dec. 2003
[49] P.E. Dodd, et al.,“SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments”, IEEE Trans. Nucl. Sci., VOL. 48, NO. 6, Dec. 2001
[50] Messenger G C,“Collection of Charge on Junction Nodes from Ion Tracks”, IEEE Trans Nuclear Science, 1982, 29(6):2024
[51] David E. Fulkerson and Harry Liu,“A Charge-Control SPICE Engineering Model for the, Parasitic Bipolar Transistor Action in SOI CMOS Single-Event Upsets”, IEEE Trans. Nucl. Sci., VOL.51, NO.1, February 2004.
[52] O.Musseau, J.L.Leray, V.Ferlet-Cavrois, Y.M.Coic, B.Giffard,“SEU in SOI SRAMs-a static model”, IEEE Trans. Nucl. Sci., VOL.41, NO.3, JUNE 1994
[53] J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Gadlage, and T. Turflinger, Variation of Digital SET Pulse Widths and the Implications for Single Event Hardening of Advanced CMOS Processes, IEEE Trans. Nucl. Sci., Vol. 52, No. 6, pp.2114-2119, Dec. 2005.
[54] M. Turowski, A. Raman, G. Jablonski, Mixed-Mode Simulation and Analysis of Digital Single Event Transients in Fast CMOSICs, 14th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES '07, pp.433-438, June 2007
[55] Daisuke Kobayashi, Hirobumi Saito, Kazuyuki, Hirose,“Estimation of Single Event Transient Voltage Pulses in VLSI Circuits From Heavy-Ion-Induced Transient Currents Measured in a Single MOSFET”, IEEE Trans. Nucl. Sci., vol.54, no.4, pp.1037~1041, Aug.2007.
[56] Daisuke Kobayashi, Kazuyuki Hirose, Takahiro Makino, et al,“Feasibility Study of a Table-Based SET-Pulse Estimation in Logic Cells From Heavy-Ion-Induced Transient Currents Measured in a Single MOSFET”, IEEE Trans. Nucl. Sci., vol.54, no.6, pp.2347~2354, Dec.2007.
[57] S.E. Kerns, Transient ionization and single event phenomena, Ionizing Radiation Effect in MOS Devices and Circuits, Wiley, New York, 1989
[58] P.E. Dodd, F.W. Sexton, Critical charge concepts for CMOS SRAMs, IEEE Trans.Nucl. Sci., vol.42, no.6, pp.1764~1771, Dec.1995.
[59]贺朝会,李国政,罗晋生,刘恩科,CMOS SRAM单粒子翻转效应的解析分析,半导体学报,第21卷第2期,2000年,pp.174~178
[60] P. C. Murley and G. R. Srinivasan,“Soft-error Monte Carlo modeling program, SEMM,”IBM J. Res. Develop., vol. 40, no. 1, pp. 109–118, Jan. 1996.
[61] S. Mitra, T. Karnik, N. Seifert, M. Zhang, Logic soft errors in sub-65nm technologies design and CAD challenges, DAC’05
[62] B. Zhang, W. S. Wang, and M. Orshansky, FASER Fast Analysis of Soft Error Susceptibility for Cell-Based Designs, IEEE Proc. ISQED, 2006.
[63] C. Zhao, X. Bai, and S. Dey,“A scalable soft spot analysis methodology for noise effects in nano-meter circuits,”in Proc. ACM/IEEE DAC, Jun. 2004, pp. 894–899.
[64] M. Zhang, et al, A Soft Error Rate Analysis (SERA) Methodology, Proc. ICCAD, pp.111-118, 2004.
[65] Ghazanfar Asadi, Mehdi B.Tahoori, An Accurate SER Estimation Method Based on Propagation Probability, DATE 2005.
[66] Natasa Miskov-Zivanov, Diana Marculescu, MARS-C Modeling and Reduction of Soft Errors in Combinational Circuits”, IEEE Proc. DAC, 2006.
[67] Natasa Miskov-Zivanov, Diana Marculescu, Soft Error Rate Analysis for Sequential Circuits, DATE, 2007.
[68] M.Omana, G. Papasso, D. Rossi, and C. Metra. A Model for Transient Fault Propagation in Combinatorial Logic. In Proc. of IEEE International On-Line Testing Symposium, IOLTS'03, 2003. July. pp.111-115
[69] Feng Wang, Yuan Xie, R. Rajaraman and B. Vaidyanathan, Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model, 20th International Conference on VLSI Design (VLSID’07), 2007
[70] Giacinto P. Saggese, Nicholas J. Wang, Zbigniew T., Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer, An Experimental Study of Soft Errors in Microprocessors, IEEE MICRO, NOVEMBER~DECEMBER, pp30~39, 2005
[71] H. T. Nguyen, Y. Yagil, N. Seifert, and M. Reitsma, Chip-level soft error estimation method, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005, pp365~381
[72] E.Jenn, J. Arlat, et al., Fault Injection into VHDL Models: The MEFISTO Tool, FTCS-24, 1994
[73] VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions 1997
[74] H. R. Zarandi, S. G. Miremadi, A. Ejlali, Fault injection into verilog models for dependability evaluation of digital systems, ISPA’03, 2003
[75] Dependability analysis using a fault injection tool based on synthesizability of HDLmodels 2003
[76] S. Kim and A. K. Somani,“Soft error sensitivity characterization for microprocessor dependability enhancement strategy,”in Proc. Int. Conf. Dependable Systems and Networks (DSN), Washington, DC, 2002, pp. 416–425.
[77] M. Rebaudengo, M. S. Reorda, M. Violante,“An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor”, The Design, Automation and Test in Europe Conference (DATE’03), 2003
[78]黄海林,唐志敏,许彤,“龙芯1号处理器的故障注入方法与软错误敏感性分析”,计算机研究与发展,第43卷,第10期,2006年10月,pp.1820~1827
[79] S.S.Mukherjee, C.Weaver, J.Emer, S.K.Reinhardt, and T.Austin. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. MICRO-36, pages29~40, Dec.2003
[80] Arijit Biswas, Paul Racunas, Joel Emer and Shubhendu S. Mukherjee, Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal, IEEE Computer Architecture Letters, 17 Dec 2007.
[81] N. Wang, A. Mahesri, S.J. Patel,“Examining ACE Analysis Reliability Estimates Using Fault-Injection”, 34th Annual International Symposium on Computer Architecture (ISCA), 2007
[82] Wei Zhang, Computing cache vulnerability to transient errors and its implication, the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05), 2005
[83] A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S.S. Mukherjee, R. Rangan, "Computing Architectural Vulnerability Factors for Address-Based Structures", 32nd Annual International Symposium on Computer Architecture (ISCA), 2005
[84] Kristen R.Walcott, Greg Humphreys, Sudhanva Gurumurthi, Vulnerabilities Dynamic prediction of architectural vulnerability from microarchitectural state, 32nd Annual International Symposium on Computer Architecture (ISCA), 2007, California, USA
[85] J. E. Lilienfeld,“Method and Apparatus for Controlling Electric Currents (Filed in 1926, Issued in 1930),“Device for Controlling Electric Current”(Filed in 1928, Issued in 1933),“Amplifier for Electric Current”(Filed in 1928, Issued in 1932),”U.S. Patents 1 745 175, 1 900 018, 1 877 140.
[86] H.M.Manasevit andW. I. Simpson,“Single-crystal silicon on a sapphire substrate,”J. Appl. Phys., vol. 35, p. , 1964.
[87]黄如,张兴,张国艳,李映雪,SOI CMOS技术及其应用,北京,科学出版社,2005年9月
[88] G. E. Davis, L. R. Hite, T. G.W. Blake, C. -E. Chen, H.W. Lam, and R. DeMoyer Jr,“Transient radiation effects in SOImemories,”IEEE Trans. Nucl. Sci., vol. 32,no. 6, pp. 4432–4437, Dec. 1985.
[89] L. W. Massengill, D. V. Kerns Jr, S. E. Kerns, and M. L. Alles,“Single event charge enhancement in SOI devices,”IEEE Electron Dev. Lett., vol. 11, no. 2, pp. 98–99, Feb. 1990.
[90] C. Brisset, P. Dollfus, O. Musseau, J. Leray, and P. Hesto,“Theoretical study of SEUS in 0.25 m fully-depleted CMOS/SOI technology,”IEEE Trans. Nucl. Sci., vol. 41, pp. 2293–2113, Dec. 1992.
[91] L. R. Hite, H. Lu, T. W. Houston, D. S. Hurta, and W. E. Bailey, An SEU resistant 256 K SOI SRAM,”IEEE Trans. Nucl. Sci., vol. 39, pp.2121–2125, Dec. 1992
[92] S. E. Kerns, L. W. Massengill, D. V. Kerns Jr, J. M. L. Alles, T. W.Houston, H. Lu, and L. R.Hite,“Model for CMOS/SOI single-event vulnerability,”IEEE Trans. Nucl. Sci., vol. 36, pp. 2305–2310, Dec. 1989
[93] F. W. Sexton,“Measurement of single event phenomena in devices and IC’s,”in 1992 IEEE Nuclear Space Radiation Effects Conf. Short Course, New Orleans, LA, pp. III-1–III-55.
[94] D. Binder, E. C. Smith, and A. B. Holman,“Satellite anomalies from galactic cosmic rays,”IEEE Trans. Nucl. Sci., vol. 22, pp. 2675–2680, Dec. 1975.
[95] P. E. Dodd, M. R. Shaneyfelt, J. R. Schwank, G. L. Hash, B. L. Draper, and P. S. Winokur,“Single-event upset and snapback in silicon-on-in-sulator devices,”IEEE Trans. Nucl. Sci., vol. 47, pp. 2165–2174, Dec.2000.
[96] P. E. Dodd, M. R. Shaneyfelt, K. M. Horn, D. S. Walsh, G. L. Hash, T. A. Hill, B. L. Draper, J. R. Schwank, F. W. Sexton, and P. S. Winokur,“SEU-sensitive volumes in bulk and SOI SRAM’s from first-principles calculations and experiments,”IEEE Trans. Nucl. Sci., vol. 48, pp.1893–1903, Dec. 2001
[97] K. Hirose, H. S. M. Akiyama, M. Arakaki, Y. Kuroda, S. Ishii, and K. Nakano,“Total-dose and single-event upset resistance in advanced SRAM’s fabricated on SOI using 0.2 m design rules,”in 2001 IEEE Radiation Effects Data Workshop Rec., Vancouver, BC, Canada, July 2001, pp. 48–50.
[98] J. R. Schwank, P. E.Dodd, M. R. Shaneyfelt,G.Vizkelethy, B. L.Draper, T. A. Hill, D. S. Walsh, and G. L. Hash,“Anomalous charge collection from SOI circuits and its effect on SEU hardness,”IEEE Trans. Nucl. Sci., vol. 49, pp. 2937–2947, Dec. 2002.
[99] S. E. Kerns, and B.D. Shafer.The Design of Radiation-Hardened Ics for Space:A Compendium of Approaches Proceedings of the IEEE, Vo1.76(11), pp.1470-1508,November,1988.
[100] L.R.Rockett, Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors, IEEE Trans. Nucl. Sci., VOL. 39, 1992
[101] L. R. Hite, H. Lu, T. W. Houston, et al. An SEU resistant 256k SOI SRAM. IEEE Transactions on Nuclear Science. 1992, 39(6): 2121-2125
[102] L.Rockett, et al., An SEU-hardened CMOS data latch design, IEEE Transactions on Nuclear Science, vol. 35, pp. 1682-1687, December 1988.
[103] S.Whitaker, J.Canaris, K.Liu. SEU Hardened Memory Cells for a CCSDS Reed Solomn Encoder. IEEE Trans. Nucl. Sci. 1991.12, 38(6): 1471-1477.
[104] M.N.Liu, S.Whitaker. Low Power SEU Immune CMOS Memory Circuits. IEEE Trans. Nucl. Sci. 1992.12, 39(6): 1679-1684.
[105] D.Bessot, R.Velazco. Design of SEU-Hardened CMOS Memory Cells: The HIT Cell, the 2nd European Conference Radiation and Its Effects on Components and Systems. 1993: 563-570.
[106] R.Velazco, D.Bessot. Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits. IEEE Trans. Nucl. Sci. 1994.12, 41(6): 2229-2234.
[107] N. Haddad, et al. Design Considerations for Next Generation Radiation Hardened SRAMs for Space Applications.IEEE Conference on Aerospace, 2005, pp1-6
[108] T.Calin, M.Nicolaidis, R.Velazco. Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Trans. Nucl. Sci. 1996.12, 43(6): 2874-2878.
[109]一种低功耗的SEU加固存储单元,半导体学报,2007年第28卷第5期,pp.755-758
[110] R.Velazco, T.Calin, M.Nicolaidis, et al. SEU-Hardened Storage Cell Validation Using a Pulsed Laser. IEEE Trans. Nucl. Sci. 1996.12, 43(6).
[111] Oluwole A. Amusan, Lloyd W. Massengill, et al., Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[112] Multiple Node Upset in SEU Hardened Storage Cells, Chinese Journal of Semiconductor, Vol.29, No.2, 2008, pp.244~250
[113] Pitsini Mongkolkachit and Bharat Bhuva,“Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic”, IEEE Transactions on Device and Materials Reliability, Vol.29. , No.3, 2003
[114] M. C. Casey, B. L. Bhuva, J. D. Black, et al., HBD Using Cascode-Voltage Switch Logic Gates for SET Tolerant Digital Designs, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2005
[115] Yoichi SASAKI, Kazuteru NAMBA, Hideo ITO, Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit, the 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006
[116] Rajesh Garg, Nikhil Jayakumar, A design approach for radiation-hard digital electronics, DAC, 2006
[117] Michels,á., Petroli, L., Lisb?a, C. A. L., Kastensmidt, F. and Carro, L. SET Fault Tolerant Combinational Circuits Based on Majority Logic, the 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006
[118] D.Mavis and P. Eaton,“Soft error rate mitigation techniques for modern microcircuits”40th Annu. IEEE Int. Reliabilitiy Physics Symp. (IRPS), Dallas, TX, 2002, pp. 216–225.
[119] J. E. Knudsen, L. T. Clark An Area and Power Efficient Radiation Hardened by Design Flip-Flop, IEEE Transactions on Nuclear Science Volume 53, Issue 6, Dec. 2006 Page(s):3392 - 3399
[120] Kartik Mohanram, Nur A. Touba, Partial Error Masking Reduce Soft Error Failure Rate in Logic Circuits, the 18th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’03), 2003
[121] Quming Zhou, Kartik Mohanram, Cost-effective radiation hardening technique for combinational logic, IEEE International Conference on Computer Aided Design (ICCAD), 2004
[122] J. H. Patel and L. Y. Fung,“Concurrent error detection in ALUs by recomputing with shifted operands,”IEEE Trans. Comput., vol. C-31, no. 7, pp. 589–595, Jul. 1982.
[123] N. Oh, P.P. Shirvani, and E.J. McCluskey,“Error Detection by Duplicated Instructions in Super-Scalar Processors,”IEEE Trans. Reliability, vol. 51, no. 1, Mar. 2002, pp. 63-75.
[124] N. Oh, S. Mitra, E.J. McCluskey, ED4I: Error Detection by Diverse Data and Duplicated Instructions, IEEE Transactions on Computer, February 2002 (Vol. 51, No. 2) , pp. 180-199
[125] J. Ray, J.C. Hoe, and B. Falsafi,“Dual Use of Superscalar Datapath for ransient-Fault Detection and Recovery,”Proc. 34th Ann. Int’l Symp. Microarchitecture (Micro-34), IEEE Press, 2001, pp. 214-224.
[126] Todd M. Austin, DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, the 32nd Annual International Symposium on Microarchitecture (MICRO), 1999.
[127] E.Rotenberg, AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In Proceedings of the 29th Fault-Tolerant Computing Symposium, June 1999.
[128] Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi, Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures, International Symposium on Microarchitecture (MICRO), 2004
[129] T.N. Vijaykumar, I. Pomeranz, and K. Cheng,“Transient-Fault Recovery Using Simultaneous Multithreading,”Proc. 29th Ann. Int’l Symp. ComputerArchitecture (ISCA 02), IEEE Press, 2002, pp. 87-98.
[130] S. Mukherjee, M. Kontz, and S. Reinhardt. Detailed Design and Evaluation of Redundant Multithreading Alternatives. In International Symposium on Computer Architecture (ISCA), pages 99–110, May 2002.
[131] A. Parashar, S. Gurumurthi, and A. Sivasubramaniam. A Complexity-E?ective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 376–386, June 2004.
[132] M. A. Gomaa and T. N. Vijaykumar. Opportunistic transient-fault detection. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 172–183, 2005.
[133]江建慧,员春欣,“芯片级系统的在线测试技术”,计算机研究与发展,第41卷,第9期,2004年9月,pp.1593~1603
[134] Wei Zhang, Enhancing Data Cache Reliability by the Addition of a Small Fully-Associative Replication Cache, 18th Annual ACM International Conference on Supercomputing (ICS), 2004
[135] Pablo Montesinos, Wei Liu and Josep Torrellas, Using Register Lifetime Predictions to Protect Register Files against Soft Errors, 37th International Conference on Dependable Systems and Networks (DSN’07), 2007
[136] Wei Zhang, Sudhanva Gurumurthi, Mahmut Kandemir, Anand Sivasubramaniam, ICR:In-Cache Replication for Enhancing Data Cache Reliability, International Conference on Dependable Systems and Networks (DSN’03), 2003
[137] Vilas Sridharan, Hossein Asadi, Mehdi B. Tahoori, David Kaeli, Reducing Data Cache Susceptibility to Soft Errors, IEEE Transactions on Dependable and Secure Computing, Col.3, No.4, October~December, 2006
[138] Jie Hu, Shuai Wang, and Sotirios G. Ziavras, In-Register Duplication Exploiting Narrow-Width Value for Improving Register File Reliability, 36th International Conference on Dependable Systems and Networks (DSN’06) , 2006
[139] D.Wiseman, J.Canaris, S.Whitaker. Design and Testing of SEU/SEL Immune Memory and Logic Circuits in a Commercial CMOS Process. NSREC Workshop. 1993.7.
[140]刘恩科,朱秉升,罗晋生等,半导体物理学(第6版),电子工业出版社,2003,北京
[141] T. Quarles, Adding Devices to SPICE3, U. C. Berkeley, Technical Report, ERL-89-45, 1989
[142] F.Somenzi, CUDD: The CU decision diagram package (version2.4.1), Boulder, CO: Dept. Electr. Comput. Eng. Univ. Colorado, [Online]. http://vlsi.colorado.edu/fabio/CUDD, May2005.
[143]边计年,薛洪熙,苏明等,数字系统设计自动化(第2版),清华大学出版社,北京,2005.7
[144] http://www.eecs.umich.edu/~jhayes/iscas.restore/benchmark.html
[145] Lu H., Yee E, Hite L., et al. 1-M bit SRAM on SIMOX material, Proc IEEE Int SOI Conf, 1993:182
[146] http://www.ssec.honeywell.com/aerospace/datesheets/HLX6256.pdf
[147]刘新宇,孙海峰,刘洪民等,CMOS/SOI 4Kb静态随机存储器,功能材料与器件学报,第8卷第2期,2002年6月,pp.165~169
[148]刘新宇,韩郑生,周小茵等,CMOS/SOI 64Kb静态随机存储器,半导体学报,第22卷第1期,2001年1月,pp.47~52
[149]赵凯,刘忠立,于芳,高见头,肖志强,洪根深,抗辐照128Kb PD SOI静态随机存储器,半导体学报,第28卷第7期,2007年7月,pp 1139~1143
[150] Ferlet-Cavrois, V. Colladant, T. Paillet, P. Leray, J.L. Musseau, O. Schwank, J.R. Shaneyfelt, M.R. Pelloie, J.L. du Port de Poncharra, J. CEA, Centre d'Etudes de Bruyeres-le-Chatel; Worst-case bias during total dose irradiation of SOI transistors, IEEE Transactions on Nuclear Science, 2000, Vol.47 (6), pp 2183 ~ 2188.
[151] G. Gasiot, D. Giot, and P. Roche,“Well Engineering Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering”, IEEE Transactions on Nuclear Science, Volume 54, Issue 6, Part 1, Dec. 2007 Page(s):2468 - 2473
[152] D. Giot, Philippe Roche, Gilles Gasiot, and Reno Harboe-S?rensen, Multiple-Bit Upset Analysis in 90 nm SRAMs: Heavy Ions Testing and 3D Simulations, IEEE Transactions on Nuclear Science, Vol. 54, No. 4, August 2007
[153] D. Giot, Philippe Roche, Gilles Gasiot, Jean-Luc Autran, and Reno Harboe-S?rensen, Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs, IEEE Transactions on Nuclear Science, Vol. 55, No. 4, August 2007
[154] M. L. Alles, L. W. Masengill, S. E. Kerns, K. L. Jones, J. E. Clark, W. F. Kraus,“Effect of Temperature-Dependent Bipolar Gain Distribution on SEU Vulnerability of SOI CMOS SRAMs,”IEEE Proc. Int. SOI Conf., pp. 96-97, Oct. 1992.
[155] D. Truyen, J. Boch, B. Sagnes, N. Renaud, E. Leduc, S. Arnal, and F. Saigné,“Temperature Effect on Heavy-Ion Induced Parasitic Current on SRAM by Device Simulation: Effect on SEU Sensitivity,”IEEE Tran. Nucl. Sci., vol. 54, no. 4, pp. 1025-1029, Aug. 2007.
[156] M. S. Tyagi and R. van Overstraeten,“Minority carrier recombination in heavily-doped Silicon,”Solid State Electronics, vol. 26, no. 6, pp. 577–597, 1983.
[157] Sentaurus Device User Guide version A-2007.12-SP1, Synopsys, Dec.2007.
[2] Gaisler J. A portable fault-tolerant microprocessor based on the SPARC V8 architecture, In Proc. of the Conference on Data systems in aerospace (DASIA 99), May 1999, Lisbon, Portugal; NETHERLANDS: IEEE CS, 1999. 173~177
[3] Gaisler J. A portable and fault-tolerant microprocessor based on the SPARC v8 architecture, In Proc. of International Conference on Dependable Systems and Networks (DSN 2002), June 2002, Bethesda, MD, USA: IEEE CS, 2002. 409~ 415
[4] http://www.atmel.com/dyn/resources/prod_documents/doc4226.pdf
[5] focus.ti.com.cn/cn/lit/ml/sgzm004/sgzm004.pdf
[6] www.xilinx.com/support/documentation/data_sheets/ds028.pdf
[7] http://www.ssec.honeywell.com/aerospace/datasheets/ HXSR01608.pdf
[8] http://www.actel.com/products/milaero/rtaxs/default.aspx
[9]辛明瑞,面向空间应用的容错RISC处理器体系结构研究,博士学位论文,西北工业大学,2006
[10]邢克飞,王跃科,扈啸.银河飞腾DSP芯片总剂量辐照试验研究,半导体技术,31(7): 493-495, 2006年07期
[11]赖祖武等,抗辐照电子学——辐射效应及加固原理,北京,国防工业出版社,1998.7
[12] Ziegler J F. Terrestrial cosmic rays. IBM Journal of Research and Development, 1996, 40(1):19~39
[13]王长河,单粒子效应对卫星空间运行可靠性影响,半导体情报,1998,35(1):1～8
[14]贺朝会,单粒子研究的现状和动态,http://www.paper.edu.cn,2005
[15] Mavis D. G., Eaton. P. H., SEU and SET modeling and mitigation in deep submicron technologies IEEE 45th Annual International Reliability Physics Symposium, Phoenix, 2007
[16] C.Lage, D.Burnett, T.McNelly, K.Baker, A.Borman, D.Dreier, V.Soorhotz,“Soft Error Rate and Stored Charge Requirements in Advanced High-Density SRAMs,”1993 IEDM Technocal Digest, pp.821.
[17] E. Dupont, M. Nicolaidis, and P. Rohr. Embedded robustness IPs for transient error-free ICs. IEEE Design & Test of Computers, 19(3):56–70, May/June 2002.
[18] T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar. Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18μ. In Proc. Symp. VLSI Circ., pages 61–62, 2001.
[19] Shivakumar P, Kistler M, Keckler S W, et al. Modeling the Effect of TechnologyTrends on the Soft Error Rate of Combinational Logic. In Proc. of the 2002 International Conference on Dependable Systems and Networks (DSN 2002). Bethesda, MD, USA:IEEE CS, 2002. 389~398
[20] P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, and T. Turflinger,“Single event transient pulse width measurements using a variable temporal latch technique,”IEEE Trans. Nucl. Sci., vol. 51, pp. 3365–3368, Dec. 2004.
[21] Daniele Radaelli,“Investigation of Multi-Bit Upsets in a 150 nm Technology SRAM Device”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 52, NO. 6, DECEMBER 2005
[22] Y. Kawakami et al.,“Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3-D mixed-mode device simulation,”in Proc. IEDM, 2004, pp.945–948.
[23] A. M. Chugg,“A statistical technique to measure the proportion of MBU’s in SEE testing,”IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp.3139–3144, Dec. 2006.
[24] P. Hazucha, C. Svensson, Impact of CMOS technology scaling on the atmospheric neutron soft error rate, IEEE Transactions on Nuclear Science, Vol. 47, No. 6, July, 2000
[25] P. Hazucha, T. Karnik, J. Maiz, et al., Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25 m to 90nm generation, IEEE International Electron Devices Meeting (IEDM '03), 2003
[26] Grubin H L, Kreskovsky J P, and Weinberg B C. Numerical Studies of Charge Collection and Funneling in Silicon Device. IEEE Trans. Nuclear Science, 1984, 31(6):1161～1166
[27] Hu C.αParticle Induced Field Enhanced Collection of Carriers. IEEE E.D. Letters, 1982, 3(2):31～34
[28] Compbell A B, Knudson A R, Shapiro P, et al. Charge Collection in Test Structures. IEEE Trans. Nuclear Science 1983, 30(6): 44864492
[29] Hauser J R, Diehl-Nagle S E, Knudson A R, et al. Ion Track Shunt Effects in Multi-Junction Structures. IEEE Trans. Nuclear Science, 1985, 32(6): 4115～4121
[30] Y. Yanagawa, K. Hirose, H. Saito, et al., Direct Measurement of SET Pulse Widths in 0.2μm SOI Logic Cells Irradiated by Heavy Ions, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[31] D. Kobayashi, M. Aimi, H. Saito, et al., Time-Domain Component Analysis of Heavy-Ion-Induced Transient Currents in Fully-Depleted SOI MOSFETs, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[32] P.E. Dodd, et al.,“Production and propagation of single-event transients in high-speed digital logic ICs”, IEEE Trans. Nucl. Sci., VOL. 51, NO. 6, Dec. 2004
[33] V. Ferlet-Cavrois, P. Palliet, M. Gaillardin, D. Lambert, J. Baggio, J. R. Schwank, G. Vizkelethy, M. R. Shaneyfelt, K. Hirose, E. W. Blackmore, O. Faynot, C. Jahan, and L. Tosti,“Statistical analysis of the charge collected in soi and bulk devices under heavy lon and proton irradiation implications for digital SETs”, IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3242–3252, Dec. 2006.
[34] Zoutendyk J A, Schwartz H R, and Nevill L R. Lateral Charge Transport from Heavy-ion Tracks in Integrated Circuits. IEEE Trans. Nuclear Science, 1988, 35(6):1644～1647
[35] Zoutendyk J A, Edmonds L D, and Smith L S. Characterization of Multiple-bit errors from Single-ion Tracks in integrated circuits. IEEE Trans. Nuclear Science, 1989, 36(6):2267～2274
[36] Olson, B.D.; Ball, D.R.; Warren, K.M.; Massengill, L.W.; Haddad, N.F.; Doyle, S.E.; McMorrow, D., Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design, IEEE Transactions on Nuclear Science, Volume 52, Issue 6, Dec. 2005 Page(s): 2132– 2136
[37] Oluwole A. Amusan, Arthur F. Witulski, et al., Charge Collection and Charge Sharing in a 130 nm CMOS Technology, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[38] Sandeepan DasGupta,“Trends in Single Event Pulse Widths and Pulse Shapes in Deep Submicron CMOS”, Thesis for the Master Degree, Vanderbilt University, December, 2007
[39] Matthew J. Gadlage, Ronald D. Schrimpf, Balaji Narasimham, et al., Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[40] S. DasGupta, A. F. Witulski, Senior Member, B. L. Bhuva, et al., Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[41]温度对数字电路中单粒子瞬态脉冲的影响,2008年第29卷第7期,pp.1407~1411
[42] V. Ferlet-Cavrois, P. Paillet, D. McMorrow, et al., New Insights Into Single Event Transient Propagation in Chains of Inverters—Evidence for Propagation-Induced Pulse Broadening, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[43] K. Castellani-Coulié, D. Munteanu, J. L. Autran, et al., Analysis of 45-nm Multi- Gate Transistors Behavior Under Heavy Ion Irradiation by 3-D Device Simulation, IEEE Transactions on Nuclear Science, Vol. 53, No. 6, 2006
[44] Jain P., Vasi J., Lal R.K., SEU reliability analysis of advanced deep-submicron transistors, IEEE Transactions on Device and Materials Reliability, Vol.5, No.2, 2005, pp.289~295
[45] K. Blotekjaer,“Transport equations for electrons in two-valley semiconductors”, IEEE Trans. Electron Devices, vol. ED-17, pp. 38-47, 1970
[46]郭红霞,集成电路电离辐射效应数值模拟及X射线剂量增强效应研究,西安电子科技大学,博士学位论文,2000
[47] P.E. Dodd, et al.,“Charge collection and SEU from angled ion strikes”, IEEE Trans. Nucl. Sci., VOL.44, 1997
[48] K.Castellani, et al.,“Comparison of NMOS and PMOS transistor sensitivity to SEU in SRAMs by device simulation”, IEEE Trans. Nucl. Sci., VOL. 50, NO. 6, Dec. 2003
[49] P.E. Dodd, et al.,“SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments”, IEEE Trans. Nucl. Sci., VOL. 48, NO. 6, Dec. 2001
[50] Messenger G C,“Collection of Charge on Junction Nodes from Ion Tracks”, IEEE Trans Nuclear Science, 1982, 29(6):2024
[51] David E. Fulkerson and Harry Liu,“A Charge-Control SPICE Engineering Model for the, Parasitic Bipolar Transistor Action in SOI CMOS Single-Event Upsets”, IEEE Trans. Nucl. Sci., VOL.51, NO.1, February 2004.
[52] O.Musseau, J.L.Leray, V.Ferlet-Cavrois, Y.M.Coic, B.Giffard,“SEU in SOI SRAMs-a static model”, IEEE Trans. Nucl. Sci., VOL.41, NO.3, JUNE 1994
[53] J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Gadlage, and T. Turflinger, Variation of Digital SET Pulse Widths and the Implications for Single Event Hardening of Advanced CMOS Processes, IEEE Trans. Nucl. Sci., Vol. 52, No. 6, pp.2114-2119, Dec. 2005.
[54] M. Turowski, A. Raman, G. Jablonski, Mixed-Mode Simulation and Analysis of Digital Single Event Transients in Fast CMOSICs, 14th International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES '07, pp.433-438, June 2007
[55] Daisuke Kobayashi, Hirobumi Saito, Kazuyuki, Hirose,“Estimation of Single Event Transient Voltage Pulses in VLSI Circuits From Heavy-Ion-Induced Transient Currents Measured in a Single MOSFET”, IEEE Trans. Nucl. Sci., vol.54, no.4, pp.1037~1041, Aug.2007.
[56] Daisuke Kobayashi, Kazuyuki Hirose, Takahiro Makino, et al,“Feasibility Study of a Table-Based SET-Pulse Estimation in Logic Cells From Heavy-Ion-Induced Transient Currents Measured in a Single MOSFET”, IEEE Trans. Nucl. Sci., vol.54, no.6, pp.2347~2354, Dec.2007.
[57] S.E. Kerns, Transient ionization and single event phenomena, Ionizing Radiation Effect in MOS Devices and Circuits, Wiley, New York, 1989
[58] P.E. Dodd, F.W. Sexton, Critical charge concepts for CMOS SRAMs, IEEE Trans.Nucl. Sci., vol.42, no.6, pp.1764~1771, Dec.1995.
[59]贺朝会,李国政,罗晋生,刘恩科,CMOS SRAM单粒子翻转效应的解析分析,半导体学报,第21卷第2期,2000年,pp.174~178
[60] P. C. Murley and G. R. Srinivasan,“Soft-error Monte Carlo modeling program, SEMM,”IBM J. Res. Develop., vol. 40, no. 1, pp. 109–118, Jan. 1996.
[61] S. Mitra, T. Karnik, N. Seifert, M. Zhang, Logic soft errors in sub-65nm technologies design and CAD challenges, DAC’05
[62] B. Zhang, W. S. Wang, and M. Orshansky, FASER Fast Analysis of Soft Error Susceptibility for Cell-Based Designs, IEEE Proc. ISQED, 2006.
[63] C. Zhao, X. Bai, and S. Dey,“A scalable soft spot analysis methodology for noise effects in nano-meter circuits,”in Proc. ACM/IEEE DAC, Jun. 2004, pp. 894–899.
[64] M. Zhang, et al, A Soft Error Rate Analysis (SERA) Methodology, Proc. ICCAD, pp.111-118, 2004.
[65] Ghazanfar Asadi, Mehdi B.Tahoori, An Accurate SER Estimation Method Based on Propagation Probability, DATE 2005.
[66] Natasa Miskov-Zivanov, Diana Marculescu, MARS-C Modeling and Reduction of Soft Errors in Combinational Circuits”, IEEE Proc. DAC, 2006.
[67] Natasa Miskov-Zivanov, Diana Marculescu, Soft Error Rate Analysis for Sequential Circuits, DATE, 2007.
[68] M.Omana, G. Papasso, D. Rossi, and C. Metra. A Model for Transient Fault Propagation in Combinatorial Logic. In Proc. of IEEE International On-Line Testing Symposium, IOLTS'03, 2003. July. pp.111-115
[69] Feng Wang, Yuan Xie, R. Rajaraman and B. Vaidyanathan, Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model, 20th International Conference on VLSI Design (VLSID’07), 2007
[70] Giacinto P. Saggese, Nicholas J. Wang, Zbigniew T., Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer, An Experimental Study of Soft Errors in Microprocessors, IEEE MICRO, NOVEMBER~DECEMBER, pp30~39, 2005
[71] H. T. Nguyen, Y. Yagil, N. Seifert, and M. Reitsma, Chip-level soft error estimation method, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005, pp365~381
[72] E.Jenn, J. Arlat, et al., Fault Injection into VHDL Models: The MEFISTO Tool, FTCS-24, 1994
[73] VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions 1997
[74] H. R. Zarandi, S. G. Miremadi, A. Ejlali, Fault injection into verilog models for dependability evaluation of digital systems, ISPA’03, 2003
[75] Dependability analysis using a fault injection tool based on synthesizability of HDLmodels 2003
[76] S. Kim and A. K. Somani,“Soft error sensitivity characterization for microprocessor dependability enhancement strategy,”in Proc. Int. Conf. Dependable Systems and Networks (DSN), Washington, DC, 2002, pp. 416–425.
[77] M. Rebaudengo, M. S. Reorda, M. Violante,“An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor”, The Design, Automation and Test in Europe Conference (DATE’03), 2003
[78]黄海林,唐志敏,许彤,“龙芯1号处理器的故障注入方法与软错误敏感性分析”,计算机研究与发展,第43卷,第10期,2006年10月,pp.1820~1827
[79] S.S.Mukherjee, C.Weaver, J.Emer, S.K.Reinhardt, and T.Austin. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. MICRO-36, pages29~40, Dec.2003
[80] Arijit Biswas, Paul Racunas, Joel Emer and Shubhendu S. Mukherjee, Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal, IEEE Computer Architecture Letters, 17 Dec 2007.
[81] N. Wang, A. Mahesri, S.J. Patel,“Examining ACE Analysis Reliability Estimates Using Fault-Injection”, 34th Annual International Symposium on Computer Architecture (ISCA), 2007
[82] Wei Zhang, Computing cache vulnerability to transient errors and its implication, the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05), 2005
[83] A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S.S. Mukherjee, R. Rangan, "Computing Architectural Vulnerability Factors for Address-Based Structures", 32nd Annual International Symposium on Computer Architecture (ISCA), 2005
[84] Kristen R.Walcott, Greg Humphreys, Sudhanva Gurumurthi, Vulnerabilities Dynamic prediction of architectural vulnerability from microarchitectural state, 32nd Annual International Symposium on Computer Architecture (ISCA), 2007, California, USA
[85] J. E. Lilienfeld,“Method and Apparatus for Controlling Electric Currents (Filed in 1926, Issued in 1930),“Device for Controlling Electric Current”(Filed in 1928, Issued in 1933),“Amplifier for Electric Current”(Filed in 1928, Issued in 1932),”U.S. Patents 1 745 175, 1 900 018, 1 877 140.
[86] H.M.Manasevit andW. I. Simpson,“Single-crystal silicon on a sapphire substrate,”J. Appl. Phys., vol. 35, p. , 1964.
[87]黄如,张兴,张国艳,李映雪,SOI CMOS技术及其应用,北京,科学出版社,2005年9月
[88] G. E. Davis, L. R. Hite, T. G.W. Blake, C. -E. Chen, H.W. Lam, and R. DeMoyer Jr,“Transient radiation effects in SOImemories,”IEEE Trans. Nucl. Sci., vol. 32,no. 6, pp. 4432–4437, Dec. 1985.
[89] L. W. Massengill, D. V. Kerns Jr, S. E. Kerns, and M. L. Alles,“Single event charge enhancement in SOI devices,”IEEE Electron Dev. Lett., vol. 11, no. 2, pp. 98–99, Feb. 1990.
[90] C. Brisset, P. Dollfus, O. Musseau, J. Leray, and P. Hesto,“Theoretical study of SEUS in 0.25 m fully-depleted CMOS/SOI technology,”IEEE Trans. Nucl. Sci., vol. 41, pp. 2293–2113, Dec. 1992.
[91] L. R. Hite, H. Lu, T. W. Houston, D. S. Hurta, and W. E. Bailey, An SEU resistant 256 K SOI SRAM,”IEEE Trans. Nucl. Sci., vol. 39, pp.2121–2125, Dec. 1992
[92] S. E. Kerns, L. W. Massengill, D. V. Kerns Jr, J. M. L. Alles, T. W.Houston, H. Lu, and L. R.Hite,“Model for CMOS/SOI single-event vulnerability,”IEEE Trans. Nucl. Sci., vol. 36, pp. 2305–2310, Dec. 1989
[93] F. W. Sexton,“Measurement of single event phenomena in devices and IC’s,”in 1992 IEEE Nuclear Space Radiation Effects Conf. Short Course, New Orleans, LA, pp. III-1–III-55.
[94] D. Binder, E. C. Smith, and A. B. Holman,“Satellite anomalies from galactic cosmic rays,”IEEE Trans. Nucl. Sci., vol. 22, pp. 2675–2680, Dec. 1975.
[95] P. E. Dodd, M. R. Shaneyfelt, J. R. Schwank, G. L. Hash, B. L. Draper, and P. S. Winokur,“Single-event upset and snapback in silicon-on-in-sulator devices,”IEEE Trans. Nucl. Sci., vol. 47, pp. 2165–2174, Dec.2000.
[96] P. E. Dodd, M. R. Shaneyfelt, K. M. Horn, D. S. Walsh, G. L. Hash, T. A. Hill, B. L. Draper, J. R. Schwank, F. W. Sexton, and P. S. Winokur,“SEU-sensitive volumes in bulk and SOI SRAM’s from first-principles calculations and experiments,”IEEE Trans. Nucl. Sci., vol. 48, pp.1893–1903, Dec. 2001
[97] K. Hirose, H. S. M. Akiyama, M. Arakaki, Y. Kuroda, S. Ishii, and K. Nakano,“Total-dose and single-event upset resistance in advanced SRAM’s fabricated on SOI using 0.2 m design rules,”in 2001 IEEE Radiation Effects Data Workshop Rec., Vancouver, BC, Canada, July 2001, pp. 48–50.
[98] J. R. Schwank, P. E.Dodd, M. R. Shaneyfelt,G.Vizkelethy, B. L.Draper, T. A. Hill, D. S. Walsh, and G. L. Hash,“Anomalous charge collection from SOI circuits and its effect on SEU hardness,”IEEE Trans. Nucl. Sci., vol. 49, pp. 2937–2947, Dec. 2002.
[99] S. E. Kerns, and B.D. Shafer.The Design of Radiation-Hardened Ics for Space:A Compendium of Approaches Proceedings of the IEEE, Vo1.76(11), pp.1470-1508,November,1988.
[100] L.R.Rockett, Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors, IEEE Trans. Nucl. Sci., VOL. 39, 1992
[101] L. R. Hite, H. Lu, T. W. Houston, et al. An SEU resistant 256k SOI SRAM. IEEE Transactions on Nuclear Science. 1992, 39(6): 2121-2125
[102] L.Rockett, et al., An SEU-hardened CMOS data latch design, IEEE Transactions on Nuclear Science, vol. 35, pp. 1682-1687, December 1988.
[103] S.Whitaker, J.Canaris, K.Liu. SEU Hardened Memory Cells for a CCSDS Reed Solomn Encoder. IEEE Trans. Nucl. Sci. 1991.12, 38(6): 1471-1477.
[104] M.N.Liu, S.Whitaker. Low Power SEU Immune CMOS Memory Circuits. IEEE Trans. Nucl. Sci. 1992.12, 39(6): 1679-1684.
[105] D.Bessot, R.Velazco. Design of SEU-Hardened CMOS Memory Cells: The HIT Cell, the 2nd European Conference Radiation and Its Effects on Components and Systems. 1993: 563-570.
[106] R.Velazco, D.Bessot. Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits. IEEE Trans. Nucl. Sci. 1994.12, 41(6): 2229-2234.
[107] N. Haddad, et al. Design Considerations for Next Generation Radiation Hardened SRAMs for Space Applications.IEEE Conference on Aerospace, 2005, pp1-6
[108] T.Calin, M.Nicolaidis, R.Velazco. Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Trans. Nucl. Sci. 1996.12, 43(6): 2874-2878.
[109]一种低功耗的SEU加固存储单元,半导体学报,2007年第28卷第5期,pp.755-758
[110] R.Velazco, T.Calin, M.Nicolaidis, et al. SEU-Hardened Storage Cell Validation Using a Pulsed Laser. IEEE Trans. Nucl. Sci. 1996.12, 43(6).
[111] Oluwole A. Amusan, Lloyd W. Massengill, et al., Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2007
[112] Multiple Node Upset in SEU Hardened Storage Cells, Chinese Journal of Semiconductor, Vol.29, No.2, 2008, pp.244~250
[113] Pitsini Mongkolkachit and Bharat Bhuva,“Design technique for mitigation of alpha-particle-induced single-event transients in combinational logic”, IEEE Transactions on Device and Materials Reliability, Vol.29. , No.3, 2003
[114] M. C. Casey, B. L. Bhuva, J. D. Black, et al., HBD Using Cascode-Voltage Switch Logic Gates for SET Tolerant Digital Designs, IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 2005
[115] Yoichi SASAKI, Kazuteru NAMBA, Hideo ITO, Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit, the 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006
[116] Rajesh Garg, Nikhil Jayakumar, A design approach for radiation-hard digital electronics, DAC, 2006
[117] Michels,á., Petroli, L., Lisb?a, C. A. L., Kastensmidt, F. and Carro, L. SET Fault Tolerant Combinational Circuits Based on Majority Logic, the 21st International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’06), 2006
[118] D.Mavis and P. Eaton,“Soft error rate mitigation techniques for modern microcircuits”40th Annu. IEEE Int. Reliabilitiy Physics Symp. (IRPS), Dallas, TX, 2002, pp. 216–225.
[119] J. E. Knudsen, L. T. Clark An Area and Power Efficient Radiation Hardened by Design Flip-Flop, IEEE Transactions on Nuclear Science Volume 53, Issue 6, Dec. 2006 Page(s):3392 - 3399
[120] Kartik Mohanram, Nur A. Touba, Partial Error Masking Reduce Soft Error Failure Rate in Logic Circuits, the 18th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’03), 2003
[121] Quming Zhou, Kartik Mohanram, Cost-effective radiation hardening technique for combinational logic, IEEE International Conference on Computer Aided Design (ICCAD), 2004
[122] J. H. Patel and L. Y. Fung,“Concurrent error detection in ALUs by recomputing with shifted operands,”IEEE Trans. Comput., vol. C-31, no. 7, pp. 589–595, Jul. 1982.
[123] N. Oh, P.P. Shirvani, and E.J. McCluskey,“Error Detection by Duplicated Instructions in Super-Scalar Processors,”IEEE Trans. Reliability, vol. 51, no. 1, Mar. 2002, pp. 63-75.
[124] N. Oh, S. Mitra, E.J. McCluskey, ED4I: Error Detection by Diverse Data and Duplicated Instructions, IEEE Transactions on Computer, February 2002 (Vol. 51, No. 2) , pp. 180-199
[125] J. Ray, J.C. Hoe, and B. Falsafi,“Dual Use of Superscalar Datapath for ransient-Fault Detection and Recovery,”Proc. 34th Ann. Int’l Symp. Microarchitecture (Micro-34), IEEE Press, 2001, pp. 214-224.
[126] Todd M. Austin, DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, the 32nd Annual International Symposium on Microarchitecture (MICRO), 1999.
[127] E.Rotenberg, AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In Proceedings of the 29th Fault-Tolerant Computing Symposium, June 1999.
[128] Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi, Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures, International Symposium on Microarchitecture (MICRO), 2004
[129] T.N. Vijaykumar, I. Pomeranz, and K. Cheng,“Transient-Fault Recovery Using Simultaneous Multithreading,”Proc. 29th Ann. Int’l Symp. ComputerArchitecture (ISCA 02), IEEE Press, 2002, pp. 87-98.
[130] S. Mukherjee, M. Kontz, and S. Reinhardt. Detailed Design and Evaluation of Redundant Multithreading Alternatives. In International Symposium on Computer Architecture (ISCA), pages 99–110, May 2002.
[131] A. Parashar, S. Gurumurthi, and A. Sivasubramaniam. A Complexity-E?ective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 376–386, June 2004.
[132] M. A. Gomaa and T. N. Vijaykumar. Opportunistic transient-fault detection. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 172–183, 2005.
[133]江建慧,员春欣,“芯片级系统的在线测试技术”,计算机研究与发展,第41卷,第9期,2004年9月,pp.1593~1603
[134] Wei Zhang, Enhancing Data Cache Reliability by the Addition of a Small Fully-Associative Replication Cache, 18th Annual ACM International Conference on Supercomputing (ICS), 2004
[135] Pablo Montesinos, Wei Liu and Josep Torrellas, Using Register Lifetime Predictions to Protect Register Files against Soft Errors, 37th International Conference on Dependable Systems and Networks (DSN’07), 2007
[136] Wei Zhang, Sudhanva Gurumurthi, Mahmut Kandemir, Anand Sivasubramaniam, ICR:In-Cache Replication for Enhancing Data Cache Reliability, International Conference on Dependable Systems and Networks (DSN’03), 2003
[137] Vilas Sridharan, Hossein Asadi, Mehdi B. Tahoori, David Kaeli, Reducing Data Cache Susceptibility to Soft Errors, IEEE Transactions on Dependable and Secure Computing, Col.3, No.4, October~December, 2006
[138] Jie Hu, Shuai Wang, and Sotirios G. Ziavras, In-Register Duplication Exploiting Narrow-Width Value for Improving Register File Reliability, 36th International Conference on Dependable Systems and Networks (DSN’06) , 2006
[139] D.Wiseman, J.Canaris, S.Whitaker. Design and Testing of SEU/SEL Immune Memory and Logic Circuits in a Commercial CMOS Process. NSREC Workshop. 1993.7.
[140]刘恩科,朱秉升,罗晋生等,半导体物理学(第6版),电子工业出版社,2003,北京
[141] T. Quarles, Adding Devices to SPICE3, U. C. Berkeley, Technical Report, ERL-89-45, 1989
[142] F.Somenzi, CUDD: The CU decision diagram package (version2.4.1), Boulder, CO: Dept. Electr. Comput. Eng. Univ. Colorado, [Online]. http://vlsi.colorado.edu/fabio/CUDD, May2005.
[143]边计年,薛洪熙,苏明等,数字系统设计自动化(第2版),清华大学出版社,北京,2005.7
[144] http://www.eecs.umich.edu/~jhayes/iscas.restore/benchmark.html
[145] Lu H., Yee E, Hite L., et al. 1-M bit SRAM on SIMOX material, Proc IEEE Int SOI Conf, 1993:182
[146] http://www.ssec.honeywell.com/aerospace/datesheets/HLX6256.pdf
[147]刘新宇,孙海峰,刘洪民等,CMOS/SOI 4Kb静态随机存储器,功能材料与器件学报,第8卷第2期,2002年6月,pp.165~169
[148]刘新宇,韩郑生,周小茵等,CMOS/SOI 64Kb静态随机存储器,半导体学报,第22卷第1期,2001年1月,pp.47~52
[149]赵凯,刘忠立,于芳,高见头,肖志强,洪根深,抗辐照128Kb PD SOI静态随机存储器,半导体学报,第28卷第7期,2007年7月,pp 1139~1143
[150] Ferlet-Cavrois, V. Colladant, T. Paillet, P. Leray, J.L. Musseau, O. Schwank, J.R. Shaneyfelt, M.R. Pelloie, J.L. du Port de Poncharra, J. CEA, Centre d'Etudes de Bruyeres-le-Chatel; Worst-case bias during total dose irradiation of SOI transistors, IEEE Transactions on Nuclear Science, 2000, Vol.47 (6), pp 2183 ~ 2188.
[151] G. Gasiot, D. Giot, and P. Roche,“Well Engineering Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering”, IEEE Transactions on Nuclear Science, Volume 54, Issue 6, Part 1, Dec. 2007 Page(s):2468 - 2473
[152] D. Giot, Philippe Roche, Gilles Gasiot, and Reno Harboe-S?rensen, Multiple-Bit Upset Analysis in 90 nm SRAMs: Heavy Ions Testing and 3D Simulations, IEEE Transactions on Nuclear Science, Vol. 54, No. 4, August 2007
[153] D. Giot, Philippe Roche, Gilles Gasiot, Jean-Luc Autran, and Reno Harboe-S?rensen, Heavy Ion Testing and 3-D Simulations of Multiple Cell Upset in 65 nm Standard SRAMs, IEEE Transactions on Nuclear Science, Vol. 55, No. 4, August 2007
[154] M. L. Alles, L. W. Masengill, S. E. Kerns, K. L. Jones, J. E. Clark, W. F. Kraus,“Effect of Temperature-Dependent Bipolar Gain Distribution on SEU Vulnerability of SOI CMOS SRAMs,”IEEE Proc. Int. SOI Conf., pp. 96-97, Oct. 1992.
[155] D. Truyen, J. Boch, B. Sagnes, N. Renaud, E. Leduc, S. Arnal, and F. Saigné,“Temperature Effect on Heavy-Ion Induced Parasitic Current on SRAM by Device Simulation: Effect on SEU Sensitivity,”IEEE Tran. Nucl. Sci., vol. 54, no. 4, pp. 1025-1029, Aug. 2007.
[156] M. S. Tyagi and R. van Overstraeten,“Minority carrier recombination in heavily-doped Silicon,”Solid State Electronics, vol. 26, no. 6, pp. 577–597, 1983.
[157] Sentaurus Device User Guide version A-2007.12-SP1, Synopsys, Dec.2007.
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