集成电路低功耗设计可逆逻辑综合及性能分析
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摘要
随着集成电路工艺进入超深亚微米和纳米时代，不断增大的电路规模、不断增加的功耗和日益凸现的物理效应等问题，都成为集成电路自动化所面临的新挑战。快速发展的集成电路低功耗设计自动化需要多学科交叉研究，存在着大量的组合优化和统计分析等问题，已成为该领域备受关注的研究热点和前沿。工艺参数变动对电路性能(如速度和功耗)的影响越来越大，迫使低功耗设计辅助工具软件必须考虑工艺参数变化对低功耗设计的影响。集成电路低功耗设计算法需要更为高效的电路时延和功耗分析算法，所以如何提高电路时延和功耗统计分析的效率，不仅是电路时延和功耗统计分析领域的研究方向，也是电路低功耗设计统计方法研究进一步发展的关键。可逆电路对低功耗设计有着潜在的优势。本文以可逆电路为背景，对结合物理因素的逻辑综合和性能分析方法进行深入研究，旨在探讨低功耗设计中以物理因素为中心的逻辑综合优化方法和性能分析方法。
本文深入分析了可逆电路的工作特点、综合优化及其性能分析问题，提出了相应的综合优化方法并实现了该算法。研究了可逆电路的面积和时延问题，采用矩阵模型和符号代数作为理论基础，提出了一种符号综合方法；深入研究了可逆电路的时延分析问题，针对串扰对电路的时延带来的影响，探讨了串扰时延的计算方法，进一步在考虑面积、时延、串扰等约束下利用成本函数来指导综合过程；深入分析和研究了性能分析问题，针对工艺参数变动对电路性能(如速度和功耗)的影响日益显著的问题，提出了更加精确的电路时延和漏功耗分析方法；针对分析的复杂度和精确度问题，提出了面向性能的参数约简方法；探讨了时空参数下的分析问题，取得了以下创新性的成果：
●将可逆电路映射到一个矩阵上，能够方便地从中提炼出成本函数所必需的相关因子以及电路中任意点的输入输出值。在缩减所用门数量的同时，将减少垃圾线数作为次要目标。将可逆逻辑综合问题当作多输出逻辑综合来处理，通过划分确保每个划分区中必要输出为单输出，利用符号代数方法找出每个划分的候选门。通过附加额外的约束条件，将PPRM中的布尔运算映射为布尔多项式的运算，提出的一种以Gr(?)bner基为数学基础的分解策略来获得候选门，既解决计算复杂性问题，又改善了电路的性能。
●本文在综合过程中考虑了串扰因素，通过信号波形间的距离，同时考虑波形间的形状，分析波形之间的相关性，定义了波形相似性的概念，建立了串扰以及串扰时延的计算方法，提出了基于串扰优化的交换线间排列的优化方法。这是其他可逆电路综合方法忽视的问题。在成本函数中，我们提出了权值确定算法，使我们能根据不同的优化目标找到适宜的结果。
●在解决低功耗问题时，不能单纯依靠低功耗器件的选用，还必须与其他一些方法相结合来设计系统。本文将海森矩阵的概念引入到二次时延模型中，建立了改进的二次时延模型，纠正了现有二次模型分析中的方差分析错误，为下面的工作打基础。本文提出了电路漏功耗的对数用改进的二次模型拟合方法，直接用工艺参数变动变量表达，并论证了这一拟合的正确性和合理性，简化分析过程。
●本文建立了一个层次化性能分析模型，根据电路的时延和漏功耗的对数的统一表达形式，提出了一种新颖的基于CH(Correlation-Hessian matrix)的面向性能的参数约简方法，保留部分重要参数，减小计算规模。利用CH矩阵作约简方法既考虑了工艺参数之间的依赖关系，又考虑到它们与高层次之间的关系，从而提高性能预算的精确度。探索时空参数变化下的参数模型，尝试将工艺参数扩展到时空参数做讨论。
本论文深入研究了可逆电路的综合优化问题以及工艺参数变化带来的性能分析等新问题，具有很强的针对性和代表性，可以作为其他以低功耗设计为中心的集成电路自动化设计方法的借鉴。
With shrinking device size,physical effects become an increasinglycritical determinant of synthesis,optimization and performance analysis inVLSI design.The increasing of circuits scale as well as the more prominentphysical effects bring huge challenge to the design of integrated circuit.ICdesign automation is a rapid development,changing,interdisciplinary andalgorithm-intensive fields,where exists lots of combinational optimizationproblems and statistic analysis problems.Therefore,it draws great concern ofthis yield.With technology scaling,process variations have a growing impacton circuit performance(such as speed and power) for today's integrated circuit(IC) technologies.Low power design automation tools have to consider theimpact of process variations.It needs more effectual circuit delay and poweranalysis algorithm.Advance analysis efficiency is interested in the yield and isbecoming a key issue in present and future technologies.Under these situations,this thesis investigates logic synthesis and performance analysis whichconsiders physical effects.It is hoped that these discussions presented in thethesis can push forward the research work on the low power design.
The thesis analyzes the work property of reversible circuits,synthesis andoptimization problems as well as performance analysis problems.Also,itintroduces some practical design algorithms behind these problems.The thesisconsists of four parts,corresponding to various aspects of low power designissues.The first part analyzes the area and delay of reversible ciruits.Asymbolic synthesis algorithm based on the matrix model and symbolic algebrais introduced to solve computational complexity problem.The second partresearch works considering the crosstalk problem in the logic,synthesis.Anefficient crosstalk reduction algorithm by permuting wires is also introduced inthe thesis.The third part analyzes the delay and leakage power of reversiblecircuits under process variation.The fourth part investigates the hierarchicalperformance analysis.A performance-oriented parameter reduction method is presented.A performance analysis under time-space parameter is discussed.The main contribution of the thesis are as follows:
The matrix modelof reversible circuit is defined.Using the model allowsus to easily extract the required factors of cost function and the inputs andoutputs values of each point in circuit.It minimizes the number of gates,pathdelay and crosstalk as the objective.We act the reversible logic synthesisproblem as multi-output logic synthesis.The method has greater potential to beextended to functions with more than just a few inputs and outputs.We resolveBoolean problem via symbolic algebra method.It not only solve computionalcomplexity,but also improve circuit performance.
The heuristic Synthesis algorithm is presented in the thesis.We define thesimilarity between waveforms by statistics.Based on matrix model andsymbolic algebra,the thesis offers a symbolic synthesis method and performsdelay and crosstalk optimization simultaneously.Using the cost function themethod steers the synthesis process,which considers multiple optimizationobjectives,including area,delay and crosstalk.
To solve low power problem,we not only use low power circuitconfiguration,but also combine with other design methods.The thesisconstructs improved quadratic model using Hessian matrix.We correct varianceanalysis result of existing quadratic model.Using the improved quadratic model,circuit delay and leakage power analysis under process variations is presentedand demonstrated.
In the thesis,a hierarchical modeling for performance analysis is built.Circuit delay and the lognormal expansion of the leakage power areexpressed as the quadratic model.A novel parameter reduction method basedon CH(Correlation-Hessian matrix) is presented.It accounts for allcorrelations,from manufacturing process dependence,to high-level analysisto produce more accurate performance predictions.
In the thesis,issues of reversible circuits synthesis and based onCorrelation-Hessian matrix hierarchical delay and leakage power analysis under process variation are investigated.This work is a typical research work in ICdesign automation field considering lower power design.It is also a goodreference for other researchers and designers working in the field.
本文深入分析了可逆电路的工作特点、综合优化及其性能分析问题，提出了相应的综合优化方法并实现了该算法。研究了可逆电路的面积和时延问题，采用矩阵模型和符号代数作为理论基础，提出了一种符号综合方法；深入研究了可逆电路的时延分析问题，针对串扰对电路的时延带来的影响，探讨了串扰时延的计算方法，进一步在考虑面积、时延、串扰等约束下利用成本函数来指导综合过程；深入分析和研究了性能分析问题，针对工艺参数变动对电路性能(如速度和功耗)的影响日益显著的问题，提出了更加精确的电路时延和漏功耗分析方法；针对分析的复杂度和精确度问题，提出了面向性能的参数约简方法；探讨了时空参数下的分析问题，取得了以下创新性的成果：
●将可逆电路映射到一个矩阵上，能够方便地从中提炼出成本函数所必需的相关因子以及电路中任意点的输入输出值。在缩减所用门数量的同时，将减少垃圾线数作为次要目标。将可逆逻辑综合问题当作多输出逻辑综合来处理，通过划分确保每个划分区中必要输出为单输出，利用符号代数方法找出每个划分的候选门。通过附加额外的约束条件，将PPRM中的布尔运算映射为布尔多项式的运算，提出的一种以Gr(?)bner基为数学基础的分解策略来获得候选门，既解决计算复杂性问题，又改善了电路的性能。
●本文在综合过程中考虑了串扰因素，通过信号波形间的距离，同时考虑波形间的形状，分析波形之间的相关性，定义了波形相似性的概念，建立了串扰以及串扰时延的计算方法，提出了基于串扰优化的交换线间排列的优化方法。这是其他可逆电路综合方法忽视的问题。在成本函数中，我们提出了权值确定算法，使我们能根据不同的优化目标找到适宜的结果。
●在解决低功耗问题时，不能单纯依靠低功耗器件的选用，还必须与其他一些方法相结合来设计系统。本文将海森矩阵的概念引入到二次时延模型中，建立了改进的二次时延模型，纠正了现有二次模型分析中的方差分析错误，为下面的工作打基础。本文提出了电路漏功耗的对数用改进的二次模型拟合方法，直接用工艺参数变动变量表达，并论证了这一拟合的正确性和合理性，简化分析过程。
●本文建立了一个层次化性能分析模型，根据电路的时延和漏功耗的对数的统一表达形式，提出了一种新颖的基于CH(Correlation-Hessian matrix)的面向性能的参数约简方法，保留部分重要参数，减小计算规模。利用CH矩阵作约简方法既考虑了工艺参数之间的依赖关系，又考虑到它们与高层次之间的关系，从而提高性能预算的精确度。探索时空参数变化下的参数模型，尝试将工艺参数扩展到时空参数做讨论。
本论文深入研究了可逆电路的综合优化问题以及工艺参数变化带来的性能分析等新问题，具有很强的针对性和代表性，可以作为其他以低功耗设计为中心的集成电路自动化设计方法的借鉴。
With shrinking device size,physical effects become an increasinglycritical determinant of synthesis,optimization and performance analysis inVLSI design.The increasing of circuits scale as well as the more prominentphysical effects bring huge challenge to the design of integrated circuit.ICdesign automation is a rapid development,changing,interdisciplinary andalgorithm-intensive fields,where exists lots of combinational optimizationproblems and statistic analysis problems.Therefore,it draws great concern ofthis yield.With technology scaling,process variations have a growing impacton circuit performance(such as speed and power) for today's integrated circuit(IC) technologies.Low power design automation tools have to consider theimpact of process variations.It needs more effectual circuit delay and poweranalysis algorithm.Advance analysis efficiency is interested in the yield and isbecoming a key issue in present and future technologies.Under these situations,this thesis investigates logic synthesis and performance analysis whichconsiders physical effects.It is hoped that these discussions presented in thethesis can push forward the research work on the low power design.
The thesis analyzes the work property of reversible circuits,synthesis andoptimization problems as well as performance analysis problems.Also,itintroduces some practical design algorithms behind these problems.The thesisconsists of four parts,corresponding to various aspects of low power designissues.The first part analyzes the area and delay of reversible ciruits.Asymbolic synthesis algorithm based on the matrix model and symbolic algebrais introduced to solve computational complexity problem.The second partresearch works considering the crosstalk problem in the logic,synthesis.Anefficient crosstalk reduction algorithm by permuting wires is also introduced inthe thesis.The third part analyzes the delay and leakage power of reversiblecircuits under process variation.The fourth part investigates the hierarchicalperformance analysis.A performance-oriented parameter reduction method is presented.A performance analysis under time-space parameter is discussed.The main contribution of the thesis are as follows:
The matrix modelof reversible circuit is defined.Using the model allowsus to easily extract the required factors of cost function and the inputs andoutputs values of each point in circuit.It minimizes the number of gates,pathdelay and crosstalk as the objective.We act the reversible logic synthesisproblem as multi-output logic synthesis.The method has greater potential to beextended to functions with more than just a few inputs and outputs.We resolveBoolean problem via symbolic algebra method.It not only solve computionalcomplexity,but also improve circuit performance.
The heuristic Synthesis algorithm is presented in the thesis.We define thesimilarity between waveforms by statistics.Based on matrix model andsymbolic algebra,the thesis offers a symbolic synthesis method and performsdelay and crosstalk optimization simultaneously.Using the cost function themethod steers the synthesis process,which considers multiple optimizationobjectives,including area,delay and crosstalk.
To solve low power problem,we not only use low power circuitconfiguration,but also combine with other design methods.The thesisconstructs improved quadratic model using Hessian matrix.We correct varianceanalysis result of existing quadratic model.Using the improved quadratic model,circuit delay and leakage power analysis under process variations is presentedand demonstrated.
In the thesis,a hierarchical modeling for performance analysis is built.Circuit delay and the lognormal expansion of the leakage power areexpressed as the quadratic model.A novel parameter reduction method basedon CH(Correlation-Hessian matrix) is presented.It accounts for allcorrelations,from manufacturing process dependence,to high-level analysisto produce more accurate performance predictions.
In the thesis,issues of reversible circuits synthesis and based onCorrelation-Hessian matrix hierarchical delay and leakage power analysis under process variation are investigated.This work is a typical research work in ICdesign automation field considering lower power design.It is also a goodreference for other researchers and designers working in the field.
引文
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