集成电路LDO稳压器的电磁兼容敏感度机理研究
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摘要
近年来集成电路（IC）的制造工艺不断提升，已从超深亚微米进入到纳米阶段。伴随着半导体特征尺寸不断减小，工作频率越来越高，涌现出大量的电磁兼容（EMC）问题，例如同时开关噪声突出、片内互扰严重、寄生效应加剧等，IC的电磁敏感度已成为影响电子系统性能提高的瓶颈。本文研究线性低压差（LDO）稳压器在电磁干扰（EMI）作用下的失效模式和失效机理，分析失效对电路系统预期造成的影响。采用国际电子委员会（IEC）标准方法，测试LDO稳压器老化过程中的频域敏感度性能。分析着重于查明失效模式、追查失效机理以及失效预测。最后通过敏感度建模和仿真结果，对失效机理进行了验证分析。
第一部分对LDO稳压器EMC敏感度机理与分析方法展开研究。首先对电源稳压器的电路结构展开研究，分析了LDO稳压器的优缺点。然后剖析了LDO稳压器电路的典型结构，并对稳压器的关键电路——运算放大器、带隙电压基准电路和功率开关元件展开具体研究，分析了LDO稳压器关键电路的敏感度失效机理。对目前应用于集成电路电磁兼容研究的建模与仿真方法进行综述，主要分析了LDO稳压器敏感度研究中采用的电路级和行为级两种建模与仿真分析方法。为了配合敏感度机理和建模仿真研究，选取直接功率注入法作为研究LDO稳压器的测试方法。
第二部分展开LDO稳压器敏感度电路级建模与仿真方法研究。首先分析了一款基于飞思卡尔90纳米工艺的实验芯片LDO稳压器电路结构，然后分析片上电压传感器的异步和同步采集原理，提出了一种创新的片上电压测试方法。对稳压器进行直流功能性测试、阻抗测试和敏感度测试，分析了测试方法和结果。提出了LDO稳压器的敏感度电路级建模与仿真流程，通过对比仿真与片上测试结果，提出了由简单至复杂的四种级别电路模型，分析了稳压器关键子电路和寄生元件对敏感度影响在频域1MHz至1GHz间的分布权重。
第三部分展开LDO稳压器敏感度行为级建模与仿真方法研究。研究了一款工业级LDO稳压器的电路结构，然后分析了敏感度测试电路板和阻抗校准板的电路设计，并搭建了敏感度测试环境。稳压器测试包括直流测试、阻抗测试以及DPI传导敏感度测试。测试结果揭示了LDO稳压器的直流特性，有源和无源阻抗特性以及稳压器输出端失效类型和敏感度水平。建模过程中，由简单线性模型逐渐深入提出线性和非线性行为级模型。最后，仿真结果实现了与测试结果在整个频域的匹配。
最后，对电应力老化导致传导敏感度变化展开研究，并将其应用于LDO稳压器电路。进行了大量的老化实验。老化条件采用电应力，通过实验验证，测试稳压器的直流特性和敏感度水平变化情况。测试结果显示，电应力加速老化导致稳压器对电源线上的EMI扰动更加敏感。在机理分析中，采用数学推导计算得出运放输入PMOS差分对会导致输出电压的偏移，达到敏感度分析设定的失效判据。老化过程中，电流镜中NMOS器件的阈值电压增加导致LDO稳压器的输出电压降低，而偏置电流的减少则进一步增加了稳压器的敏感度。建立LDO稳压器的敏感度加速老化模型，其中包含可靠性模型和敏感度模型，可实现稳压器在整个生命周期内的敏感度水平预测。
In recent years, the CMOS technology has changed from ultra deep submicron tonanometer. With the decreasing of semiconductor feature size and the increasing ofon-chip clock frequency, there come serious Electromagnetic Compatibility (EMC)problems like simultaneous switching noise, on-chip inter-disturbance, parasitic effectsand so on. The IC’s electromagnetic susceptibility (EMS) has become the bottleneck ofthe electron system performance improvement. This paper studies the failure modes andmechanism of the linear low-dropout (LDO) voltage regulator under ElectromagneticInterference (EMI) and evaluates the defect influence to circuit system. Thesusceptibility performance of the LDO regulator in ageing process is measured byInternational Electrotechnical Commission (IEC) standard test methods in the frequencydomain. The analysis is mainly focused on identifying failure modes, failure mechanism,modeling and prediction by simulations. The failure mechanism is validated bysusceptibility modeling and simulation results.
In the first part of the thesis, the LDO susceptibility mechanism and analysismethods are studied. Firstly, the structure of power regulator circuit is analyzed to findthe advantages and disadvantages of LDO regulator. Then, the typical structure of LDOvoltage regulator circuit is divided into operational amplifier, bandgap voltage referencecircuit and pass devices for immunity failure mechanism analysis. The current modelingand simulation methods which are applied in IC EMC research are reviewed. The twokinds of modeling and simulation analysis methods including the circuit level andbehavioral level are mainly analyzed for LDO regulator study. And the direct powerinjection (DPI) method is selected as the test technology to help the mechanism analysis,modeling and simulation process.
In the second part of the thesis, the LDO regulator sensitivity circuit levelmodeling and simulation method is evaluated. The structure of a test chip designed byFreescale90nm technology is analyzed firstly. Based on the on-chip voltage sensorasynchronous and synchronous acquisition principle study, an innovative on-chipvoltage test method is presented. Subsequently, the DC functional, impedance andsusceptibility measurement results are explored. The LDO regulator immunity circuitlevel modeling and simulation flow is presented combined with simulation and on-chiptest results. Finally, four types of models from simple to complex levels are discussedstep by step to distinguish contributions of key sub-circuits and parasitic elements in thefrequency domain from1MHz to1GHz.
In the third part of the thesis, the LDO regulator susceptibility behavioral levelmodeling and simulation method is evaluated. The structure of an industry test chip isanalyzed firstly. With the test circuit PCB board and impedance calibration board, the immunity measurement environment is built. The test results of DC, impedance and DPIconducted immunity show the DC characteristic, active and passive impedance andsusceptibility level. In modeling process, the non-linear behavioral is proposed fromsimple linear model and linear behavioral model. The simulation results achieve a goodmatch with the test results in the frequency domain.
Finally, this paper analyses the drift in LDO immunity after accelerated ageing. Alarge number of measurements which show the variations in the test results for DCcharacteristic, impedance and immunity reveal increasing susceptibility after electricalaccelerated ageing. With the susceptibility drift mechanism study, the immunitydecreasing in ageing process is explained by mathematical analytical analysis of theop-amp input PMOS differential pair. In ageing process, the increasing of NMOSthreshold voltage leads to the decreasing of LDO regulator output voltage. And the biascurrent decreasing is mainly responsible for the immunity decreasing. The regulatoraccelerating ageing model which is combined with reliability and immunity model isestablished to realize the susceptibility level prediction of the entire life cycle.
第一部分对LDO稳压器EMC敏感度机理与分析方法展开研究。首先对电源稳压器的电路结构展开研究，分析了LDO稳压器的优缺点。然后剖析了LDO稳压器电路的典型结构，并对稳压器的关键电路——运算放大器、带隙电压基准电路和功率开关元件展开具体研究，分析了LDO稳压器关键电路的敏感度失效机理。对目前应用于集成电路电磁兼容研究的建模与仿真方法进行综述，主要分析了LDO稳压器敏感度研究中采用的电路级和行为级两种建模与仿真分析方法。为了配合敏感度机理和建模仿真研究，选取直接功率注入法作为研究LDO稳压器的测试方法。
第二部分展开LDO稳压器敏感度电路级建模与仿真方法研究。首先分析了一款基于飞思卡尔90纳米工艺的实验芯片LDO稳压器电路结构，然后分析片上电压传感器的异步和同步采集原理，提出了一种创新的片上电压测试方法。对稳压器进行直流功能性测试、阻抗测试和敏感度测试，分析了测试方法和结果。提出了LDO稳压器的敏感度电路级建模与仿真流程，通过对比仿真与片上测试结果，提出了由简单至复杂的四种级别电路模型，分析了稳压器关键子电路和寄生元件对敏感度影响在频域1MHz至1GHz间的分布权重。
第三部分展开LDO稳压器敏感度行为级建模与仿真方法研究。研究了一款工业级LDO稳压器的电路结构，然后分析了敏感度测试电路板和阻抗校准板的电路设计，并搭建了敏感度测试环境。稳压器测试包括直流测试、阻抗测试以及DPI传导敏感度测试。测试结果揭示了LDO稳压器的直流特性，有源和无源阻抗特性以及稳压器输出端失效类型和敏感度水平。建模过程中，由简单线性模型逐渐深入提出线性和非线性行为级模型。最后，仿真结果实现了与测试结果在整个频域的匹配。
最后，对电应力老化导致传导敏感度变化展开研究，并将其应用于LDO稳压器电路。进行了大量的老化实验。老化条件采用电应力，通过实验验证，测试稳压器的直流特性和敏感度水平变化情况。测试结果显示，电应力加速老化导致稳压器对电源线上的EMI扰动更加敏感。在机理分析中，采用数学推导计算得出运放输入PMOS差分对会导致输出电压的偏移，达到敏感度分析设定的失效判据。老化过程中，电流镜中NMOS器件的阈值电压增加导致LDO稳压器的输出电压降低，而偏置电流的减少则进一步增加了稳压器的敏感度。建立LDO稳压器的敏感度加速老化模型，其中包含可靠性模型和敏感度模型，可实现稳压器在整个生命周期内的敏感度水平预测。
In recent years, the CMOS technology has changed from ultra deep submicron tonanometer. With the decreasing of semiconductor feature size and the increasing ofon-chip clock frequency, there come serious Electromagnetic Compatibility (EMC)problems like simultaneous switching noise, on-chip inter-disturbance, parasitic effectsand so on. The IC’s electromagnetic susceptibility (EMS) has become the bottleneck ofthe electron system performance improvement. This paper studies the failure modes andmechanism of the linear low-dropout (LDO) voltage regulator under ElectromagneticInterference (EMI) and evaluates the defect influence to circuit system. Thesusceptibility performance of the LDO regulator in ageing process is measured byInternational Electrotechnical Commission (IEC) standard test methods in the frequencydomain. The analysis is mainly focused on identifying failure modes, failure mechanism,modeling and prediction by simulations. The failure mechanism is validated bysusceptibility modeling and simulation results.
In the first part of the thesis, the LDO susceptibility mechanism and analysismethods are studied. Firstly, the structure of power regulator circuit is analyzed to findthe advantages and disadvantages of LDO regulator. Then, the typical structure of LDOvoltage regulator circuit is divided into operational amplifier, bandgap voltage referencecircuit and pass devices for immunity failure mechanism analysis. The current modelingand simulation methods which are applied in IC EMC research are reviewed. The twokinds of modeling and simulation analysis methods including the circuit level andbehavioral level are mainly analyzed for LDO regulator study. And the direct powerinjection (DPI) method is selected as the test technology to help the mechanism analysis,modeling and simulation process.
In the second part of the thesis, the LDO regulator sensitivity circuit levelmodeling and simulation method is evaluated. The structure of a test chip designed byFreescale90nm technology is analyzed firstly. Based on the on-chip voltage sensorasynchronous and synchronous acquisition principle study, an innovative on-chipvoltage test method is presented. Subsequently, the DC functional, impedance andsusceptibility measurement results are explored. The LDO regulator immunity circuitlevel modeling and simulation flow is presented combined with simulation and on-chiptest results. Finally, four types of models from simple to complex levels are discussedstep by step to distinguish contributions of key sub-circuits and parasitic elements in thefrequency domain from1MHz to1GHz.
In the third part of the thesis, the LDO regulator susceptibility behavioral levelmodeling and simulation method is evaluated. The structure of an industry test chip isanalyzed firstly. With the test circuit PCB board and impedance calibration board, the immunity measurement environment is built. The test results of DC, impedance and DPIconducted immunity show the DC characteristic, active and passive impedance andsusceptibility level. In modeling process, the non-linear behavioral is proposed fromsimple linear model and linear behavioral model. The simulation results achieve a goodmatch with the test results in the frequency domain.
Finally, this paper analyses the drift in LDO immunity after accelerated ageing. Alarge number of measurements which show the variations in the test results for DCcharacteristic, impedance and immunity reveal increasing susceptibility after electricalaccelerated ageing. With the susceptibility drift mechanism study, the immunitydecreasing in ageing process is explained by mathematical analytical analysis of theop-amp input PMOS differential pair. In ageing process, the increasing of NMOSthreshold voltage leads to the decreasing of LDO regulator output voltage. And the biascurrent decreasing is mainly responsible for the immunity decreasing. The regulatoraccelerating ageing model which is combined with reliability and immunity model isestablished to realize the susceptibility level prediction of the entire life cycle.
引文
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