时间交叉模数转换器数字校准技术研究
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摘要
信息技术和集成系统的迅速发展使得对高性能模数转换器的需求日趋强烈。然而,随着CMOS工艺的演进,在深亚微米、纳米工艺条件下,器件尺寸按比例缩减、电源电压降低以及晶体管本征增益变低等因素的存在使得电路的非理想效应更加凸显,为高性能模数转换器的设计带来诸多困难,单通道模数转换器的速度与精度性能已趋于现有条件下的物理极限。时间交叉技术是突破物理限制,实现高速、高精度模数转换的必然途径,但是通道问的失调失配、增益失配和采样时间失配严重制约了时间交叉模数转换器的性能。凭借大规模数字集成电路在工艺、集成度、成本、功耗等方面的优势,采用数字校准技术突破模拟电路性能瓶颈是未来高速、高精度时间交叉模数转换器发展的趋势所在。
本论文研究高性能时间交叉模数转换器的数字辅助设计技术,探讨数字辅助的模拟集成电路的设计原理及设计流程,依靠数字信号处理知识体系的完备性,利用数字后处理技术抑制时间交叉模数转换器通道失配误差对其动态性能的影响,实现数字校准。通过在系统行为级、电路级搭建设计和验证平台,完成完整的设计和验证过程。
第一,提出了互质通道组的劈分时间交叉模数转换器一般性结构。系统地研究时间交叉模数转换器通道失配误差的来源、误差效应及误差模型,深入讨论带通道失配误差校准的时间交叉模数转换器的系统架构、基础理论以及算法实现。依据劈分通道互校准概念,研究利用劈分设计技术实现时间交叉模数转换器的基本原理,提出了设计互质通道组劈分时间交叉模数转换器的充分条件及设计方法。
第二,针对所提出的互质通道组的劈分时间交叉模数转换器结构,提出了通道失配误差全数字校准技术。该校准技术能够在后台自适应地对通道失调失配、增益失配和采样时间失配同时进行校准,消除误差对时间交叉模数转换器性能的限制。校准算法基于最小均方迭代原理,具有计算复杂度低、易于硬件实现的优点。为保证高频信号输入时的校准效果,在校准过程中引入针对采样时间高阶误差项的级联补偿技术,使得输入在接近奈奎斯特频率时仍然具有优异的校准效果。以一个7通道劈分时间交叉模数转换器为例完成对所提出的互质通道组劈分时间交叉模数转换器结构及其失配校准技术的示范论证。同时,所提出的结构和校准技术也具有向任意通道数量的时间交叉模数转换系统扩展的特点。
第三,设计了单通道14位、125MS/s流水线型模数转换器,并以之为通道单元搭建了用于验证所提出转换器结构的电路平台,结合校准算法的FPGA硬件实现,完成了对所提校准方案正确性和可实现性的验证。电路级验证结果表明,在失调失配、增益失配和采样时间失配分别为3%满幅值输入范围、2%和2%采样时钟周期的条件下,经过校准后时间交叉ADC的无杂散动态范围和信号噪声畸变比均提高了50dBc左右,分别达到92dBc和84dBc,有效位数提高了8位,达到13.7位,接近时间交叉ADC中单通道ADC的有效精度。该结果说明,所提出的数字校准技术能够有效消除时间交叉ADC通道失配导致的非理想效应,提高其动态性能。
Rapid developments of information technology and integrated systems have strong growing demand for high performance ADCs. However, with the development of CMOS process, the design of high performance ADCs are challenged by more obvious nonideal factors brought about by scaling down of technology, low supply voltage, low transistor intrinsic gain under deep submicron and nanometer process. The performance of single channel ADC approaches to the technology limitations on speed and accuracy in the present conditions. Multi-channel Time-Interleaved ADC (TIADC) is a necessary and an effective way of breaking through technology restrictions and speeding up high resolution analog-to-digital conversion. Offset mismatch, gain mismatch, and timing skew mismatch among channels, however, severely restrict the performance of TIADC. With large scale integrated circuits' advantages on process, intergration, cost and power, using digital calibration for breaking through the performance bottleneck of analog circuits will be the general trend of high speed high resolution TIADC design in future.
This thesis researches digitally assisted design technique for high performance TIADC. Exploring universal design principle and design flew of the digital assisted analog integrated circuits. Depending on the completeness of digital signal processing knowledge,achieving digital calibration by using digital post processing technique to inhibit the detrimental effect on dynamic performance of the TIADC resulted from the mismatches among channels. Designing system-level, behavior-level and circuit-level verification platform for completed design and verification
Firstly, A novel mutual-prime-channel-group TIADC based on split-ADC and its general architecture are presented. The sources of channel mismatch errors and the error effects are studied systematically, and a channel model with mismatch errors is given. System architectures, basic theories, and algorithm implementation of TIADC with channel mismatches calibration are thorough discussed. On the basis of split-ADC calibration concept, basic principle of time-interleaved ADC using split design technique is researched in depth, sufficient conditions and design method of mutual-prime-channel-group TIADC based on split-ADC are presented.
Secondly, all-digital channel mismatches calibration technique aiming at the mutual-prime-channel-group TIADC is presented. This technique can adaptively calibrate offset mismatch, gain mismatch and timing skew mismatch among channels simultaneously at background, eliminating performance limitations which are brought about by mismatches for TIADC. The calibration algorithm is based on least-mean-square iteration which has advantages of low computational complexity and easy in complementation. To guarantee effective calibration when input frequency of the TIADC is high, a cascaded compensation scheme for correction of high-order timing skew errors is employed and good calibrating performance is demonstrated with normalized input frequency near Nyquist frequency. In this thesis, a7-channel split-ADC based TIADC is taken as an example to prove the architecture of mutual-prime-channel-group TIADC and its mismatches digital background calibration. Moreover, the proposed architecture and the associated calibration technique can be expanded to channels of any number.
Finally, a14-bit125MS/s pipelined ADC is designed, and using it as channel unit for developing a circuit platform of the proposed TIADC architecture, in combination with the implementation of the calibration algorithm by FPGA, verifications for the correctness and the practicability of the proposed TIADC architecture and calibration scheme are done. Verification results show that, with3%full scale range offset mismatch,2%gain mismatch and2%sampling period timing skew mismatch, spurious free dynamic range and signal to noise and distortion rate improve about50dBc, achieve92dBc and84dBc respectively, effective number of bits improves8bits, achieve13.7bits which approaches the single channel resolution of the TIADC. This reveals the proposed digital calibration technique does eliminate the nonideal effects brought about by channel mismatch and improves TIADC dynamic performance.
本论文研究高性能时间交叉模数转换器的数字辅助设计技术,探讨数字辅助的模拟集成电路的设计原理及设计流程,依靠数字信号处理知识体系的完备性,利用数字后处理技术抑制时间交叉模数转换器通道失配误差对其动态性能的影响,实现数字校准。通过在系统行为级、电路级搭建设计和验证平台,完成完整的设计和验证过程。
第一,提出了互质通道组的劈分时间交叉模数转换器一般性结构。系统地研究时间交叉模数转换器通道失配误差的来源、误差效应及误差模型,深入讨论带通道失配误差校准的时间交叉模数转换器的系统架构、基础理论以及算法实现。依据劈分通道互校准概念,研究利用劈分设计技术实现时间交叉模数转换器的基本原理,提出了设计互质通道组劈分时间交叉模数转换器的充分条件及设计方法。
第二,针对所提出的互质通道组的劈分时间交叉模数转换器结构,提出了通道失配误差全数字校准技术。该校准技术能够在后台自适应地对通道失调失配、增益失配和采样时间失配同时进行校准,消除误差对时间交叉模数转换器性能的限制。校准算法基于最小均方迭代原理,具有计算复杂度低、易于硬件实现的优点。为保证高频信号输入时的校准效果,在校准过程中引入针对采样时间高阶误差项的级联补偿技术,使得输入在接近奈奎斯特频率时仍然具有优异的校准效果。以一个7通道劈分时间交叉模数转换器为例完成对所提出的互质通道组劈分时间交叉模数转换器结构及其失配校准技术的示范论证。同时,所提出的结构和校准技术也具有向任意通道数量的时间交叉模数转换系统扩展的特点。
第三,设计了单通道14位、125MS/s流水线型模数转换器,并以之为通道单元搭建了用于验证所提出转换器结构的电路平台,结合校准算法的FPGA硬件实现,完成了对所提校准方案正确性和可实现性的验证。电路级验证结果表明,在失调失配、增益失配和采样时间失配分别为3%满幅值输入范围、2%和2%采样时钟周期的条件下,经过校准后时间交叉ADC的无杂散动态范围和信号噪声畸变比均提高了50dBc左右,分别达到92dBc和84dBc,有效位数提高了8位,达到13.7位,接近时间交叉ADC中单通道ADC的有效精度。该结果说明,所提出的数字校准技术能够有效消除时间交叉ADC通道失配导致的非理想效应,提高其动态性能。
Rapid developments of information technology and integrated systems have strong growing demand for high performance ADCs. However, with the development of CMOS process, the design of high performance ADCs are challenged by more obvious nonideal factors brought about by scaling down of technology, low supply voltage, low transistor intrinsic gain under deep submicron and nanometer process. The performance of single channel ADC approaches to the technology limitations on speed and accuracy in the present conditions. Multi-channel Time-Interleaved ADC (TIADC) is a necessary and an effective way of breaking through technology restrictions and speeding up high resolution analog-to-digital conversion. Offset mismatch, gain mismatch, and timing skew mismatch among channels, however, severely restrict the performance of TIADC. With large scale integrated circuits' advantages on process, intergration, cost and power, using digital calibration for breaking through the performance bottleneck of analog circuits will be the general trend of high speed high resolution TIADC design in future.
This thesis researches digitally assisted design technique for high performance TIADC. Exploring universal design principle and design flew of the digital assisted analog integrated circuits. Depending on the completeness of digital signal processing knowledge,achieving digital calibration by using digital post processing technique to inhibit the detrimental effect on dynamic performance of the TIADC resulted from the mismatches among channels. Designing system-level, behavior-level and circuit-level verification platform for completed design and verification
Firstly, A novel mutual-prime-channel-group TIADC based on split-ADC and its general architecture are presented. The sources of channel mismatch errors and the error effects are studied systematically, and a channel model with mismatch errors is given. System architectures, basic theories, and algorithm implementation of TIADC with channel mismatches calibration are thorough discussed. On the basis of split-ADC calibration concept, basic principle of time-interleaved ADC using split design technique is researched in depth, sufficient conditions and design method of mutual-prime-channel-group TIADC based on split-ADC are presented.
Secondly, all-digital channel mismatches calibration technique aiming at the mutual-prime-channel-group TIADC is presented. This technique can adaptively calibrate offset mismatch, gain mismatch and timing skew mismatch among channels simultaneously at background, eliminating performance limitations which are brought about by mismatches for TIADC. The calibration algorithm is based on least-mean-square iteration which has advantages of low computational complexity and easy in complementation. To guarantee effective calibration when input frequency of the TIADC is high, a cascaded compensation scheme for correction of high-order timing skew errors is employed and good calibrating performance is demonstrated with normalized input frequency near Nyquist frequency. In this thesis, a7-channel split-ADC based TIADC is taken as an example to prove the architecture of mutual-prime-channel-group TIADC and its mismatches digital background calibration. Moreover, the proposed architecture and the associated calibration technique can be expanded to channels of any number.
Finally, a14-bit125MS/s pipelined ADC is designed, and using it as channel unit for developing a circuit platform of the proposed TIADC architecture, in combination with the implementation of the calibration algorithm by FPGA, verifications for the correctness and the practicability of the proposed TIADC architecture and calibration scheme are done. Verification results show that, with3%full scale range offset mismatch,2%gain mismatch and2%sampling period timing skew mismatch, spurious free dynamic range and signal to noise and distortion rate improve about50dBc, achieve92dBc and84dBc respectively, effective number of bits improves8bits, achieve13.7bits which approaches the single channel resolution of the TIADC. This reveals the proposed digital calibration technique does eliminate the nonideal effects brought about by channel mismatch and improves TIADC dynamic performance.
引文
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