基于NAND Flash的嵌入式图像记录技术
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摘要
NAND Flash具有功耗低、体积小、重量轻、固态化、发热少、抗震能力强、工作温度宽等优点，非常适合用来设计使用环境严酷的超高速图像记录系统。本文针对基于NAND Flash设计记录系统存在的一系列关键技术问题，分别提出和实现了满足高性能要求的系统架构和数据流控制算法。
针对如何提高NAND Flash物理底层访问速度问题，研究了NAND Flash的内部结构和工作原理，分析了各类操作的物理底层驱动逻辑。在FPGA中分别实现了操作NAND Flash的各种时序。从理论层面研究了传统的片外流水线和并行技术，并提出了片外两级流水和内部交叉写入结合的方法。通过FPGA硬件实现，证明了本文提出的方法具有最大流水线加速比，能有效提高写入速度，同时减少了FPGA引脚资源占用。
针对坏块表的快速检索和可靠存储问题，提出了基于位索引的坏块信息快速检索结构；为解决坏块快速匹配问题，提出了基于滑动窗口的无效块预匹配机制；对于突发坏块造成写入速度下降问题，提出了滞后回写机制。坏块管理全部用硬件实现；提出并实现了一种高效的并适合于顺序数据流记录的损耗均衡方法。同时提出和实现了一种NAND Flash扩展方法，能有效避免NAND Flash记录系统要使用多个NAND Flash控制器的情况，节省了FPGA内部资源；
针对嵌入式超高速图像记录应用中，任务如何有效管理的问题，设计了超高速图像数据流内存缓存机制，实现了高带宽图像数据缓存和任务附加信息实时嵌入。提出了一种两级数据索引机制，并详细阐述了任务管理的映射关系。为保证记录数据的安全性，实现了任务管理相关表项在NOR Flash中的备份和定时更新机制。实践表明，以上方法能够有效降低CPU开销，适合在嵌入式系统中应用。
针对记录系统性能测试问题，设计了测试模型，包括：针对系统可靠性初步测试问题，设计了基于指数回归的速度压力模型和基于对数正态分布的测试时长控制模型；针对峰值记录速度测定问题，提出了基于爬山搜索算法和速率二分法的软硬件协同测试方法。通过FPGA实现，验证了提出方法的有效性。
为了推进相关研究成果的工程实用化，设计并实现了光电经纬仪NANDFlash嵌入式图像记录系统。分别研究和实现了光纤、PCIE、千兆网传输、DVI显示回放以及基于WEB服务器的记录系统远程管理技术。结果表明，该系统最大记录带宽可达1260MB/s，容量可达8TB；最后，研究了结构紧凑多模块记录系统，设计了3U CPCIE记录模块。该系统可根据具体需求增加和裁剪记录模块，实现不同的记录性能。
The NAND Flash has versatile features such as low-power consumption, excellenttemperature tolerance ability, non-volatility, high random access performance,solid-state reliability, shock resistance, and high mobility. It is suitable for designinghigh-speed image recorder system used in extreme environment. In this paper, to solvethe various problems involved in designing NAND Flash-based image recording system,architectures and algorithms that are more suitable for engineering applications andhave better performance are proposed.
For how to improve the access speed of the NAND Flash, this paper studies theinternal structure and working principle of the NAND Flash, analysis the drive timingof various operations and realizes the various drive timing of NAND Flash's operationsin the FPGA respectively. This paper researchs traditional pipelining and paralleltechnologies theoretically, finally, proposes an new method based on NAND flashon-chip interleave write and off-chip2level pipelining. Through the various controltechniques implemented in FPGA, it is demonstrated that the method presented has thelargest pipelining speedup, can effectively improve the writing speed while reducing theFPGA pin occupancy.
In order to solve the problem of invalid block table’s fast search and reliable store,an invalid block information fast search architecture based on bit index is proposed. Aninvalid block pre-matching mechanism based on glide window is proposed to solve theproblem of invalid block’s fast matching. In consideration of the disadvantage thatburst invalid block will decrease write speed, this paper presents a lag copy backmechanism. Architecture is implemented in form of hardware. Moreover, efficientwear-leveling method suitable for sequence recording system is proposed andimplemented. At the same time, this paper proposes and implements a IO transformmethod, which can effectively avoid the NAND Flash recording system to use more ofthe NAND Flash controller, greatly saving FPGA internal resources.
The problem of how to facilitate efficient task management for high-speed image recording is researched. Then, high-speed image memory caching mechanism isdesigned. This paper realizes the high-speed image data cache and additionalinformation embedding real-timely, presents a two-stage data indexing mechanism, andexpounds the mapping of task management in detail. To ensure the security of recordingdata, the task management related tables backup and update in NOR Flash. The practiceshows that these mechanisms can reduce the CPU cost, shorten the query time of taskinformation and image data, and is suitable for application in embedded system.
In order to determine the elementary reliability of the recorder and the peakrecording speed, new load test models are designed. To solve the problem of stabilitytest, speed load model based on exponential regression and test time control modelbased on the lognormal distribution are proposed; to test the peak recording speed, thispaper presents the test methods combining hardware with software based on climbingsearch algorithm and speed dichotomy. These methods are implemented in the FPGA,the effectiveness of the proposed methods is verified.
In order to promote practical engineering application of the relevant researchresults, this paper proposes and realizes the photoelectric theodolite NAND Flashembedded image recording system. The optical fiber, PCIE, gigabit networktransmission, DVI display technology, and remote management technology based onWEB server are researched and realized respectively. The results show that theconsecutive write speed is up to1260MB/s, the storage capacity is up to4TB. In the endof this paper, the compact military ATR recording system is researched. The3U CPCIErecording module scheme is proposed and drew. The system can obtain different recordperformance according to increase or cut the record module according to the specificdemand.
针对如何提高NAND Flash物理底层访问速度问题，研究了NAND Flash的内部结构和工作原理，分析了各类操作的物理底层驱动逻辑。在FPGA中分别实现了操作NAND Flash的各种时序。从理论层面研究了传统的片外流水线和并行技术，并提出了片外两级流水和内部交叉写入结合的方法。通过FPGA硬件实现，证明了本文提出的方法具有最大流水线加速比，能有效提高写入速度，同时减少了FPGA引脚资源占用。
针对坏块表的快速检索和可靠存储问题，提出了基于位索引的坏块信息快速检索结构；为解决坏块快速匹配问题，提出了基于滑动窗口的无效块预匹配机制；对于突发坏块造成写入速度下降问题，提出了滞后回写机制。坏块管理全部用硬件实现；提出并实现了一种高效的并适合于顺序数据流记录的损耗均衡方法。同时提出和实现了一种NAND Flash扩展方法，能有效避免NAND Flash记录系统要使用多个NAND Flash控制器的情况，节省了FPGA内部资源；
针对嵌入式超高速图像记录应用中，任务如何有效管理的问题，设计了超高速图像数据流内存缓存机制，实现了高带宽图像数据缓存和任务附加信息实时嵌入。提出了一种两级数据索引机制，并详细阐述了任务管理的映射关系。为保证记录数据的安全性，实现了任务管理相关表项在NOR Flash中的备份和定时更新机制。实践表明，以上方法能够有效降低CPU开销，适合在嵌入式系统中应用。
针对记录系统性能测试问题，设计了测试模型，包括：针对系统可靠性初步测试问题，设计了基于指数回归的速度压力模型和基于对数正态分布的测试时长控制模型；针对峰值记录速度测定问题，提出了基于爬山搜索算法和速率二分法的软硬件协同测试方法。通过FPGA实现，验证了提出方法的有效性。
为了推进相关研究成果的工程实用化，设计并实现了光电经纬仪NANDFlash嵌入式图像记录系统。分别研究和实现了光纤、PCIE、千兆网传输、DVI显示回放以及基于WEB服务器的记录系统远程管理技术。结果表明，该系统最大记录带宽可达1260MB/s，容量可达8TB；最后，研究了结构紧凑多模块记录系统，设计了3U CPCIE记录模块。该系统可根据具体需求增加和裁剪记录模块，实现不同的记录性能。
The NAND Flash has versatile features such as low-power consumption, excellenttemperature tolerance ability, non-volatility, high random access performance,solid-state reliability, shock resistance, and high mobility. It is suitable for designinghigh-speed image recorder system used in extreme environment. In this paper, to solvethe various problems involved in designing NAND Flash-based image recording system,architectures and algorithms that are more suitable for engineering applications andhave better performance are proposed.
For how to improve the access speed of the NAND Flash, this paper studies theinternal structure and working principle of the NAND Flash, analysis the drive timingof various operations and realizes the various drive timing of NAND Flash's operationsin the FPGA respectively. This paper researchs traditional pipelining and paralleltechnologies theoretically, finally, proposes an new method based on NAND flashon-chip interleave write and off-chip2level pipelining. Through the various controltechniques implemented in FPGA, it is demonstrated that the method presented has thelargest pipelining speedup, can effectively improve the writing speed while reducing theFPGA pin occupancy.
In order to solve the problem of invalid block table’s fast search and reliable store,an invalid block information fast search architecture based on bit index is proposed. Aninvalid block pre-matching mechanism based on glide window is proposed to solve theproblem of invalid block’s fast matching. In consideration of the disadvantage thatburst invalid block will decrease write speed, this paper presents a lag copy backmechanism. Architecture is implemented in form of hardware. Moreover, efficientwear-leveling method suitable for sequence recording system is proposed andimplemented. At the same time, this paper proposes and implements a IO transformmethod, which can effectively avoid the NAND Flash recording system to use more ofthe NAND Flash controller, greatly saving FPGA internal resources.
The problem of how to facilitate efficient task management for high-speed image recording is researched. Then, high-speed image memory caching mechanism isdesigned. This paper realizes the high-speed image data cache and additionalinformation embedding real-timely, presents a two-stage data indexing mechanism, andexpounds the mapping of task management in detail. To ensure the security of recordingdata, the task management related tables backup and update in NOR Flash. The practiceshows that these mechanisms can reduce the CPU cost, shorten the query time of taskinformation and image data, and is suitable for application in embedded system.
In order to determine the elementary reliability of the recorder and the peakrecording speed, new load test models are designed. To solve the problem of stabilitytest, speed load model based on exponential regression and test time control modelbased on the lognormal distribution are proposed; to test the peak recording speed, thispaper presents the test methods combining hardware with software based on climbingsearch algorithm and speed dichotomy. These methods are implemented in the FPGA,the effectiveness of the proposed methods is verified.
In order to promote practical engineering application of the relevant researchresults, this paper proposes and realizes the photoelectric theodolite NAND Flashembedded image recording system. The optical fiber, PCIE, gigabit networktransmission, DVI display technology, and remote management technology based onWEB server are researched and realized respectively. The results show that theconsecutive write speed is up to1260MB/s, the storage capacity is up to4TB. In the endof this paper, the compact military ATR recording system is researched. The3U CPCIErecording module scheme is proposed and drew. The system can obtain different recordperformance according to increase or cut the record module according to the specificdemand.
引文
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