片上高性能嵌入式计算—面向软基带的应用并行处理模型及体系结构
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摘要
以无线通信为代表的高性能嵌入式计算已深入到国民生活、工业生产和军事科技等各个领域,由于各种高性能嵌入式计算目标应用的计算复杂度、功耗预算、实时性约束变化多样且不断加强,当前高性能嵌入式计算正在经历由以通用数字信号处理器和通用高性能嵌入式处理器为中心的传统高性能嵌入式计算向领域优化高性能嵌入式计算转变。无线通信协议不断演进,人们对多模通信的需求不断增加,采用可编程处理技术完成基带处理的软基带应用逐渐兴起。由于具备高计算复杂度、高性能功耗比约束、强实时性的特点,软基带应用成为了推动高性能嵌入式计算模式转变的主要因素之一,使得高性能嵌入式计算的体系结构和实现技术面临全新的挑战,特别是以MIMO-OFDM(Multi-Input Multi-Output Orthogonal Frequency Division Multiplexing)系统为代表的软基带应用的计算需求随着无线通信系统的演进不断强化,给面向软基带的片上系统体系结构设计带来了前所未有的挑战。研究面向以MIMO-OFDM系统为代表的软基带应用的片上高性能嵌入式计算体系结构具有明显意义。
本文在总结分析MIMO-OFDM系统模型的基础上,对以MIMO-OFDM基带系统为代表的软基带应用并行处理模型、面向软基带的可预测异构多核体系结构、面向软基带的多模多域无冲突并行存储结构、LDPC(Low Desity Parity Check)码译码算法和加速处理单元体系结构以及Reed Solomon (RS)码译码算法和加速处理单元体系等几个方面的重点内容展开了深入研究,概括本文所取得的创新性工作主要有以下几点：
A.给出了面向基于MIMO-OFDM软基带的应用并行处理模型,包括数据流模型、空时二维数据并行模型以及“本原”操作模型。数据流模型描述了基带核心任务之间的数据流关系以及流量量化模型；空时二维数据并行模型描述了核心任务内部存在的特有数据级并行层次和并行度；“本原”操作模型则描述了各种基带任务的任务本身所特有的操作序列模型。通过并行处理模型实例分析了典型MIMO-OFDM基带系统计算模式的演化过程,包括核心操作的复杂度演化、“本原”操作并行度演化、以及任务间通信流量演化。
B.提出并研究了领域优化可编程处理单元。领域优化可编程处理单元采用标量／向量混合处理技术,并借助VLIW(Very Large Instruction Word)和SIMD(Single Instruction,Multiple Data-stream)技术支持目标应用的各种计算模式；当采用SIMD技术加速核心算法的“本原”操作时考虑到存在大量簇间数据交换操作,本文所提的领域优化可编程向量处理单元内建支持了通用以及若干种专用的簇间数据交换网络。本文采用电子系统级设计方法完成了领域优化可编程向量处理单元的建模和实现,并通过典型算法分析了领域优化可编程向量处理单元相对于传统信号处理器的加速比,结果表明所研究的可编程向量处理单元在处理和目标应用密切相关的核心算法时具有比较明显的加速比。
C.在总结软基带应用的主要访存模式的基础上提出了专用存储组织模型,并基于该存储组织模型,提出了支持主要访存模式无冲突访问的可扩展多模多域无冲突并行存储体系结构模型和实现技术,结合所提领域专用可编程处理单元进行访存通路流水线实现,并针对无线通信目标应用的存储特点进行了仿真。实现结果表明本文所提出的多模多域无冲突并行存储体系结构的扩展性良好,且实现开销和相关存储结构基本相同；仿真结果表明：针对无线通信目标应用,可扩展多模多域无冲突并行存储体系结构相比于传统并行存储体系结构有明显的加速比。
D.针对前向纠错系统中新近应用较广的具有很高纠错性能的LDPC码的译码复杂度较高的实际,提出了RMP调度最小和算法(RMP-Min-Sum算法)。RMP-Min-Sum算法采用了行消息传递方式降低算法的迭代次数,并采用最小和译码算法消除译码算法中的非线性操作,降低硬件实现代价,仿真表明RMP-Min-Sum的译码性能和传统和积算法相比具有相当性能,而复杂度则明显降低。本文研究了RMP-Min-Sum软译码的可行性,研究表明当前可编程处理器无法高效能实现长帧LDPC码的译码。最后针对扩展非规则累积LDPC码给出了基于RMP-Min-Sum算法的并行加速单元体系结构,结合DVB-S2 LDPC码进行了加速单元实现,并对加速单元的并行度、复杂度以及吞吐率进行了演化,实现结果表明：采用RMP-Min-Sum算法的LDPC码译码加速单元在保证提供同等量级的吞吐率的基础上,可大幅降低硬件开销。
E.提出了支持RS码译码结构的宏流水负载均衡的关键多项式求解算法：TD-iBM算法。TD-iBM算法采用了分时调度各个伽罗华域乘法器技术,通过时间换取面积的方式,在保证译码吞吐率的同时,提高了译码加速单元宏流水的均衡度,并降低了译码加速单元的面积开销,提高了译码效率。本文基于TD-iBM算法实现了RS(255,223)码型以及相关截断码的译码加速单元,实验表明：与现有的主要RS译码器相比,本文所实现的RS译码加速单元具有一定译码效率优势。
F.基于可编程向量处理单元以及若干前向纠错加速单元提出并研究了可预测多核片上系统体系结构以及原型系统。本文采用片内总线作为多核互连的基础,并针对强实时性需求引入了软件可控的时分复用总线,该总线以很小硬件代价提供了设计时可预测、可控的总线分配模式,且设计人员可通过编制不同总线调度程序支持各种总线分配策略；考虑到软件可控的时分复用总线提供了设计时可预测、可控的总线分配策略,其为日益增加的总线功耗的降低提供了可能。基于可编程向量处理单元、前向纠错加速单元以及软件可控的时分复用总线,给出了可预测多核片上系统体系结构原型,并给出了面向简化的MIMO-OFDM基带系统流水映射方式的优化原型实现。
综上所述,本文面向以MIMO-OFDM基带系统为代表的软基带应用,研究了应用并行处理模型、领域优化多核体系结构和实现技术、高效能并行存储体系结构以及前向纠错系统核心算法改进和加速实现技术,对于推动面向软基带的片上高性能嵌入式计算的研究和实用化具有一定的意义和价值。
High Performance Embedded Computing (HPEC) including wireless computing is ubiquitous in society life, industry application and military technology. The computing complexity, power budget and real-time constraint of different HPEC applications are varied and strengthening, the morden HPEC is undergoing the transformation from the traditional HPEC based on general Digital Signal Processor and general high performance embedded processor to domain specific HPEC. The soft baseband, which is resulting from the evolution of wireless protocols and the requirements of muti-mode communication, is one of the main driving applications of domain specific HPEC. The architecture design of On-Chip High Performance Embedded Computing (OCHPEC) for software baseband is being challenged for its high computing complexity, high performance power ratio constraint and high real-time constraint, especially when MIMO-OFDM baseband system is involved. Besides, to meeting the computing requirements of the evoluting wireless protocols is also an issue of architecture design of OCHPEC for soft baseband.
Based on the analysis of the MIMO-OFDM system model, this dissertation focuses on the following research points:soft baseband application parallel processing model for MIMO-OFDM, Predictable Heterogeneous Multi-Processor System-on-Chip (PH-MPSoC) architecture, multi-pattern multi-domain conflict-free parallel memory architecture, Low Desity Parity Check (LDPC) code decoding algorithm/accelerator and Reed Solomon code decoding algorithm/accelerator. The key contributions are summarized as follows.
A. The application parallel processing model for MIMO-OFDM based soft baseband is introduced, including data stream model, space-time 2-dimension data level parallel model and atom operaion model. The data stream model describes the data stream dependency relationship between the baseband tasks, and the stream quantifing model; space-time 2-dimension data level parallel model describes the data level parallelism of the baseband tasks; atom operaion model describes the specific operaion sequences of MIMO-OFDM baseband tasks. A typical MIMO-OFDM baseband system is analyzed based on this application parallel processing model, the complexity evolution of the kernel operaion, the parallelism evolution of the atom operaions and the stream flux evolution of the tasks are showed.
B. Domain specific programmable process unit is proposed and researched. The proposed programmable process unit adopts scalar and vector hybrid processing technique. It introduces VLIW and SIMD to support the varied computing patterns in target applications. It introduces general and application specific inter-cluster data exchange network to accerating the atom operaion when SIMD technique is used. ESL methodology and tools are used to model and implement the domain specific programmable process unit. Some typical algorithms are used for evaluating the performance of the domain specific programmable process unit. The results shows the proposed domain specific programmable process unit is more efficient than others in the kernel algorithms of wireless communication
C. A domain specific memory organization model is proposed after analyzing of main memory access patterns. Based on the memory organization model, a Multi-Pattern and Multi-Domain conflict free Parallel Memory Architecture (MPMD-PMA) model for the main memory access patterns is proposed. The implementation detail and the pipelined case study of MPMD-PMA is done based on the proposed domain specific programmable PE, and the memory access simulation experiments have been done in the behavior simulator. The implementation results show the expansibility of MPMD-PMA is equivalent with general PMA; and the simulation results show the performance speedup of MPMD-PMA over general PMA in soft baseband memory access patterns is significant.
D. RMP-Min-Sum decoding algorithm for LDPC codes, which is the newest FEC code, is proposed to reduce the LDPC decoding complexity. RMP-Min-Sum introduces the Row Message Passage pattern to reduce the decoding iterations, and Min-Sum algorithm to reduce the complexity of the kernel operations. The simulation results show the application value of RMP-Min-Sum decoding algorithm is significant. The hardware cost of the RMP-Min-Sum decoding implementation in software has evaluated, and the results show it is not a high efficient solution for long frame structure LDPC code. Then, the parallel accelerator architecture based on RMP-Min-Sum decoding algorithm for eIRA-LDPC code is proposed, and the case study of DVB-S2 LDPC decoder is showed. The results show hardware cost of the parallel accelerator based on RMP-Min-Sum decoding is less than other LDPC decoder.
E. TD-iBM:a Key Equation Solver (KES) algorithm for supporting RS decoding balanced macro-pipeline architecture is proposed. It adopts time division scheduling of the Galois Field multipliers in iBM based KES algorithm to reduce the complexity of KES and balance the macro-pipeline. Decoding accelerator architecture for RS (255,223) and its truncation codes is proposed based on TD-iBM algorithm. The results show the decoding accelerator based on TD-iBM algorithm is an area-efficient decoding accelerator.
F. Predictable Heterogeneous Multi-Processor System-on-Chip (PH-MPSoC) architecture and prototype are proposed based on the programmable process unit and some FEC accelerators. In PH-MPSoC architecture, Software Controlling -Time Division Multiplexing bus (SC-TDM bus) is introduced to offer the predictable interconnection timing. SC-TDM bus offer the design time bus scheduling scheme with little hardware cost, and different bus scheduling patterns can be introduced by programmer. Besides, the design time predictable bus scheduling scheme can be used to reduce the power cost of the interconnection. The PH-MPSoC prototype is proposed, and optimized prototype implementation is designed for the simplified MIMO-OFDM baseband system pipeline mapping scheme.
In summary, this dissertation investigates soft baseband application parallel processing model, domain specific MPSoC architecture and implementation technology, high efficient parallel memory architecture and FEC decoding algorithm and accelerator architecture. The contributions of this dissertation are useful in driving the development of the OCHEPC for soft baseband processing.
本文在总结分析MIMO-OFDM系统模型的基础上,对以MIMO-OFDM基带系统为代表的软基带应用并行处理模型、面向软基带的可预测异构多核体系结构、面向软基带的多模多域无冲突并行存储结构、LDPC(Low Desity Parity Check)码译码算法和加速处理单元体系结构以及Reed Solomon (RS)码译码算法和加速处理单元体系等几个方面的重点内容展开了深入研究,概括本文所取得的创新性工作主要有以下几点：
A.给出了面向基于MIMO-OFDM软基带的应用并行处理模型,包括数据流模型、空时二维数据并行模型以及“本原”操作模型。数据流模型描述了基带核心任务之间的数据流关系以及流量量化模型；空时二维数据并行模型描述了核心任务内部存在的特有数据级并行层次和并行度；“本原”操作模型则描述了各种基带任务的任务本身所特有的操作序列模型。通过并行处理模型实例分析了典型MIMO-OFDM基带系统计算模式的演化过程,包括核心操作的复杂度演化、“本原”操作并行度演化、以及任务间通信流量演化。
B.提出并研究了领域优化可编程处理单元。领域优化可编程处理单元采用标量／向量混合处理技术,并借助VLIW(Very Large Instruction Word)和SIMD(Single Instruction,Multiple Data-stream)技术支持目标应用的各种计算模式；当采用SIMD技术加速核心算法的“本原”操作时考虑到存在大量簇间数据交换操作,本文所提的领域优化可编程向量处理单元内建支持了通用以及若干种专用的簇间数据交换网络。本文采用电子系统级设计方法完成了领域优化可编程向量处理单元的建模和实现,并通过典型算法分析了领域优化可编程向量处理单元相对于传统信号处理器的加速比,结果表明所研究的可编程向量处理单元在处理和目标应用密切相关的核心算法时具有比较明显的加速比。
C.在总结软基带应用的主要访存模式的基础上提出了专用存储组织模型,并基于该存储组织模型,提出了支持主要访存模式无冲突访问的可扩展多模多域无冲突并行存储体系结构模型和实现技术,结合所提领域专用可编程处理单元进行访存通路流水线实现,并针对无线通信目标应用的存储特点进行了仿真。实现结果表明本文所提出的多模多域无冲突并行存储体系结构的扩展性良好,且实现开销和相关存储结构基本相同；仿真结果表明：针对无线通信目标应用,可扩展多模多域无冲突并行存储体系结构相比于传统并行存储体系结构有明显的加速比。
D.针对前向纠错系统中新近应用较广的具有很高纠错性能的LDPC码的译码复杂度较高的实际,提出了RMP调度最小和算法(RMP-Min-Sum算法)。RMP-Min-Sum算法采用了行消息传递方式降低算法的迭代次数,并采用最小和译码算法消除译码算法中的非线性操作,降低硬件实现代价,仿真表明RMP-Min-Sum的译码性能和传统和积算法相比具有相当性能,而复杂度则明显降低。本文研究了RMP-Min-Sum软译码的可行性,研究表明当前可编程处理器无法高效能实现长帧LDPC码的译码。最后针对扩展非规则累积LDPC码给出了基于RMP-Min-Sum算法的并行加速单元体系结构,结合DVB-S2 LDPC码进行了加速单元实现,并对加速单元的并行度、复杂度以及吞吐率进行了演化,实现结果表明：采用RMP-Min-Sum算法的LDPC码译码加速单元在保证提供同等量级的吞吐率的基础上,可大幅降低硬件开销。
E.提出了支持RS码译码结构的宏流水负载均衡的关键多项式求解算法：TD-iBM算法。TD-iBM算法采用了分时调度各个伽罗华域乘法器技术,通过时间换取面积的方式,在保证译码吞吐率的同时,提高了译码加速单元宏流水的均衡度,并降低了译码加速单元的面积开销,提高了译码效率。本文基于TD-iBM算法实现了RS(255,223)码型以及相关截断码的译码加速单元,实验表明：与现有的主要RS译码器相比,本文所实现的RS译码加速单元具有一定译码效率优势。
F.基于可编程向量处理单元以及若干前向纠错加速单元提出并研究了可预测多核片上系统体系结构以及原型系统。本文采用片内总线作为多核互连的基础,并针对强实时性需求引入了软件可控的时分复用总线,该总线以很小硬件代价提供了设计时可预测、可控的总线分配模式,且设计人员可通过编制不同总线调度程序支持各种总线分配策略；考虑到软件可控的时分复用总线提供了设计时可预测、可控的总线分配策略,其为日益增加的总线功耗的降低提供了可能。基于可编程向量处理单元、前向纠错加速单元以及软件可控的时分复用总线,给出了可预测多核片上系统体系结构原型,并给出了面向简化的MIMO-OFDM基带系统流水映射方式的优化原型实现。
综上所述,本文面向以MIMO-OFDM基带系统为代表的软基带应用,研究了应用并行处理模型、领域优化多核体系结构和实现技术、高效能并行存储体系结构以及前向纠错系统核心算法改进和加速实现技术,对于推动面向软基带的片上高性能嵌入式计算的研究和实用化具有一定的意义和价值。
High Performance Embedded Computing (HPEC) including wireless computing is ubiquitous in society life, industry application and military technology. The computing complexity, power budget and real-time constraint of different HPEC applications are varied and strengthening, the morden HPEC is undergoing the transformation from the traditional HPEC based on general Digital Signal Processor and general high performance embedded processor to domain specific HPEC. The soft baseband, which is resulting from the evolution of wireless protocols and the requirements of muti-mode communication, is one of the main driving applications of domain specific HPEC. The architecture design of On-Chip High Performance Embedded Computing (OCHPEC) for software baseband is being challenged for its high computing complexity, high performance power ratio constraint and high real-time constraint, especially when MIMO-OFDM baseband system is involved. Besides, to meeting the computing requirements of the evoluting wireless protocols is also an issue of architecture design of OCHPEC for soft baseband.
Based on the analysis of the MIMO-OFDM system model, this dissertation focuses on the following research points:soft baseband application parallel processing model for MIMO-OFDM, Predictable Heterogeneous Multi-Processor System-on-Chip (PH-MPSoC) architecture, multi-pattern multi-domain conflict-free parallel memory architecture, Low Desity Parity Check (LDPC) code decoding algorithm/accelerator and Reed Solomon code decoding algorithm/accelerator. The key contributions are summarized as follows.
A. The application parallel processing model for MIMO-OFDM based soft baseband is introduced, including data stream model, space-time 2-dimension data level parallel model and atom operaion model. The data stream model describes the data stream dependency relationship between the baseband tasks, and the stream quantifing model; space-time 2-dimension data level parallel model describes the data level parallelism of the baseband tasks; atom operaion model describes the specific operaion sequences of MIMO-OFDM baseband tasks. A typical MIMO-OFDM baseband system is analyzed based on this application parallel processing model, the complexity evolution of the kernel operaion, the parallelism evolution of the atom operaions and the stream flux evolution of the tasks are showed.
B. Domain specific programmable process unit is proposed and researched. The proposed programmable process unit adopts scalar and vector hybrid processing technique. It introduces VLIW and SIMD to support the varied computing patterns in target applications. It introduces general and application specific inter-cluster data exchange network to accerating the atom operaion when SIMD technique is used. ESL methodology and tools are used to model and implement the domain specific programmable process unit. Some typical algorithms are used for evaluating the performance of the domain specific programmable process unit. The results shows the proposed domain specific programmable process unit is more efficient than others in the kernel algorithms of wireless communication
C. A domain specific memory organization model is proposed after analyzing of main memory access patterns. Based on the memory organization model, a Multi-Pattern and Multi-Domain conflict free Parallel Memory Architecture (MPMD-PMA) model for the main memory access patterns is proposed. The implementation detail and the pipelined case study of MPMD-PMA is done based on the proposed domain specific programmable PE, and the memory access simulation experiments have been done in the behavior simulator. The implementation results show the expansibility of MPMD-PMA is equivalent with general PMA; and the simulation results show the performance speedup of MPMD-PMA over general PMA in soft baseband memory access patterns is significant.
D. RMP-Min-Sum decoding algorithm for LDPC codes, which is the newest FEC code, is proposed to reduce the LDPC decoding complexity. RMP-Min-Sum introduces the Row Message Passage pattern to reduce the decoding iterations, and Min-Sum algorithm to reduce the complexity of the kernel operations. The simulation results show the application value of RMP-Min-Sum decoding algorithm is significant. The hardware cost of the RMP-Min-Sum decoding implementation in software has evaluated, and the results show it is not a high efficient solution for long frame structure LDPC code. Then, the parallel accelerator architecture based on RMP-Min-Sum decoding algorithm for eIRA-LDPC code is proposed, and the case study of DVB-S2 LDPC decoder is showed. The results show hardware cost of the parallel accelerator based on RMP-Min-Sum decoding is less than other LDPC decoder.
E. TD-iBM:a Key Equation Solver (KES) algorithm for supporting RS decoding balanced macro-pipeline architecture is proposed. It adopts time division scheduling of the Galois Field multipliers in iBM based KES algorithm to reduce the complexity of KES and balance the macro-pipeline. Decoding accelerator architecture for RS (255,223) and its truncation codes is proposed based on TD-iBM algorithm. The results show the decoding accelerator based on TD-iBM algorithm is an area-efficient decoding accelerator.
F. Predictable Heterogeneous Multi-Processor System-on-Chip (PH-MPSoC) architecture and prototype are proposed based on the programmable process unit and some FEC accelerators. In PH-MPSoC architecture, Software Controlling -Time Division Multiplexing bus (SC-TDM bus) is introduced to offer the predictable interconnection timing. SC-TDM bus offer the design time bus scheduling scheme with little hardware cost, and different bus scheduling patterns can be introduced by programmer. Besides, the design time predictable bus scheduling scheme can be used to reduce the power cost of the interconnection. The PH-MPSoC prototype is proposed, and optimized prototype implementation is designed for the simplified MIMO-OFDM baseband system pipeline mapping scheme.
In summary, this dissertation investigates soft baseband application parallel processing model, domain specific MPSoC architecture and implementation technology, high efficient parallel memory architecture and FEC decoding algorithm and accelerator architecture. The contributions of this dissertation are useful in driving the development of the OCHEPC for soft baseband processing.
引文
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