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MPEG音频编码算法的研究和VLSI前端设计
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摘要
在卫星数字电视广播领域,我国采用国际上通用的MPEG-1层Ⅱ双声道立体声编码算法,然而这种编码算法需要大量的数据操作,必须用专用硬件来实现。本文对此算法进行了优化和软件验证,并研究了硬件实现的方法。
     本文主要包含了以下几个方面的内容:
     首先,通过与其它几种常用压缩算法的比较,阐述了MPEG编码算法在音频压缩位率和质量上的优点,并详细分析了MPEG音频编码算法的国际标准。利用Matlab数学工具实现了MPEG-1层Ⅱ音频编、解码过程。在此基础上,提出编码系统的硬件结构。
     其次,分析了硬件结构中各个模块并估计了它们的运算复杂性,然后对子带滤波器组和心理声学模型作了进一步的探讨,提出了基于FFT的高效实现算法及其硬件结构。结合硬件的特点,利用Matlab工具建模验证了算法的正确性。根据该算法的硬件结构,编写了结构中所有的Verilog HDL模型,并成功进行了仿真和逻辑综合。
     最后,在MPEG-1层Ⅱ编码的硬件结构的基础上,结合计算机并口通信和Flash存储器的接口模块,采用现场可编程逻辑器件FPGA技术,最终设计了一种应用于音频信号存储的MPEG音频编码系统。完成了该系统的VLSI结构设计和Verilog HDL模型描述,并进行验证。
In the field of satellite digital television broadcast, our country employs the MPEG-1 layers II dual channel stereo coding algorithm. However, the large amount of data operation is required in this kind of algorithm and it cannot be implemented without the Application Specific Integrated Circuit. In the paper, the algorithm procedure is optimized and verified with software, and a hardware-base system is searched.
    This thesis consists of the following contents:
    First, the differences of the MPEG coding and some generally audio coding algorithms are compared, and the MPEG coding plays better than others in rate and quality. The MPEG audio coding international standard is analyzed in detail, and the model of the MPEG audio coding and decoding system set up with the MATLAB mathematics tools. At last, the encoding hardware structure of MPEG-1 layer II is put forward.
    Second, in the paper, we have analyzed every module of the structure and estimated it's complexity. Then the sub-band filter bank and psycho- acoustic modules are more investigated. A more efficient algorithm based on Fast Fourier Transform is introduced, and we join together the character of the hardware to improve it's hardware construction. Furthermore the validity of algorithm has been verified using the Matlab tool. Programs with Verilog language, which describe all modules of the hardware construction, have been given and succeed in the logic simulation and synthesis.
    
    
    Finally, on the basis of the MPEG-1 layer Hencoding hardware structure, the block of logic communicates with the PC over the parallel port and the interface for Flash memory are design. Then a MPEG audio coding system, which applies to store audio signal, is presented through the field programmable gate array device technology. The Verilog HDL models of the coder are programmed, and verified.
引文
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