关于HDL测试的研究
摘要
在现代微电子设计过程中，随着门电路数目和系统复杂性以指数倍增，功能测试的作用日益变得重要，人们将在测试上投入更多的人力物力。为了保证系统测试的快捷和精确，我们必须改进测试工具，革新测试方法，探讨独立于开发工具和设计过程的测试方法。
本文首先阐述了测试平台的基本概念；归纳了常用的功能测试方法：白箱测试、黑箱测试和灰箱测试，并说明了其不同的应用场合；列举了常用的测试工具：代码静态分析工具、代码检查、仿真器、示波器和代码覆盖；接着讨论了如何在测试计划中分析测试粒度、确定待测特征；阐明了待测特征、测试实例和测试平台之间的结构关系。和TRL代码相比，行为描述代码可以减少代码量和测试的工作量，提高仿真的性能，并更有利于在串行处理器上实现并行结构。并在此基础之上，探讨了在测试平台中如何产生各种激发信号；如何对波形的产生过程进行封装；以及如何解决死锁和异步接口的问题，与此对应，也论述了响应和激发之间的反馈、预测输出结果和响应的检测和激发的产生并行处理等问题。最后研究了如何通过优化结构来提高构件和模型的可再用性；对采用不可再用和可再用结构的测试平台进行了比较，得出了后者更能提高测试效率的结论，并通过实际的编程验证了这个结论；提出了总线功能模型的封装方法；给出了i386SX总线功能模型的结构、代码和调用过程，并在使模型自动激发和监控方面做了初步的尝试。
In the modern micro-electronics designs, with gates counts and system complexity growing exponentially, function verification will play a more and more important role, and verification will consume more design effort. To rapid and accurate system verification, new and innovative approaches and more powerful tools should be introduced, and verification approaches independent of tools and designs should be pursued.
At first, the article describes the basic concept of testbench; summaries general function verification approaches: white-box verification, black-box verification, and grey-box verification, and shows their different application situations; examples general verification tools: linting tools, code review, simulator, waveform viewer and code coverage. After doing that, it discusses how to analysis the granularity for verification and how to specify the verification, and details the construct relations between verification specification, testcase and testbench. Compared to RTL code, using behavioral code can reduce code and verification effort, improve simulation performance, and it is prone to realize parallel constructs on serial processor. And on the basis of that, the paper probes into how to generate stimulus in the testbench, how to encapsulate waveform generation , how to avoid deadlock and how to find a solution to asynchronous interface. It also discourse on the feedback between stimulus and response,
the prediction of output and the concurrent of response verification and stimulus generation. Finally, it researches on how to optimize constructs in order to improve the reusability of components and models, compares the testbench using the non-reusable structure with that using the reusable structure, concludes that the latter can improve the verification efficiency, verifies the conclusion by programming a few examples, proposes the way of encapsulating bus functional model, gives the constructs , code and recall of i386SX bus function model, and attempts to realize model generation automation and monitoring automation.
本文首先阐述了测试平台的基本概念；归纳了常用的功能测试方法：白箱测试、黑箱测试和灰箱测试，并说明了其不同的应用场合；列举了常用的测试工具：代码静态分析工具、代码检查、仿真器、示波器和代码覆盖；接着讨论了如何在测试计划中分析测试粒度、确定待测特征；阐明了待测特征、测试实例和测试平台之间的结构关系。和TRL代码相比，行为描述代码可以减少代码量和测试的工作量，提高仿真的性能，并更有利于在串行处理器上实现并行结构。并在此基础之上，探讨了在测试平台中如何产生各种激发信号；如何对波形的产生过程进行封装；以及如何解决死锁和异步接口的问题，与此对应，也论述了响应和激发之间的反馈、预测输出结果和响应的检测和激发的产生并行处理等问题。最后研究了如何通过优化结构来提高构件和模型的可再用性；对采用不可再用和可再用结构的测试平台进行了比较，得出了后者更能提高测试效率的结论，并通过实际的编程验证了这个结论；提出了总线功能模型的封装方法；给出了i386SX总线功能模型的结构、代码和调用过程，并在使模型自动激发和监控方面做了初步的尝试。
In the modern micro-electronics designs, with gates counts and system complexity growing exponentially, function verification will play a more and more important role, and verification will consume more design effort. To rapid and accurate system verification, new and innovative approaches and more powerful tools should be introduced, and verification approaches independent of tools and designs should be pursued.
At first, the article describes the basic concept of testbench; summaries general function verification approaches: white-box verification, black-box verification, and grey-box verification, and shows their different application situations; examples general verification tools: linting tools, code review, simulator, waveform viewer and code coverage. After doing that, it discusses how to analysis the granularity for verification and how to specify the verification, and details the construct relations between verification specification, testcase and testbench. Compared to RTL code, using behavioral code can reduce code and verification effort, improve simulation performance, and it is prone to realize parallel constructs on serial processor. And on the basis of that, the paper probes into how to generate stimulus in the testbench, how to encapsulate waveform generation , how to avoid deadlock and how to find a solution to asynchronous interface. It also discourse on the feedback between stimulus and response,
the prediction of output and the concurrent of response verification and stimulus generation. Finally, it researches on how to optimize constructs in order to improve the reusability of components and models, compares the testbench using the non-reusable structure with that using the reusable structure, concludes that the latter can improve the verification efficiency, verifies the conclusion by programming a few examples, proposes the way of encapsulating bus functional model, gives the constructs , code and recall of i386SX bus function model, and attempts to realize model generation automation and monitoring automation.
引文
[1] The Programmable Logic DATA BOOK. Xilinx Incorporation San Jose USA, 1999
[2] 专用集成电路和集成系统自动化设计方法，中国集成电路大全[M]．北京：国防工业出版社，1997
[3] Mayer R J ed. "IDEFO Function Modeling", KBSI, 1990
[4] Mayer R J ed. "IDEF1X Data Modeling", KBSI, 1990
[5] 潘松．VHDL实用教程．电子科技大学出版社，2000
[6] 宋万杰，罗丰，吴顺君．CPLD技术及其应用．西安电子科技大学出版社，1999
[7] 侯伯亨，顾新．VHDL硬件描述语言与数字逻辑电路设计(修订版)．西安电子科技大学出版社，1995
[8] Mayer R J et al. "IDEF3 process description capture method report", AL-TR-1992-0057, KBSI, 1992
[9] Mayer R J et al. "IDEF4 objected-oriented design method report", AL-TR-1992-0056, KBSI, 1992
[10] Benjamin P C et al, "IDEF5 report", KBSI, 1994
[11] Mayer R J et al. "Information Integeration for Concurrent Engineering(IICE) Compendium of methods report", KBSI, 1995
[12] Hamzaolu I, Patel J H. New techniques for deterministic test pattern generation[J]. Electronic Testing: Theory and Application, 1999; 15:63-73
[13] 徐志军，徐光辉等．大规模可编程逻辑器件及其应用．成都电子科技大学出版社，2000
[14] 陈禹六．IDEF建模分析和设计方法．清华大学出版社，1998
[15] 陈禹六等．IDEFO及IDEF1X——复杂系统通用的设计分析方法．电子工业出版社，1999
[16] 陈禹六，谢斌，董亚男．计算机集成制造 (CIM) 系统设计和实施方法论．清华大学出版社，1996
[17] Roth J P. Computer logic, testing, and verification [M]. Potomac, MD: Computer Science Press, 1990
[18] Goel P An implicit enumeration algorithm to generate tests for combinational logic circuits [J]. IEEE Trans Comput, 1991: 30(2): 215-228
[19] Fujiwara H, Shimono T. On the acceleration of test generation algorithms [J]. IEEE Trans Comput, 1993; 32(12): 1137-1144
[20] Hansen M C, Hayes J P. High-level test generation using physically-induced faults [A]. VLSI Test Symposium Paper [C]. 1995
[21] 赵慧玲，张国宏．ATM、帧中继测试技术．电子工业出版社，1998
[22] 宋保维．系统可靠性设计与分析．西北工业大学出版社，2000
[23] 梅启智，廖炯生．系统可靠性基础．科学出版社，1990
[24] 章国栋，陆庭孝．系统可靠性与维修性的分析与设计．北京航空航天大学，1990
[25] Tsai K H, Rajski J, Marek-Sadowska M. Star test: the theory and its applications [J]. IEEE Trans Computer-Aided Design, 2000; 19(9): 1052-1063
[26] Brglez F, Fujiwara H. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran [A]. Proc IEEE Int Symp Circ Syst [C]. 1995
[27] Ciletti M D. Modeling, synthesis, and rapid prototyping with the Verilog HDL[M]. USA: Prentice-Hall, Inc. 1999,63-64
[28] Keating M, Bricaud P. Reuse methodology manual: for system-on-a-chip design[M]. 2nd Ed. USA: Kluwer Academic Publishers. 1999, 31-32
[29] Petlin O, Genusov A, Wakeman L. Methodology and code reuse in the verification of telecommunication SOCs [A]. Proc 13th Annual IEEE Int ASIC/SOC Conf [C], 2000,187-191.
[30] Panigrahi D, Taylor C N, Dey S. Interface based hardware/software validation of a system-on-chip [A]. Proc IEEE Int High-Level Design Validation and Test Workshop [C], 2000, 53-58
[31] IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture[S], IEEE, 1990
[32] Whetsel L. An IEEE 1149.1-based test access architecture for IC"s with embedded cords [A], Proc IEEE Int Test Conf [C], 1997, 69-78
[33] Cong J, Pan Z. Interconnect delay estimation models for synthesis and design planning [A]. Proc Asic and South Pacific Design Automation Conf [C]. 1999, 97-100
[34] Ismail Y I, Friedman E G, Neves J L. Figures of merit to characterize the importance of on-chip inductance [J]. IEEE Trans VLSI Syst, 1999; 7(4): 442-449
[35] Cong J, leung K S. Optimal wire sizing under the distributed Elmore delay model [A]. Proc Int Conf Computer Aided design [C]. 1993, 634-639
[36] Ismail Y J, Friedman E G, Neves J L. Signal wave-form characterization in RLC trees[A] Proc Int Symp Cir Syst[C]. 1999, 190-193
[37] Gupta R, Tutuianu B, Pileggi P T. The Elmore delay as a bound for RC trees with generalized input signals [J] IEEE Trans Computer-Aided Design, 1997; 16(1): 95-104
[38] van Ginneken L P P P. Buffer placement in distributed RC-tree networks for minimal Elmore delay [A]. Proc Int Symp Circ Syst [C]. 1990, 865-868
[39] Kay R, Pillage L T. EWA: efficient wiring-sizing algorithm for signal nets and clock nets [J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 1998: 17(1)
[40] Chu C C N, Wong D F. A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing [J]. IEEE Trans Computer_Aided Design, 1999; 16(6): 787-798
[41] 韩雁．专用集成电路设计技术基础．成都电子科技大学出版社，2000
[42] 张明．Verilog HDL实用教程[M]．成都电子科技大学出版社，1999
[43] Synopsys.SYNOPSYS静态验证技术[M]．2000
[2] 专用集成电路和集成系统自动化设计方法，中国集成电路大全[M]．北京：国防工业出版社，1997
[3] Mayer R J ed. "IDEFO Function Modeling", KBSI, 1990
[4] Mayer R J ed. "IDEF1X Data Modeling", KBSI, 1990
[5] 潘松．VHDL实用教程．电子科技大学出版社，2000
[6] 宋万杰，罗丰，吴顺君．CPLD技术及其应用．西安电子科技大学出版社，1999
[7] 侯伯亨，顾新．VHDL硬件描述语言与数字逻辑电路设计(修订版)．西安电子科技大学出版社，1995
[8] Mayer R J et al. "IDEF3 process description capture method report", AL-TR-1992-0057, KBSI, 1992
[9] Mayer R J et al. "IDEF4 objected-oriented design method report", AL-TR-1992-0056, KBSI, 1992
[10] Benjamin P C et al, "IDEF5 report", KBSI, 1994
[11] Mayer R J et al. "Information Integeration for Concurrent Engineering(IICE) Compendium of methods report", KBSI, 1995
[12] Hamzaolu I, Patel J H. New techniques for deterministic test pattern generation[J]. Electronic Testing: Theory and Application, 1999; 15:63-73
[13] 徐志军，徐光辉等．大规模可编程逻辑器件及其应用．成都电子科技大学出版社，2000
[14] 陈禹六．IDEF建模分析和设计方法．清华大学出版社，1998
[15] 陈禹六等．IDEFO及IDEF1X——复杂系统通用的设计分析方法．电子工业出版社，1999
[16] 陈禹六，谢斌，董亚男．计算机集成制造 (CIM) 系统设计和实施方法论．清华大学出版社，1996
[17] Roth J P. Computer logic, testing, and verification [M]. Potomac, MD: Computer Science Press, 1990
[18] Goel P An implicit enumeration algorithm to generate tests for combinational logic circuits [J]. IEEE Trans Comput, 1991: 30(2): 215-228
[19] Fujiwara H, Shimono T. On the acceleration of test generation algorithms [J]. IEEE Trans Comput, 1993; 32(12): 1137-1144
[20] Hansen M C, Hayes J P. High-level test generation using physically-induced faults [A]. VLSI Test Symposium Paper [C]. 1995
[21] 赵慧玲，张国宏．ATM、帧中继测试技术．电子工业出版社，1998
[22] 宋保维．系统可靠性设计与分析．西北工业大学出版社，2000
[23] 梅启智，廖炯生．系统可靠性基础．科学出版社，1990
[24] 章国栋，陆庭孝．系统可靠性与维修性的分析与设计．北京航空航天大学，1990
[25] Tsai K H, Rajski J, Marek-Sadowska M. Star test: the theory and its applications [J]. IEEE Trans Computer-Aided Design, 2000; 19(9): 1052-1063
[26] Brglez F, Fujiwara H. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran [A]. Proc IEEE Int Symp Circ Syst [C]. 1995
[27] Ciletti M D. Modeling, synthesis, and rapid prototyping with the Verilog HDL[M]. USA: Prentice-Hall, Inc. 1999,63-64
[28] Keating M, Bricaud P. Reuse methodology manual: for system-on-a-chip design[M]. 2nd Ed. USA: Kluwer Academic Publishers. 1999, 31-32
[29] Petlin O, Genusov A, Wakeman L. Methodology and code reuse in the verification of telecommunication SOCs [A]. Proc 13th Annual IEEE Int ASIC/SOC Conf [C], 2000,187-191.
[30] Panigrahi D, Taylor C N, Dey S. Interface based hardware/software validation of a system-on-chip [A]. Proc IEEE Int High-Level Design Validation and Test Workshop [C], 2000, 53-58
[31] IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture[S], IEEE, 1990
[32] Whetsel L. An IEEE 1149.1-based test access architecture for IC"s with embedded cords [A], Proc IEEE Int Test Conf [C], 1997, 69-78
[33] Cong J, Pan Z. Interconnect delay estimation models for synthesis and design planning [A]. Proc Asic and South Pacific Design Automation Conf [C]. 1999, 97-100
[34] Ismail Y I, Friedman E G, Neves J L. Figures of merit to characterize the importance of on-chip inductance [J]. IEEE Trans VLSI Syst, 1999; 7(4): 442-449
[35] Cong J, leung K S. Optimal wire sizing under the distributed Elmore delay model [A]. Proc Int Conf Computer Aided design [C]. 1993, 634-639
[36] Ismail Y J, Friedman E G, Neves J L. Signal wave-form characterization in RLC trees[A] Proc Int Symp Cir Syst[C]. 1999, 190-193
[37] Gupta R, Tutuianu B, Pileggi P T. The Elmore delay as a bound for RC trees with generalized input signals [J] IEEE Trans Computer-Aided Design, 1997; 16(1): 95-104
[38] van Ginneken L P P P. Buffer placement in distributed RC-tree networks for minimal Elmore delay [A]. Proc Int Symp Circ Syst [C]. 1990, 865-868
[39] Kay R, Pillage L T. EWA: efficient wiring-sizing algorithm for signal nets and clock nets [J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 1998: 17(1)
[40] Chu C C N, Wong D F. A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing [J]. IEEE Trans Computer_Aided Design, 1999; 16(6): 787-798
[41] 韩雁．专用集成电路设计技术基础．成都电子科技大学出版社，2000
[42] 张明．Verilog HDL实用教程[M]．成都电子科技大学出版社，1999
[43] Synopsys.SYNOPSYS静态验证技术[M]．2000
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