RS译码算法的研究及RS（256，252）译码器的实现
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摘要
纠错编译码技术在卫星通信、移动通信以及数据存储领域已获得了广泛的应用，其中RS（Reed-Solomon）码是最重要的、也是研究最多的码类之一。很多国际标准采用了RS码，比如空间数据系统咨询委员会（CCSDS）在遥测信道编码的建议书中将RS(255,223)系统码作为标准使用，高级在轨系统（AOS）也采用了RS码。
本课题研究的主要内容是RS码的译码算法及RS（256，252）译码器的实现，重点是RS（256，252）译码器的实现。RS（256，252）码是由RS（255，252）码拓展而来。它的每个码块长度n=256,信息位符号数k=252, 纠错能力E=2。也就是说，只要每个码块中发生错误的码符号数不多于两个，它都能够给予准确无误地纠正。
RS（256，252）译码器的设计过程主要包括输入数据的存储、伴随式的计算、乘法器和除法器的设计、关键方程的求解等几个步骤。在硬件电路的设计过程中用的仿真软件是Xilinx Foundation 3.1，主要采用了原理图设计方式，部分模块使用了VHDL。最后用Xilinx的FPGA芯片XC2S200PQ208C-5实现了其全部设计，译码速率可达到100Mbps，译码延时为321个字节时钟周期。
由于该译码器有较高的纠错速率和规则的设计结构，使它可以方便地用于数据传输和存储过程中进行差错控制。
Du Pingzhou (Computer Application)
Directed by Prof.Sun Huixian
Error-correction coding is used widely in satellite communications, mobile communications and data storing. Reed-Solomon code is one of the most useful Error-correction codes, which has been accepted by CCSDS AOS as part of standard protocol.
This paper focuses on the algorithm of RS decoder and the implementation of RS（256，252）decoder. RS（256，252）code is extended from RS（255，252）code ,a byte-wide single error-correcting and double-error detecting cyclic block code. Considering RS（256，252）code, its block length n equals to 256 with each block containing 252 8-bit information symbols over the finite field GF(). The number of error symbols that can be corrected by the decoder is 2.
The design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation. During the course of designing circuit, I use the software Xilinx Foundation 3.1 in the associated manner of VHDL and schematic. Finally, this decoder is implemented by FPGA－XC2S200PQ208C-5. It operates very well at up to 100Mbps with 321 bytes delay.
Since this decoder has high error-correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate.
本课题研究的主要内容是RS码的译码算法及RS（256，252）译码器的实现，重点是RS（256，252）译码器的实现。RS（256，252）码是由RS（255，252）码拓展而来。它的每个码块长度n=256,信息位符号数k=252, 纠错能力E=2。也就是说，只要每个码块中发生错误的码符号数不多于两个，它都能够给予准确无误地纠正。
RS（256，252）译码器的设计过程主要包括输入数据的存储、伴随式的计算、乘法器和除法器的设计、关键方程的求解等几个步骤。在硬件电路的设计过程中用的仿真软件是Xilinx Foundation 3.1，主要采用了原理图设计方式，部分模块使用了VHDL。最后用Xilinx的FPGA芯片XC2S200PQ208C-5实现了其全部设计，译码速率可达到100Mbps，译码延时为321个字节时钟周期。
由于该译码器有较高的纠错速率和规则的设计结构，使它可以方便地用于数据传输和存储过程中进行差错控制。
Du Pingzhou (Computer Application)
Directed by Prof.Sun Huixian
Error-correction coding is used widely in satellite communications, mobile communications and data storing. Reed-Solomon code is one of the most useful Error-correction codes, which has been accepted by CCSDS AOS as part of standard protocol.
This paper focuses on the algorithm of RS decoder and the implementation of RS（256，252）decoder. RS（256，252）code is extended from RS（255，252）code ,a byte-wide single error-correcting and double-error detecting cyclic block code. Considering RS（256，252）code, its block length n equals to 256 with each block containing 252 8-bit information symbols over the finite field GF(). The number of error symbols that can be corrected by the decoder is 2.
The design process includes storing the input data, calculating the syndromes, designing multiplier and divider and solving the key equation. During the course of designing circuit, I use the software Xilinx Foundation 3.1 in the associated manner of VHDL and schematic. Finally, this decoder is implemented by FPGA－XC2S200PQ208C-5. It operates very well at up to 100Mbps with 321 bytes delay.
Since this decoder has high error-correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate.
引文
1.H.M.Shao,T.K.Truong,L.J.Deutsh,J.H.Yuen,and I.S.Reed"A VLSI design of a pipeline Reed-Solomon decoder," IEEE Trans.Comput., vol C-34,pp. 393-402,May 1985.
2.T.Iwaki,T.Tanaka,E.Yamada,T.Okuda,and T.Sasada, "Architecture of a high speed Reed-Solomon decoder," IEEE Trans.Consumer Electron., vol.40,pp.75-82,FEB.1994
3.Jah-ming Hau and Chin-Liang Wang, "an Area-Efficient Pipelined VLSI Architecture for Decoding of Reed-solomon Codes Based on a Time-Domain Algorithm"IEEE Trans.circuit and systemfor video technology vol.7 No.6 December 1997。
4.周云生, "47M译码器的实现" 通信学报 vol,17 no.3 may 1996。
5.肖国镇, <<编码理论>> 国防工业出版社，1993。
6.Man Young Rhee <> McGraw-Hill Publishing Company,1989.
7.S.T.J.Femn,M.Beaissa and D.Taylor, "improved algorithm for division over GF(2m)",Electronics Letters 4 th March 1993 vol.29 no.5.
8.Howard M.shao and Irving S.reed , "On the VLSI Desing of a Pipeline Reed-Solomon Decoder Using Systolic Arrays",IEEE tran.on com,vol.37 No.10,October 1988.
9.于伟, "一种ＲＳ码变换域译码算法及关键方程的讨论．" 空间电子技术 No.2 2000.
10.Chistof Pssr and Martin Rosner， "Comparison of Arithmetic Architectures for Reed-Solomon Decoders in Reconfigurable Hardware" IEEE,Department of Electrical and Computer Engineering Worcester Polytechic Institute,0-8186-8159-4/97.
11．M.S.Hodgart，"Efficient coding and error monitoring for spacecraft digital memory" INT.J.Electronics,1992, vol.73, No.1,1-36.
2.T.Iwaki,T.Tanaka,E.Yamada,T.Okuda,and T.Sasada, "Architecture of a high speed Reed-Solomon decoder," IEEE Trans.Consumer Electron., vol.40,pp.75-82,FEB.1994
3.Jah-ming Hau and Chin-Liang Wang, "an Area-Efficient Pipelined VLSI Architecture for Decoding of Reed-solomon Codes Based on a Time-Domain Algorithm"IEEE Trans.circuit and systemfor video technology vol.7 No.6 December 1997。
4.周云生, "47M译码器的实现" 通信学报 vol,17 no.3 may 1996。
5.肖国镇, <<编码理论>> 国防工业出版社，1993。
6.Man Young Rhee <
7.S.T.J.Femn,M.Beaissa and D.Taylor, "improved algorithm for division over GF(2m)",Electronics Letters 4 th March 1993 vol.29 no.5.
8.Howard M.shao and Irving S.reed , "On the VLSI Desing of a Pipeline Reed-Solomon Decoder Using Systolic Arrays",IEEE tran.on com,vol.37 No.10,October 1988.
9.于伟, "一种ＲＳ码变换域译码算法及关键方程的讨论．" 空间电子技术 No.2 2000.
11．M.S.Hodgart，"Efficient coding and error monitoring for spacecraft digital memory" INT.J.Electronics,1992, vol.73, No.1,1-36.
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