基于V93000的现场可编程门阵列测试时间优化方法
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摘要
对于现场可编程门阵列FPGA,测试配置时间远大于加测试向量的时间,为实现FPGA快速配置测试,本文提出了一种FPGA测试时间优化方法:采用Advantest公司V93000自动测试设备,通过在一个周期内加载4行配置向量对电路配置比特流的测试时间进行优化(即4X配置方式),并结合FPGA多帧写位流压缩方法对电路测试配置的编程加载时间进行优化;以Xilinx公司Virtex-7系列FPGA-XC7VX485T为例进行了测试验证,测试数据表明:采用V93000SoC测试系统的4X配置方式,FPGA的单次配置时间减少了74.1%;为了满足量产测试对于测试时间的要求,进一步提出V93000的4X配置方式与FPGA的位流压缩相结合的方法,FPGA的单次配置时间由1.047s减少到47.834ms,测试时间压缩了95.5%.该方法有效减少了FPGA单次测试时间,提高了在系统配置速度.
For the field programmable gate array FPGA,the test configuration time is much longer than the time of adding the test vector.In order to realize the FPGA fast configuration test,an FPGA test time optimization method is proposed.Using the Advantest V93000 automatic test equipment,the test time of the circuit configuration bit stream is optimized by loading 4rows of configuration vectors in one cycle(ie 4X configuration).And combined with the FPGA multi-frame write bit stream compression method to optimize the programming load time of the circuit test configuration.Taking Xilinx Virtex-7 series FPGA-XC7VX485 Tas an example to test and verify.The test data shows that with the 4X configuration of the V93000 SoC test system,the FPGA's single configuration time is reduced by 74.1%.In order to meet the requirements of the mass production test for test time,the method is further proposed which combine the 4X configuration of the V93000 with the bitstream compression of the FPGA.The single configuration time of the FPGA is reduced from 1.047 sto 47.834 ms,and the test time is compressed by 95.5%.This method effectively reduces the single test time of the FPGA and improves the system configuration speed.
For the field programmable gate array FPGA,the test configuration time is much longer than the time of adding the test vector.In order to realize the FPGA fast configuration test,an FPGA test time optimization method is proposed.Using the Advantest V93000 automatic test equipment,the test time of the circuit configuration bit stream is optimized by loading 4rows of configuration vectors in one cycle(ie 4X configuration).And combined with the FPGA multi-frame write bit stream compression method to optimize the programming load time of the circuit test configuration.Taking Xilinx Virtex-7 series FPGA-XC7VX485 Tas an example to test and verify.The test data shows that with the 4X configuration of the V93000 SoC test system,the FPGA's single configuration time is reduced by 74.1%.In order to meet the requirements of the mass production test for test time,the method is further proposed which combine the 4X configuration of the V93000 with the bitstream compression of the FPGA.The single configuration time of the FPGA is reduced from 1.047 sto 47.834 ms,and the test time is compressed by 95.5%.This method effectively reduces the single test time of the FPGA and improves the system configuration speed.
引文
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[2]陈田,梁华国,王伟,等.基于优化编码的LFSR重播种测试压缩方案[J].计算机研究与发展,2012,49(2):443-451.Chen Tian,Liang Huaguo,Wang Wei,et al.A test compression scheme based on LFSR reseeding and optimized coding[J].Journal of Computer Research and Development,2012,49(2):443-451.(in Chinese)
[3]张玲.数字电路测试激励压缩研究[D].长沙:湖南大学,2013.
[4]解维坤,陈龙,黄晋,等.FPGA测试压缩技术研究[J].电子与封装,2018,18(5):8-11.Xie Weikun,Chen Long,Huang Jin,et al.Research on test compression technology of FPGA[J].Electronics&Packaging,2018,18(5):8-11.(in Chinese)
[5]吉国凡,赵智昊,杨嵩.基于ATE的FPGA测试方法[J].电子测试,2007(12):43-46.Ji Guofan,Zhao Zhihao,Yang Song.FPGA testing method based on ATE[J].Electronic Test,2007(12):43-46.(in Chinese)
[6]解维坤,万清,章慧彬.基于测试系统的FPGA测试方法研究[J].电子与封装,2013(5):6-8.Xie Weikun,Wan Qing,Zhang Huibin.FPGA testing method on the test system[J].Electronics&Packaging,2013(5):6-8.(in Chinese)
[7]胡海涛,钟明琛,刘彬.用于测试FPGA的MultiPort下载方式[J].信息技术与标准化,2012(8):75-77.Hu Haitao,Zhong Mingchen,Liu Bin.Configuration based on Multi-Pport for FPGA testing[J].Information Technology&Standardization,2012(8):75-77.(in Chinese)
[8]Agilent Technologies.The ASCII Interface Reference Manual[M].Revision 3.2.0,2001.
[9]陈辉,姚若河,王晓晗,等.一种ATE测试向量时序优化算法[J].微电子学,2011,41(2):310-314.Chen Hui,Yao Ruohe,Wang Xiaohan,et al.An algorithm for optimizing timing of test vector in ATE[J].Microelectronics,2011,41(2):310-314.(in Chinese)
[10]王华.基于ATE的FPGA测试技术研究和应用[J].电子与封装,2018(7):12-15.Wang Hua.Research and application of FPGA testing technology based on ATE[J].Electronics&Packaging,2018(7):12-15.(in Chinese)
[11]Xilinx Inc.7Series FPGAs Configuration User Guide[Z].San Jose,USA:Xilinx,2018.
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