An 8-bit parallel DAC with segmented architecture

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• 作者：M. S. Enuchenko ; D. V. Morozov…
• 刊名：Journal of Communications Technology and Electronics
• 出版年：2017
• 出版时间：January 2017
• 年：2017
• 卷：62
• 期：1
• 页码：89-100
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Communications Engineering, Networks;
• 出版者：Pleiades Publishing
• ISSN：1555-6557
• 卷排序：62

文摘

An 8-bit parallel DAC with a segmented architecture that employs a 4-bit binary and an unary segments is presented. A switched current source and a thermometric decoder are discussed. A test chip is fabricated using a 180-nm CMOS technology. Measured results show higher conversion rate and smaller chip area in comparison with other papers.