应用于流水线型模数转换器的采样保持电路的研究与设计
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摘要
近年来,模数转换器(ADC)在制造工艺、结构、性能上都有了突飞猛进的发展,正在朝着高速、高分辨率的方向发展。采样保持电路用于流水线型模数转换器的最前端,其输出信号精度和建立速度直接影响到整个流水线型模数转换器的分辨率和转换速率,因此采样保持电路的设计成为流水线型模数转换器电路设计的关键环节。本文针对8 bit 25 MHz Pipelined ADC的应用为目标进行采样保持电路的研究与设计。
本文主要研究应用于流水线型模数转换器中的采样保持电路的相关设计技术。首先从采样保持电路的基本理论入手,详细分析了采样保持电路采样模式和保持模式工作原理。其次对于各个模式下影响采样保持电路性能的非理想因素进行全面而深入的分析。在采样模式下主要分析了影响模拟开关性能的因素如电荷注入效应、开关时钟馈通效应、开关电阻的非线性等;在保持模式下主要对运放的建立时间的数学模型进行了详细的研究,同时对比分析了各种结构运算放大器的性能。然后运用MATLAB对整个系统进行建模分析,建模时为了模拟实际情况,对影响采样保持电路性能的非理想因素也进行了建模。在进行实际电路设计时,针对影响模拟开关性能的各个因素提出了相应的改进方案,在设计运放时运用了几何规划方法对运算放大器进行了优化设计。
最后基于0.18μm CMOS工艺模型在Cadence环境下对电路进行了模拟仿真。仿真结果表明,在输入信号为12.5 MHz正弦波,采样频率为25 MHz时,大信号建立时间为7.76 ns,建立误差小于117.49μV。对输出信号进行离散傅里叶变换(DFT)得到SNR为57.27 dB,达到了8 bit 25 MHz Pipelined ADC采样频率技术指标,研究设计的采样保持电路可以应用于相应的模数转换器中。
In recent years, analog-to-digital converters have gained great development in process, architecture and performance. Sample and hold circuit is developing towards high speed and high precision which is in the front of the ADC. The setting error and setting speed are the most important parameters of the Sample-and-Hold circuit which affects the resolution and speed of the whole pipelined ADC directly. Therefore the design of sample and hold circuit become the most important cell in pipelined ADC. An 8 bit 25 MHz pipelined ADC S/H circuit is introduced in this thesis.
The relevant techniques about the design of Sample-and-Hold circuit in pipelined ADC are discussed in this thesis. Firstly, Starting from basic principles of Sample and hold circuit, we analysis the sample and hold modes in details. Secondly we analysis the Non-ideal factors impacting the Sample-and-hold circuit in every mode fully and deeply. Factors effecting analog switch performance in the holding mode, such as charge injection, switch clock feed-through, Nonlinear of switch resistance and so on are analyzed as well. We study Mathematical model of set-up time of operational amplifier in details while at the same time, comparisons of Various-structure operational amplifier performance are made. Then Modeling in Matlab is used to analysis the whole system. And for situation of Non-ideal circumstances, we propose the improvement for every factor effecting analog switch performance, and use Optimum Designing for operational amplifier with the generalized geometric method.
The sample and hold circuit is simulated by Cadence with standard 0.18μm CMOS process model. The simulation shows that with 12.5 MHz input sine-waves which is at 25 MHz sampling rate, gain error is less than 117.49μV, slewing settling time reached 7.76 ns, SNR for the output DFT is 57.27 dB while Pipelined ADC sampling rate optimized to be 8 bit 25 MHz Pipelined ADC. Sample and hold circuit designed in this thesis can be applied to related ADC.
本文主要研究应用于流水线型模数转换器中的采样保持电路的相关设计技术。首先从采样保持电路的基本理论入手,详细分析了采样保持电路采样模式和保持模式工作原理。其次对于各个模式下影响采样保持电路性能的非理想因素进行全面而深入的分析。在采样模式下主要分析了影响模拟开关性能的因素如电荷注入效应、开关时钟馈通效应、开关电阻的非线性等;在保持模式下主要对运放的建立时间的数学模型进行了详细的研究,同时对比分析了各种结构运算放大器的性能。然后运用MATLAB对整个系统进行建模分析,建模时为了模拟实际情况,对影响采样保持电路性能的非理想因素也进行了建模。在进行实际电路设计时,针对影响模拟开关性能的各个因素提出了相应的改进方案,在设计运放时运用了几何规划方法对运算放大器进行了优化设计。
最后基于0.18μm CMOS工艺模型在Cadence环境下对电路进行了模拟仿真。仿真结果表明,在输入信号为12.5 MHz正弦波,采样频率为25 MHz时,大信号建立时间为7.76 ns,建立误差小于117.49μV。对输出信号进行离散傅里叶变换(DFT)得到SNR为57.27 dB,达到了8 bit 25 MHz Pipelined ADC采样频率技术指标,研究设计的采样保持电路可以应用于相应的模数转换器中。
In recent years, analog-to-digital converters have gained great development in process, architecture and performance. Sample and hold circuit is developing towards high speed and high precision which is in the front of the ADC. The setting error and setting speed are the most important parameters of the Sample-and-Hold circuit which affects the resolution and speed of the whole pipelined ADC directly. Therefore the design of sample and hold circuit become the most important cell in pipelined ADC. An 8 bit 25 MHz pipelined ADC S/H circuit is introduced in this thesis.
The relevant techniques about the design of Sample-and-Hold circuit in pipelined ADC are discussed in this thesis. Firstly, Starting from basic principles of Sample and hold circuit, we analysis the sample and hold modes in details. Secondly we analysis the Non-ideal factors impacting the Sample-and-hold circuit in every mode fully and deeply. Factors effecting analog switch performance in the holding mode, such as charge injection, switch clock feed-through, Nonlinear of switch resistance and so on are analyzed as well. We study Mathematical model of set-up time of operational amplifier in details while at the same time, comparisons of Various-structure operational amplifier performance are made. Then Modeling in Matlab is used to analysis the whole system. And for situation of Non-ideal circumstances, we propose the improvement for every factor effecting analog switch performance, and use Optimum Designing for operational amplifier with the generalized geometric method.
The sample and hold circuit is simulated by Cadence with standard 0.18μm CMOS process model. The simulation shows that with 12.5 MHz input sine-waves which is at 25 MHz sampling rate, gain error is less than 117.49μV, slewing settling time reached 7.76 ns, SNR for the output DFT is 57.27 dB while Pipelined ADC sampling rate optimized to be 8 bit 25 MHz Pipelined ADC. Sample and hold circuit designed in this thesis can be applied to related ADC.
引文
[1]朱樟明,杨银堂.高速ADC(模拟数字转换器)结构设计技术.半导体技术, 2003, 28(5): 65-69
[2]李福乐.适宜于系统集成的高速高精度模数转换器电路设计技术研究: [博士学位论文].北京:清华大学电子工程系, 2003.
[3] Bin Le, Rondeau T W, Reed J H, Bostian C W. Analog-to-digital Converters. IEEE Signal Processing Magazine, 2005, 22(6): 80-92
[4] Mikko Waltari. Integration of High-Speed CMOS Sample-and-Hold Circuits: [Master thesis]. Finland, Helsinki University of Technology, 1999.
[5] Hirotomo Ishii, Ken Tanabe, Tetsuya Iida. A 1.0 V 40 mW 10 bit 100 MS/s pipeline ADC in 90 nm CMOS. IEEE Custom Integrated Circuits Conference, 2005: 395-398
[6] Park Jong-Bum, Yoo Sang-Min, Kim Se-Won, et al. A 10 bit 150 MS/s 1.8 V 123 mW CMOS A/D Converter with 400 MHz Input Bandwidth. IEEE Journal of Solid-State Circuits, 2004, 39(8): 1335-1337
[7] Chouia Y, El-Sankary K, Saleh A, et al. 14 bit 50 MS/s CMOS Front-End Sample and Hold Module Dedicated to a Pipelined ADC. IEEE International Midwest Symposium on Circuits and Systems, 2004, 1: 353-356
[8]兀革.一种模拟开关两步法ADC的CMOS实现研究: [博士学位论文].北京:中科院半导体研究所, 2000.
[9] Behzad Razavi. Principles of Data Conversion System Design. New York: IEEE Press, 1995. 10-15
[10] Alan V Oppenheim, Alan S Willsky, Nawab S Hamid. Signals and Systems.第二版.北京:清华大学出版社, 1998. 55-97
[11] Abraham Peled, Bede Liu. Digital signal processing: theory, design, and implementation. New York: Wiley, 1976. 20-27
[12] Alan V Oppenheim, Ronald W Schafer, John R Buck. Discrete-time Signal Processing. Second Edition. New Jersey: Prentice Hall, 1999. 64-86
[13] Jacsik Lee, Pascal Roux, Koc Ut-Va, et al. A 5 bit 10 GS/s A/D Converter for 10 Gb/s Optical Receivers. IEEE Journal of Solid-State Circuits, 2004, 39(10): 1671-1679
[14] Mehradad Nayebi, Bruce A Wooley. A 10 bit Video BiCMOS Track-and-Hold Amplifier. IEEE Journal of Solid-State Circuits, 1989, 24(6): 1507-1516
[15] Van P Peteghem, Sanaen W. Single versus complementary switches: A discussion of clock feed-through in SC circuits. Europe Solid-State Circuits Conference. Delft, the Netherlands, 1986: 16-18
[16] Miki T, Kouno H, Kumamoto T, Kanoshita Y, Igarashi T, Okada K. A 10 bit 50 MS/s 500 mW A/D converter using a differential-voltage sub-converter. IEEE Journal of Solid-State Circuits, 1994, 29(4): 516-522
[17] Shu T H, Bacrania K, Goanale R. A 10 bit 40 MS/s BiCMOS A/D Converter. IEEE Journal of Solid-State Circuits, 1996, 31(10): 1507-1510
[18] Cho T B, Paul R Gray. A 10 bit 20 MS/s 35 mW pipeline A/D Converter. IEEE Custom Integrated Circuits Conference, 1994, 30(3): 166-172
[19] Larry Singer, Stacy Ho, Mike Timko, et al. A 12 bit 65 MS/s CMOS ADC with 82 dB SFDR at 120 MHz. IEEE Proceedings of 2000 International Solid-State Circuits Conference, 2000: 38-39
[20] Wenhua Yang, Dan Kelly, Iuri Mehr, et al. A 3 V 340 mW 14 bit 75 MS/s CMOS ADC with 85 dB SFDR at Nyquist Input. IEEE JSSCC, 2001, 36(12): 1931-1936
[21] Shinagawa M, Akazawa Y, Wakimoto T. Jitter Analysis of High-Speed Sampling Systems. IEEE Journal of Solid-State Circuits, 1990, 25(1): 220-224
[22] Rudy Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Second Edition. New York: Kluwer Academic Publishers, 2003. 23-25
[23] Wegmann G, Vittoz E A, Rahali F. Charge injection in analog MOS switch. IEEE Journal of Solid-State Circuits, 1987, 22(6): 1091-1097
[24] Bing Sheu, Je-Hurn Shieh, Patil M. Modeling charge injection in MOS analog switches. IEEE Transactions on Circuits and Systems, 1987, 34(2): 214-216
[25] Wilson W B, Massoud H Z, Swanson E J, et al. Measurement and modeling of charge feed-through in n-channel MOS analog switches. IEEE Journal of Solid-StateCircuits, 1985, 20(6): 1206-1213
[26] Behzad Razavi.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003. 165-197
[27] Cho T B. Low-Power, Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures: [Ph.D.Dissertation], Berkeley, University of California, 1995.
[28] Mikael Gustavsson, Wikner J Jacob, Nianxiong N Tan. CMOS Data Converters for Communications. New York: Kluwer Academic Publishers, 2002. 125-127
[29] Abo A M, Paul R Gray. A 1.5 V 10 bit 14 MS/s CMOS Pipeline Analog-to-Digital Converter. IEEE Symposium on VLSI Circuits, 1998: 166-169
[30] Paul R Gray, Paul J Hurst. Analysis and Design of Analog Integrated Circuits. Fourth Edition. New York: Wiley, 2004. 462-465
[31] Bult K,Geelen G J G M. A fast-settling CMOS op-amp for SC circuits with 90 dB DC gain. IEEE Journal of Solid-State Circuits, 1990, 25(6): 1379-1384
[32] Chuang C T. Analysis of the Settling Behavior of an Operational Amplifier, IEEE Journal of Solid-State Circuits, 1982, 17(1): 74-80
[33] Schlarmann M E, Geiger R L. Relationship between amplifier settling time and pole-zero placements for second-order systems. IEEE Proceedings of the 43rd Midwest Symposium on Circuits and Systems, 2000, 1: 54-59
[34] Fernando Silveira, Denis Flandre. Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling Time. IEEE Proceedings of the 15th Symposium on Integrated Circuits and Systems Design, 2002: 247-253
[35] Howard C Yang, David J Allstot. Considerations for fast settling operational amplifiers. IEEE Transactions on Circuits and Systems, 1990, 37(3): 326-334
[36] Bernard E Boser, Bruce A Wooley. The Design of Sigma-Delta Modulation Analog- to-Digital Converters. IEEE Journal of Solid-State Circuits, 1988, 23(6): 1298-1308
[37] Malcovati P, Brigati S, Francesconi F, et al. Behavioral modeling of switched capacitor sigma-delta modulators. IEEE transactions on circuits and systems-II, 2004, 50(3): 352-364
[38] Maria del Mar Hershenson, Stephen P Boyd, Thomas H Lee. Optimal Design of aCMOS op-amp via Geometric Programming. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2001, 20(1): 1-21
[39] Pradip Mandal, Visvanathan V. CMOS Op-Amp Sizing Using a Geometric Programming Formulation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2001, 20(1): 22-38
[40] Maria del Mar Hershenson. CMOS analog circuit design via geometric programming. IEEE American Control Conference, 2004, 30(4): 3266-3271
[41] Maria del Mar Hershenson. Design of pipeline analog-to-digital converters via geometric programming. IEEE/ACM International Conference on Computer Aided Design, 2002: 317-324
[2]李福乐.适宜于系统集成的高速高精度模数转换器电路设计技术研究: [博士学位论文].北京:清华大学电子工程系, 2003.
[3] Bin Le, Rondeau T W, Reed J H, Bostian C W. Analog-to-digital Converters. IEEE Signal Processing Magazine, 2005, 22(6): 80-92
[4] Mikko Waltari. Integration of High-Speed CMOS Sample-and-Hold Circuits: [Master thesis]. Finland, Helsinki University of Technology, 1999.
[5] Hirotomo Ishii, Ken Tanabe, Tetsuya Iida. A 1.0 V 40 mW 10 bit 100 MS/s pipeline ADC in 90 nm CMOS. IEEE Custom Integrated Circuits Conference, 2005: 395-398
[6] Park Jong-Bum, Yoo Sang-Min, Kim Se-Won, et al. A 10 bit 150 MS/s 1.8 V 123 mW CMOS A/D Converter with 400 MHz Input Bandwidth. IEEE Journal of Solid-State Circuits, 2004, 39(8): 1335-1337
[7] Chouia Y, El-Sankary K, Saleh A, et al. 14 bit 50 MS/s CMOS Front-End Sample and Hold Module Dedicated to a Pipelined ADC. IEEE International Midwest Symposium on Circuits and Systems, 2004, 1: 353-356
[8]兀革.一种模拟开关两步法ADC的CMOS实现研究: [博士学位论文].北京:中科院半导体研究所, 2000.
[9] Behzad Razavi. Principles of Data Conversion System Design. New York: IEEE Press, 1995. 10-15
[10] Alan V Oppenheim, Alan S Willsky, Nawab S Hamid. Signals and Systems.第二版.北京:清华大学出版社, 1998. 55-97
[11] Abraham Peled, Bede Liu. Digital signal processing: theory, design, and implementation. New York: Wiley, 1976. 20-27
[12] Alan V Oppenheim, Ronald W Schafer, John R Buck. Discrete-time Signal Processing. Second Edition. New Jersey: Prentice Hall, 1999. 64-86
[13] Jacsik Lee, Pascal Roux, Koc Ut-Va, et al. A 5 bit 10 GS/s A/D Converter for 10 Gb/s Optical Receivers. IEEE Journal of Solid-State Circuits, 2004, 39(10): 1671-1679
[14] Mehradad Nayebi, Bruce A Wooley. A 10 bit Video BiCMOS Track-and-Hold Amplifier. IEEE Journal of Solid-State Circuits, 1989, 24(6): 1507-1516
[15] Van P Peteghem, Sanaen W. Single versus complementary switches: A discussion of clock feed-through in SC circuits. Europe Solid-State Circuits Conference. Delft, the Netherlands, 1986: 16-18
[16] Miki T, Kouno H, Kumamoto T, Kanoshita Y, Igarashi T, Okada K. A 10 bit 50 MS/s 500 mW A/D converter using a differential-voltage sub-converter. IEEE Journal of Solid-State Circuits, 1994, 29(4): 516-522
[17] Shu T H, Bacrania K, Goanale R. A 10 bit 40 MS/s BiCMOS A/D Converter. IEEE Journal of Solid-State Circuits, 1996, 31(10): 1507-1510
[18] Cho T B, Paul R Gray. A 10 bit 20 MS/s 35 mW pipeline A/D Converter. IEEE Custom Integrated Circuits Conference, 1994, 30(3): 166-172
[19] Larry Singer, Stacy Ho, Mike Timko, et al. A 12 bit 65 MS/s CMOS ADC with 82 dB SFDR at 120 MHz. IEEE Proceedings of 2000 International Solid-State Circuits Conference, 2000: 38-39
[20] Wenhua Yang, Dan Kelly, Iuri Mehr, et al. A 3 V 340 mW 14 bit 75 MS/s CMOS ADC with 85 dB SFDR at Nyquist Input. IEEE JSSCC, 2001, 36(12): 1931-1936
[21] Shinagawa M, Akazawa Y, Wakimoto T. Jitter Analysis of High-Speed Sampling Systems. IEEE Journal of Solid-State Circuits, 1990, 25(1): 220-224
[22] Rudy Plassche. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Second Edition. New York: Kluwer Academic Publishers, 2003. 23-25
[23] Wegmann G, Vittoz E A, Rahali F. Charge injection in analog MOS switch. IEEE Journal of Solid-State Circuits, 1987, 22(6): 1091-1097
[24] Bing Sheu, Je-Hurn Shieh, Patil M. Modeling charge injection in MOS analog switches. IEEE Transactions on Circuits and Systems, 1987, 34(2): 214-216
[25] Wilson W B, Massoud H Z, Swanson E J, et al. Measurement and modeling of charge feed-through in n-channel MOS analog switches. IEEE Journal of Solid-StateCircuits, 1985, 20(6): 1206-1213
[26] Behzad Razavi.模拟CMOS集成电路设计.陈贵灿,程军,张瑞智等译.西安:西安交通大学出版社, 2003. 165-197
[27] Cho T B. Low-Power, Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures: [Ph.D.Dissertation], Berkeley, University of California, 1995.
[28] Mikael Gustavsson, Wikner J Jacob, Nianxiong N Tan. CMOS Data Converters for Communications. New York: Kluwer Academic Publishers, 2002. 125-127
[29] Abo A M, Paul R Gray. A 1.5 V 10 bit 14 MS/s CMOS Pipeline Analog-to-Digital Converter. IEEE Symposium on VLSI Circuits, 1998: 166-169
[30] Paul R Gray, Paul J Hurst. Analysis and Design of Analog Integrated Circuits. Fourth Edition. New York: Wiley, 2004. 462-465
[31] Bult K,Geelen G J G M. A fast-settling CMOS op-amp for SC circuits with 90 dB DC gain. IEEE Journal of Solid-State Circuits, 1990, 25(6): 1379-1384
[32] Chuang C T. Analysis of the Settling Behavior of an Operational Amplifier, IEEE Journal of Solid-State Circuits, 1982, 17(1): 74-80
[33] Schlarmann M E, Geiger R L. Relationship between amplifier settling time and pole-zero placements for second-order systems. IEEE Proceedings of the 43rd Midwest Symposium on Circuits and Systems, 2000, 1: 54-59
[34] Fernando Silveira, Denis Flandre. Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling Time. IEEE Proceedings of the 15th Symposium on Integrated Circuits and Systems Design, 2002: 247-253
[35] Howard C Yang, David J Allstot. Considerations for fast settling operational amplifiers. IEEE Transactions on Circuits and Systems, 1990, 37(3): 326-334
[36] Bernard E Boser, Bruce A Wooley. The Design of Sigma-Delta Modulation Analog- to-Digital Converters. IEEE Journal of Solid-State Circuits, 1988, 23(6): 1298-1308
[37] Malcovati P, Brigati S, Francesconi F, et al. Behavioral modeling of switched capacitor sigma-delta modulators. IEEE transactions on circuits and systems-II, 2004, 50(3): 352-364
[38] Maria del Mar Hershenson, Stephen P Boyd, Thomas H Lee. Optimal Design of aCMOS op-amp via Geometric Programming. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2001, 20(1): 1-21
[39] Pradip Mandal, Visvanathan V. CMOS Op-Amp Sizing Using a Geometric Programming Formulation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2001, 20(1): 22-38
[40] Maria del Mar Hershenson. CMOS analog circuit design via geometric programming. IEEE American Control Conference, 2004, 30(4): 3266-3271
[41] Maria del Mar Hershenson. Design of pipeline analog-to-digital converters via geometric programming. IEEE/ACM International Conference on Computer Aided Design, 2002: 317-324