UHF RFID阅读器中Delta-Sigma Fractional-N频率合成器的研究
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摘要
超高频射频识别(UHF RFID)的巨大市场潜力推动了阅读器(Reader)和标签(Tag)的研究和开发。频率合成器是阅读器中最关键的部分，随着CMOS工艺的不断发展，频率合成器的单片集成已经成为可能。
本文从UHF RFID的协议及频谱规范出发，系统地论述了阅读器中Delta-Sigma Fractional-N频率合成器的理论和实现，并且创新性地研究了频率合成器中的许多关键技术。
首先，根据UHF RFID阅读器中发射机的频谱特性和接收机的链路特征，本文系统地分析了阅读器中频率合成器的设计指标，并通过仿真模型验证了指标的正确性。
第二，基于阅读器的射频参数和频率合成器的设计指标，本文系统地分析了频率合成器的环路参数和噪声特性，保证所设计的环路指标能够满足锁相环频率合成器的噪声要求，在噪声合格前提下，设计出环路中的关键电路指标，包括环路带宽、VCO增益、电荷泵电流、分频比及滤波器参数等。
第三，设计出高Q值的锥形差分电感，从根本上改善VCO的相位噪声特性。锥形差分电感不但提高谐振网络的品质因素，改善相位噪声性能，并且有效地降低了芯片的面积。
第四，提出对称噪声滤波方案，并将其运用到压控振荡器的设计中，有效地解决了N/PMOS互补交叉耦合型(Complement Cross-Couple)VCO中电流源和电源中的噪声混频问题，芯片验证表明该措施效果明显。
第五，基于误差反馈型Delta-Sigma调节器，本文提出系数重配置方案，灵活动态地配置反馈回路中的系数，在环路参数变化时能相应地改变零点位置，增加芯片的可靠性和流片的一次成功率。
第六，提出基于同步补偿的压控振荡器增益线性化方案，解决由于频率调节而引起的增益变化问题，提高了环路的稳定性。
最后，基于频率合成器的设计指标，首次设计出应用于UHF RFID阅读器系统的Delta-Sigma Fractional-N频率合成器，流片测试表明芯片的主要指标都满足阅读器系统的要求，该设计为进一步的研究工作打下坚实的基础。
Driven by the enormous market of UHF RFID, the research and development for Reader and Tag have grows explosively. The frequency synthesizer is the key block in Reader, and it is undoubtedly possible to integrate the frequency synthesizer into a chip with the development of CMOS process.
Based on the protocols and spectrum regulations in UHF RFID, theoretical analysis and implement for Delta-Sigma Fractional-N frequency synthesizer of Reader are described detailedly in this thesis, and many creationary key techniques have been applied into the design of frequency synthesizer.
Firstly, according to spectrum characteristics of transmitter and link parameters of receiver in UHF RFID, the specification of the frequency synthesizer has been analyzed systemically in Reader, and it has been proven correct by the system simulation model.
Secondly, based on the RF parameters of Reader and the specification of the frequency synthesizer, the loop parameters and noise performance have been investigated systemically to guarantee that the loop characteristics can meet the noise requirements in the frequency synthesizer. The key design specifications such as loop bandwidth, VCO gain, Charge-pump current, Divider ratio and filter parameters have been specified on the condition of reasonable noise performance.
Thirdly, the phase noise performance of VCO can be improved by applying the high Q-value taper spiral inductor. The taper spiral inductor can not only increase the Q-value of the resonator, improve the phase noise performance of VCO, but also decrease the die area.
Fourthly, the symmetrical noise filtering technique has been brought forward and applied into the VCO design. It can avoid the noise mixing in tail current and power line in the N/PMOS complement cross-couple VCO. The measurement results show that this technique is useful.
Fifthly, based on the error-feedback Delta-Sigma modulator, this thesis has brought out the technique of coefficient reconfiguring. It can adjust the pole freely when the loop parameters have been changed. It can improve the reliability against process variation and the successful probability for successful taping out.
Sixthly, the technique of gain linearization based on synchronized compensation has been brought out in this thesis to solve the problem of gain variation during frequency adjusting, and this technique can greatly improve the loop stability.
Finally, based on the specification of the frequency synthesizer, a Delta-Sigma Fractional-N frequency synthesizer applied into UHF RFID Reader has been designed for the first time. The measurement results indicate that this design can meet the requirement of the Reader system. This work has made a solid basis for the further research.
本文从UHF RFID的协议及频谱规范出发，系统地论述了阅读器中Delta-Sigma Fractional-N频率合成器的理论和实现，并且创新性地研究了频率合成器中的许多关键技术。
首先，根据UHF RFID阅读器中发射机的频谱特性和接收机的链路特征，本文系统地分析了阅读器中频率合成器的设计指标，并通过仿真模型验证了指标的正确性。
第二，基于阅读器的射频参数和频率合成器的设计指标，本文系统地分析了频率合成器的环路参数和噪声特性，保证所设计的环路指标能够满足锁相环频率合成器的噪声要求，在噪声合格前提下，设计出环路中的关键电路指标，包括环路带宽、VCO增益、电荷泵电流、分频比及滤波器参数等。
第三，设计出高Q值的锥形差分电感，从根本上改善VCO的相位噪声特性。锥形差分电感不但提高谐振网络的品质因素，改善相位噪声性能，并且有效地降低了芯片的面积。
第四，提出对称噪声滤波方案，并将其运用到压控振荡器的设计中，有效地解决了N/PMOS互补交叉耦合型(Complement Cross-Couple)VCO中电流源和电源中的噪声混频问题，芯片验证表明该措施效果明显。
第五，基于误差反馈型Delta-Sigma调节器，本文提出系数重配置方案，灵活动态地配置反馈回路中的系数，在环路参数变化时能相应地改变零点位置，增加芯片的可靠性和流片的一次成功率。
第六，提出基于同步补偿的压控振荡器增益线性化方案，解决由于频率调节而引起的增益变化问题，提高了环路的稳定性。
最后，基于频率合成器的设计指标，首次设计出应用于UHF RFID阅读器系统的Delta-Sigma Fractional-N频率合成器，流片测试表明芯片的主要指标都满足阅读器系统的要求，该设计为进一步的研究工作打下坚实的基础。
Driven by the enormous market of UHF RFID, the research and development for Reader and Tag have grows explosively. The frequency synthesizer is the key block in Reader, and it is undoubtedly possible to integrate the frequency synthesizer into a chip with the development of CMOS process.
Based on the protocols and spectrum regulations in UHF RFID, theoretical analysis and implement for Delta-Sigma Fractional-N frequency synthesizer of Reader are described detailedly in this thesis, and many creationary key techniques have been applied into the design of frequency synthesizer.
Firstly, according to spectrum characteristics of transmitter and link parameters of receiver in UHF RFID, the specification of the frequency synthesizer has been analyzed systemically in Reader, and it has been proven correct by the system simulation model.
Secondly, based on the RF parameters of Reader and the specification of the frequency synthesizer, the loop parameters and noise performance have been investigated systemically to guarantee that the loop characteristics can meet the noise requirements in the frequency synthesizer. The key design specifications such as loop bandwidth, VCO gain, Charge-pump current, Divider ratio and filter parameters have been specified on the condition of reasonable noise performance.
Thirdly, the phase noise performance of VCO can be improved by applying the high Q-value taper spiral inductor. The taper spiral inductor can not only increase the Q-value of the resonator, improve the phase noise performance of VCO, but also decrease the die area.
Fourthly, the symmetrical noise filtering technique has been brought forward and applied into the VCO design. It can avoid the noise mixing in tail current and power line in the N/PMOS complement cross-couple VCO. The measurement results show that this technique is useful.
Fifthly, based on the error-feedback Delta-Sigma modulator, this thesis has brought out the technique of coefficient reconfiguring. It can adjust the pole freely when the loop parameters have been changed. It can improve the reliability against process variation and the successful probability for successful taping out.
Sixthly, the technique of gain linearization based on synchronized compensation has been brought out in this thesis to solve the problem of gain variation during frequency adjusting, and this technique can greatly improve the loop stability.
Finally, based on the specification of the frequency synthesizer, a Delta-Sigma Fractional-N frequency synthesizer applied into UHF RFID Reader has been designed for the first time. The measurement results indicate that this design can meet the requirement of the Reader system. This work has made a solid basis for the further research.
引文
[1] 瑞福智能科技有限公司．RFID(UHF)技术 [EB／OL]．：http://www.raifu.cn/rfid.htm, 2006-3-2.
[2] Bradley J. Bazuin. An In-Depth Review of Radio Frequency Identification [EB/OL].: http://homepages.wmich.edu/~bazuinb/RFID/RFID_FlexoDay2005.pdf 2006-3-2.
[3] 李强．超高频射频电子标签芯片中低功耗电路的研究[D]．上海：复旦大学，2005．
[4] 韩益峰．射频识别阅读器的研究和设计[D]．上海：复旦大学，2005．
[5] Yang Feng-lin, Min Hao. Analysis of the Requirement for Phase Noise in 860-960MHz RFID Reader Systems [J]. Submitted to Journal of Fudan University (Nature Science).
[6] WJ Communications. RFID. [EB/OL].:http://www.wj.com, 2006-3-1.
[7] Udo Karthaus, Martin Fischer. Fully Integrated Passive UHF RFID Transponder IC With 16.7-μW Minimum RF Input Power [J]. IEEE Journal of Solid-State Circuits, 2003, 38(10), 166-175.
[8] V. Beroulle, R. Khouri, T. Vuong, S. Tedjini. Behavioral modeling and simulation of antennas: radio-frequency identification case study [A]. In: IEEE Circuits and Systems Society, Proceedings of the International Workshop on Behavioral Modeling and Simulation [C]. California: IEEE, 2003: 102-106.
[9] Carlo Samori, Salvatore Levantino, and Andrea L. Lacaita. Integrated LC Oscillators for Frequency Synthesis in Wireless Applications [J]. IEEE Communications Magazine, 2002, 40(5), 166-171.
[10] Neric H. W. Fong, Jean Olivier Plouchart et al. Design of Wide-Band CMOS VCO for Multiband Wireless LAN Applications [J]. IEEE Journal of Solid-State Circuits, 2003, 38(8) 1333-1342.
[11] M. Bayer, et al. A low noise CMOS frequency synthesizer with dynamic bandwidth control [A]. In: Custom Integrated Circuits Society, Processings CICC [C]. California: IEEE, 851-852.
[12] B. Y. Zhang, et al. Feed-forward compensated high switching speed digital phase-locked loops [A]. In: Proceedings of ISCAS [C]. Orlando: IEEE: 1999, 371-374.
[13] T. P. Kenny, T. A. D. Riley et al. Design and realization of a digital Δ Σ modulator for fraction-n frequency synthesizer [J]. IEEE Transactions on vehicular technology, 1999, 48(2), 510-521.
[14] S. Willingham, M. Perrott, et al. An integrated 2.5GHz Δ Σ frequency synthesizer with 5μ s setting and 2Mb/s closed loop modulation [A]. In: IEEE International Solid-State Circuits Conference [C]. California: IEEE, 2000.
[15] W. Rhee, B. Song and A. Ali. A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Δ Σ modulator [J]. IEEE J. Solid-State Circuits, 2000, 35(10), 1453-1460.
[16] B. Bisanti, S. Cipriani, et al. Fully integrated sigma-delta synthesizer suitable for indirect vco modulation in 2.5G application [A]. In: IEEE Radio Frequency Integrated Circuits Symposium [C]. Philadelphia: IEEE, 2003, 515-518.
[17] A. M. Fahim, M. I. Elmasry. A wideband sigma-delta phase-locked-loop modulation for wireless application [J]. IEEE Transactions on Circuits and System-Ⅱ: Analog and Digital Signal Processing, 2003, 50(2), 53-61.
[18] S. Pamarti, L. Jansson, et al. A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-MB/s in-loop modulation [J]. IEEE J. Solid-State Circuits, 2004, 39(1), 49-61.
[1] 韩益峰．射频识别阅读器的研究与设计[D]．上海：复旦大学，2005．
[2] U.S. Code of Federal Regulations (CFR), Title 47, Chapter Ⅰ, Part 15: Radio-frequency device [S]. Washington: U. S. Federal Communication Commission, 1999.
[3] ETSI EN 320 208-1, Radio Frequency Identification Equipment operating in the band 865MHz - 868MHz with power levels up to 2W [M]. Cedex: ETSI, 2002.
[4] EPC global EPC Radio-Frequency Identify Protocol Class-1 Generation-2 UHF RFID Protocol for Communication at 860MHz-960MHz, Version 1.0.7 [R]. Massachusetts: Auto-ID Laboratory, 2003.
[5] Jacques C. Rudell, Jeffrey A. Weldon, Jia-Jiunn Ou, Li Lin, and Paul Gray. An Integrated GSM/DECT Receiver: Design Specification [R]. California: UCB Electronics Research Laboratory Memorandum, 1998.
[6] Behzad Razavi. RF Microelectronics [M]. NJ: Prentice Hall, 2000.
[7] 王险峰．TD-SCDMA手机射频前端设计[R]．北京：Maxim技术文档，2005．
[8] 杨丰林，闵昊．Analysis of the Requirement for Phase Noise in 860~960MHz RFID Reader Systems [J]. Shanghai: Submitted to Journal of Fudan University.
[1] KELIU SHU. DESIGN OF A 2.4HHz CMOS MONOLITHIC FRACTIONAL-N FREQUENCY SYNTHESIZER [D]. Texas: Texas A&M University, 2003.
[2] Chun Huat Heng. A 1.8-GHz CMOS Fractional-N Frequency Synthesizer with Randomized Multiphase VCO [D]. Illinois: University of Illinois at Urbana-Champaign, 2003.
[3] 何捷．DVB-T接收机中的频率综合器的研究[D]．上海：复旦大学，2005．
[4] C. Yuen, C. Wong, and K. Tsang. 1μs Fast Acquisition 2.4GHz Low Voltage Frequency Synthesizer for FH-CDMA Mobile Communication [A]. In: Proceedings of the Asia-Pacific Microwave Conference [C]. Hongkong: IEEE, 1997.
[5] Dean Banerjee. PLL Performance, Simulation and Design, Second Edition [R]. California: National Semiconductor, 2001.
[6] Curtis Barrent. Fractional/Integer-N PLL Basics [R]. Texas: Texas Instruments, 1999.
[7] WOOGEUN RHEE. MULTI-BIT DELTA-SIGMA MODULATION TECHNIQUE FOR FRACTIONAL-N FREQUENCY SYNTHESIZERS [D]. Illinois: University of Illinois at Urbana-Champaign, 2001.
[8] 张海清．2.4GHz CMOS全集成调制用△∑分数—N PLL频率合成器研究[D]．上海：复旦大学，2003．
[9] Lee K, Park B. A 3-bit 4th-order ∑ △ modulator with metal-connected multipliers for fractional-n frequency synthesizer [A]. In: IEEE Radio Frequency Integrated Circuits Symposium [C]. Philadelphia: IEEE, 2003, 177-180.
[10] Sudhakar Pamarti, Lars Jansson, and Ian Galton. A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL with 1-MB/s In-Loop Modulation [J]. IEEE Journal of Solid-State Circuits, 2004, 39(1), 49-59.
[11] Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski. Delta-Sigma Modulation in Fractional-N Frequency Synthesis [J]. IEEE Journal of Solid-State Circuits, 1993, 28(5), 553-558.
[12] Rhee W, Song G.. A 1.1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order △ ∑ modulator [J]. IEEE Journal of Solid-State Circuits, 2000, 35(11), 1453-1459.
[13] Benyong Zhang. A 2.4GHz, Low Power, Fully-lntegrated CMOS Frequency Synthesizer for Wireless Communication [D]. Georgia: Georgia Institute of Technology, 2001.
[14] Liang Dai. Design of High-Performance CMOS Voltage-Controlled Oscillator [M]. Boston: Kluwer Academic Publishers, 2003.
[15] Emad Hegazi, Henrik Sjoland, A. A. Abidi. A Filtering Technique to Lower LC Oscillator Phase Noise [J]. IEEE Journal of Solid-State Circuits, 2001, 36(12), 1921-1925.
[16] Ali Hajimiri, Thomas H. Lee. Design Issue in CMOS Differential LC Oscillator [J]. IEEE Journal of Solid-State Circuits, 1999, 34(5), 717-724.
[17] Lance hascari. PLL design/analysis worksheet version 3.8 [EB/OL].: Http://www.rfdude.com, 2005-03-01.
[18] 石浩．低噪声宽带∑△小数频率合成器与新型宽频带、多频带压控振荡器的设计和模拟研究[D]．北京：北京大学，2005。
[1] B. Razavi. RF Microelectronics [M]. NJ: Prentice Hall, 1998.
[2] J. Craninckx and M. Steyaert. Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks [J]. IEEE Trans. Circuits Syst.- Ⅱ, 1995, 42(12):794-803.
[3] Thomas Dellsperger. Design of 5GHz VCO in CMOS [R]. Zurch: Swiss Federal Institute of Technology, 2002.
[4] 张海清．2.4GHz CMOS全集成调制用△∑分数—N PLL频率合成器研究[D]．上海：复旦大学，2003．
[5] 石浩。低噪声宽带∑△小数频率合成器与新型宽频带、多频带压控振荡器的设计和模拟研究[D]．北京：北京大学，2005。
[6] Donhee Ham, A. Hajirimi. Concepts and Methods in Optimization of Integrated LC VCOs [J]. IEEE J. Solid-State Circuits, 2001, 36(6), 896-909.
[7] 唐长文．电感电容压控振荡器[D]．上海：复旦大学，2004．
[8] 褚洪涛．低噪声宽调节范围电感电容压控振荡器设计[D]．上海：上海交通大学，2006．
[9] J. M. Lopez-Vilegas, J. Samitier, C. Cane et al. Improvement of the quality factor of RF integrated inductors by layout optimization [J]. IEEE trans. Microwave theory tech., 2000, 48(1) 76-81.
[10] C. C. Tang, C. H. Wu, S. I. Liu. Miniature 3-D inductors in standard CMOS process [J]. IEEE J. Solid-State Circuits, 2002, 37(4), 471-480.
[11] 菅洪彦．射频集成电路片上电感的分析和优化设计[D]．上海：复旦大学，2005。
[12] J. J. Rael, A. A. Abidi. Physical Processes of Phase Noise in Differential LC Oscillator [A]. In: Proc. of CICC 2000 [C]. Orlando: IEEE, 2000, 569 - 572.
[13] Emad Hegazi, H. Sjoland, A.A. Abidi. A Filtering Technique to Lower LC Oscillator Phase Noise [J]. IEEE J. Solid-State Circuits, 2001, 36(12), 1921-1929.
[14] Pietro Andreani, H. Sjoland. Tail Current Noise Suppression in RF CMOS VCOs [J]. IEEE J. Solid-State Circuits, 2000, 37(3), 342-348.
[15] Anh, Do Manh. Wide-Band/Multi-Band Voltage Controlled Oscillator [P] United States: 6417740, July 9, 2002.
[16] F. Dulger, E. S. Sinencio. Fully-Integrated LC VCOs at RF on Silicon [A]. In: Proc. SSMSD [C]. Texas: IEEE, 2001, 13-18.
[17] Nathan Sneed. A 2-GHz CMOS LC-Tuned VCO using Switch-Capacitors to Compensate for Bond Wire Inductance Variation [D]. California: UCB, 2000.
[18] Yang Fenglin, Min Hao, et al. A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range [J]. Chinese Journal of Semiconductor, 2005, 26(3), 448-452.
[19] F. Svelto, S. Deantoni, R. Castello. A 1.3 GHz Low-Phase Noise Fully Tunable CMOS LC VCO [J]. IEEE J. Solid-State Circuits, 2000,35(3), 356-361.
[20] Young-Mi Lee, Ju-Sang Lee, Ri-A Ju, Kang-Wook Kim, Sang-Dae Yu. A 1.8-V Frequency Synthesizer for WCDMA in O. 18-μm CMOS [A]. In: Proc. MWSCAS [C]. Tulsa, USA: IEEE, 2002, 613-616.
[21] Ahmed H. Mostafa and Monurad. A 12.5 GHz Back-Gated Tuned CMOS Voltage Controlled Oscillator [A]. In: Proc. ICECS [C]. NJ: IEEE, 2000, 243-247.
[22] Pietro Andreani, H. Sjoland. A 2.2GHz CMOS VCO with Inductive Degeneration Noise Suppression [J]. In: Proc. CICC [C]. NJ: IEEE, 2001, 197-200.
[23] F. Svelto, S. Deantoni, R. Castello. A 1.3GHz CMOS VCO with 28% frequency tuning [A]. In: Proc. CICC [C]. NJ: IEEE, 2002, 645-648.
[24] M. Tiebout. A differentially tuned 1.73GHz-1.99GHz Quadrature CMOS VCO for DECT, DCS1800 and GSM900 with a Phase Noise over Tuning Range between - 128dBc/Hz and - 137dBc/Hz at 600KHz Offset [A]. In: Proc. ESSCIRC. NJ: IEEE, 2000.
[25] T. I. Ahrens, T. H. Lee. A 1.4-GHz 3-mW CMOS LC Low Phase Noise VCO Using Tapped Bona Wire Inductances [A]. In: Proc. ACM [C]. Washington: IEEE, 1998, 16-19.
[26] F. Svelto, S. Deantoni, R. Castello. A 1mA, -120.5 dBc/Hz at 600KHz from 1.9GHz fully tuneable LC CMOS VCO [A]. In: Proc. CICC [C]. NJ: IEEE, 2000, 577-580.
[27] J. Bhattacharjee, D. Mukherjee, E. Gebara, S. Nuttinck, J. Laskar. A 5.8GHz Fully Integrated Low Power Low Phase Noise CMOS LC VCO for WLAV Application [A]. In: Proc. RFIC [C]. Seattle: IEEE, 2002, 475-478.
[28] J. H. Chang, Y. S. Youn, Mun-Yang Park, Choong-Ki Kim. A New 6 GHz Fully Integrated Low Power Low Phase Noise CMOS LC Quadrature VCO [A]. In: Proc. RFIC [C]. NJ: IEEE, 2003, 295-298.
[29] Sander L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, V. Boccuzzi. A Low-Phase-Noise 5-GHZ CMOS Quadrature VCO Using Superharmonic Coupling [J]. IEEE J. Solid-Circuits, 2003, 38(7), 1148-1154.
[30] 杨丰林，闵昊．CMOS电感电容压控振荡器中对称噪声滤波技术的研究[J]．微电子学与计算机，已录用，待发表。
[1] Arm M. Fahimo Design and Analysis of Agile Frequency Synthesizer for Mobile Communication [D]. Waterloo: University of Waterloo, 2000.
[2] David A. Johns, Ken Martin. Analog Integrated Circuit Design [M]. Washington: John Wiley & Sons, Inc., 1997.
[3] M. H. Perrott. Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizer [D]. Massachusetts: Massachusetts Institute of Technology, 1997.
[4] KELIU SHU. DESIGN OF A 2.4HHz CMOS MONOLITHIC FRACTIONAL-N FREQUENCY SYNTHESIZER [D]. Texas: Texas A&M University, 2003.
[5] T. A. Riley, M. Copeland, and T. Kwasnieewski. Delta-sigma modulation in fractional-N frequency synthesizer [J]. IEEE J. Solid-State Circuits, 1993, 28(5), 553-559.
[6] L. Wu and W. Black. A low jitter skew -calibrated multi-phase clock generation for time-interleaved applications [A]. In ISSCC Dig. Tech [C]. San Francisco: IEEE, 2001.
[7] Chun Huat Heng. A 1. 8-GHz CMOS Fraction-N Frequency Synthesizer with Randomized Multiphase VCO [D]. Illinois: University of Illinois at Urbana-Champaign, 2003.
[8] L. Sun, T. Lepley, F. Nozalic, et al. Reduced complexity, high performance digital delta-sigma modulator for fraction-N frequency synthesis [A]. In: Proc. ICCAS [C]. Orlando: IEEE, 1999.
[9] T. Musch, I. Rolfes, and B. Schiek. A highly linear frequency ramp generator based on a fractional divider phase-locked loop [J]. IEEE Trans. Instruments Measurements, 1999, 48(1).
[10] Johns D, Martin K. Analog Integrated Circuit Design [M]. NY: Wiley, 1996: 531-573.
[11] Rhee W, Song G.. A 1. 1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order △(?) modulator [J]. IEEE Journal of Solid-State Circuits, 2000, 35(10), 1453-1459.
[12] Rhee. Multi-bit Delta-Sigma Modulation Technique for Fraction-N frequency Synthesizers [D]. Illinois: University of Illinois-Champaign, 2001.
[13] Lee K, Park B. A 3-bit 4~(th)-order(?) △ modulator with metal-connected multipliers for fractional-n frequency synthesizer[A]. In: IEEE Radio Frequency Integrated Circuits Symposium[C]. Philadelphia: IEEE, 2003, 177-180.
[14] R. I. Hartley. Subexpression sharing in filters using canonic signed digit multipliers [J]. IEEE Trans. Circuits and Sys. II,1996, 43(3), 677-688.
[1] Rhee. Multi-bit Delta-Sigma Modulation Technique for Fraction-N frequency Synthesizers [D]. Illinois: University of Illinois-Champaign, 2001.
[2] 何捷．DVB-T接收机中的频率综合器的研究[D]．上海：复旦大学，2005．
[3] 石浩。低噪声宽带∑△小数频率合成器与新型宽频带、多频带压控振荡器的设计和模拟研究[D]．北京：北京大学，2005。
[4] Sudhakar Pamarti, Lars Jansson, fan Galton. A Wideband 2.4-GHz Delta-Sigma Fracional-N PLL With 1-Mb/s In-Loop Modulation [J]. IEEE Journal of Solid-State Circuits, 2004, 39(1), 49-62.
[5] Keliu Shu, Edgar Sanchez-Sinencio. CMOS PLL Synthesizer: Analysis and Design [M]. Boston: Springer, 2005.
[6] W. Rhee. Design of high performance CMOS charge pumps in phase locked loop [A]. In: Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) [C]. Orlando: IEEE, 1999, 545-548.
[7] J. G. Maneatis. Low-jitter and process-independent DLL and PLL based on self-biased techniques [J]. IEEE, Journal of Solid-State Circuits, 1996, 31(11), 1723-1730.
[8] 李骅．应用于无线通讯系统的高速分频器的研究[D]．上海：复旦大学，2005．
[9] Muhammad Usama, Tad Kwasniewski. New CML Latch Structure for High Speed Prescaler Design [R]. Ontario: Department of electronics, Carleton University.
[10] Jan Craninckx, and Michel S. J. Steyaert. A Fully Integrated CMOS DCS-1800 Frequency Synthesizer [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33(12), 1915-1918.
[11] Ullas Singh, Michael Green. Dynamics of High-freqnency CMOS Dividers [R]. California: University of California Irvine, 2002.
[1] J.J. Rael, A.A. Abidi. Physical Processes of Phase Noise in Differential LC Oscillator [A]. In: Proc. of CICC [C]. Orlando: IEEE, 2000, 569 - 572.
[2] T. P. Kenny, T. A. D. Riley et al. Design and realization of a digital Δ Σ modulator for fraction-n frequency synthesizer [J]. IEEE Transactions on vehicular technology, 1999, 48(2), 510-521.
[3] S. Willingham, M. Perrott, et al. An integrated 2.5GHz Δ Σ frequency synthesizer with 5μs setting and 2Mb/s closed loop modulation [A]. In: IEEE International Solid-State Circuits Conference [C]. California: IEEE, 2000.
[4] W. Rhee, B. Song and A. Ali. A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Δ Σ modulator [J]. IEEE J. Solid-State Circuits, 2000, 35(10), 1453-1460.
[5] B. Bisanti, S. Cipriani, et al. Fully integrated sigma-delta synthesizer suitable for indirect vco modulation in 2.5G application [A]. In: IEEE Radio Frequency Integrated Circuits Symposium [C]. Philadelphia: IEEE, 2003, 515-518.
[6] A. M. Fahim, M. I. Elmasry. A wideband sigma-delta phase-locked-loop modulation for wireless application [J]. IEEE Transactions on Circuits and System-Ⅱ: Analog and Digital Signal Processing, 2003, 50(2), 53-61.
[7] S. Pamarti, L. Jansson, et al. A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-MB/s in-loop modulation [J]. IEEE J. Solid-State Circuits, 2004, 39(1), 49-61.
[2] Bradley J. Bazuin. An In-Depth Review of Radio Frequency Identification [EB/OL].: http://homepages.wmich.edu/~bazuinb/RFID/RFID_FlexoDay2005.pdf 2006-3-2.
[3] 李强．超高频射频电子标签芯片中低功耗电路的研究[D]．上海：复旦大学，2005．
[4] 韩益峰．射频识别阅读器的研究和设计[D]．上海：复旦大学，2005．
[5] Yang Feng-lin, Min Hao. Analysis of the Requirement for Phase Noise in 860-960MHz RFID Reader Systems [J]. Submitted to Journal of Fudan University (Nature Science).
[6] WJ Communications. RFID. [EB/OL].:http://www.wj.com, 2006-3-1.
[7] Udo Karthaus, Martin Fischer. Fully Integrated Passive UHF RFID Transponder IC With 16.7-μW Minimum RF Input Power [J]. IEEE Journal of Solid-State Circuits, 2003, 38(10), 166-175.
[8] V. Beroulle, R. Khouri, T. Vuong, S. Tedjini. Behavioral modeling and simulation of antennas: radio-frequency identification case study [A]. In: IEEE Circuits and Systems Society, Proceedings of the International Workshop on Behavioral Modeling and Simulation [C]. California: IEEE, 2003: 102-106.
[9] Carlo Samori, Salvatore Levantino, and Andrea L. Lacaita. Integrated LC Oscillators for Frequency Synthesis in Wireless Applications [J]. IEEE Communications Magazine, 2002, 40(5), 166-171.
[10] Neric H. W. Fong, Jean Olivier Plouchart et al. Design of Wide-Band CMOS VCO for Multiband Wireless LAN Applications [J]. IEEE Journal of Solid-State Circuits, 2003, 38(8) 1333-1342.
[11] M. Bayer, et al. A low noise CMOS frequency synthesizer with dynamic bandwidth control [A]. In: Custom Integrated Circuits Society, Processings CICC [C]. California: IEEE, 851-852.
[12] B. Y. Zhang, et al. Feed-forward compensated high switching speed digital phase-locked loops [A]. In: Proceedings of ISCAS [C]. Orlando: IEEE: 1999, 371-374.
[13] T. P. Kenny, T. A. D. Riley et al. Design and realization of a digital Δ Σ modulator for fraction-n frequency synthesizer [J]. IEEE Transactions on vehicular technology, 1999, 48(2), 510-521.
[14] S. Willingham, M. Perrott, et al. An integrated 2.5GHz Δ Σ frequency synthesizer with 5μ s setting and 2Mb/s closed loop modulation [A]. In: IEEE International Solid-State Circuits Conference [C]. California: IEEE, 2000.
[15] W. Rhee, B. Song and A. Ali. A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Δ Σ modulator [J]. IEEE J. Solid-State Circuits, 2000, 35(10), 1453-1460.
[16] B. Bisanti, S. Cipriani, et al. Fully integrated sigma-delta synthesizer suitable for indirect vco modulation in 2.5G application [A]. In: IEEE Radio Frequency Integrated Circuits Symposium [C]. Philadelphia: IEEE, 2003, 515-518.
[17] A. M. Fahim, M. I. Elmasry. A wideband sigma-delta phase-locked-loop modulation for wireless application [J]. IEEE Transactions on Circuits and System-Ⅱ: Analog and Digital Signal Processing, 2003, 50(2), 53-61.
[18] S. Pamarti, L. Jansson, et al. A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-MB/s in-loop modulation [J]. IEEE J. Solid-State Circuits, 2004, 39(1), 49-61.
[1] 韩益峰．射频识别阅读器的研究与设计[D]．上海：复旦大学，2005．
[2] U.S. Code of Federal Regulations (CFR), Title 47, Chapter Ⅰ, Part 15: Radio-frequency device [S]. Washington: U. S. Federal Communication Commission, 1999.
[3] ETSI EN 320 208-1, Radio Frequency Identification Equipment operating in the band 865MHz - 868MHz with power levels up to 2W [M]. Cedex: ETSI, 2002.
[4] EPC global EPC Radio-Frequency Identify Protocol Class-1 Generation-2 UHF RFID Protocol for Communication at 860MHz-960MHz, Version 1.0.7 [R]. Massachusetts: Auto-ID Laboratory, 2003.
[5] Jacques C. Rudell, Jeffrey A. Weldon, Jia-Jiunn Ou, Li Lin, and Paul Gray. An Integrated GSM/DECT Receiver: Design Specification [R]. California: UCB Electronics Research Laboratory Memorandum, 1998.
[6] Behzad Razavi. RF Microelectronics [M]. NJ: Prentice Hall, 2000.
[7] 王险峰．TD-SCDMA手机射频前端设计[R]．北京：Maxim技术文档，2005．
[8] 杨丰林，闵昊．Analysis of the Requirement for Phase Noise in 860~960MHz RFID Reader Systems [J]. Shanghai: Submitted to Journal of Fudan University.
[1] KELIU SHU. DESIGN OF A 2.4HHz CMOS MONOLITHIC FRACTIONAL-N FREQUENCY SYNTHESIZER [D]. Texas: Texas A&M University, 2003.
[2] Chun Huat Heng. A 1.8-GHz CMOS Fractional-N Frequency Synthesizer with Randomized Multiphase VCO [D]. Illinois: University of Illinois at Urbana-Champaign, 2003.
[3] 何捷．DVB-T接收机中的频率综合器的研究[D]．上海：复旦大学，2005．
[4] C. Yuen, C. Wong, and K. Tsang. 1μs Fast Acquisition 2.4GHz Low Voltage Frequency Synthesizer for FH-CDMA Mobile Communication [A]. In: Proceedings of the Asia-Pacific Microwave Conference [C]. Hongkong: IEEE, 1997.
[5] Dean Banerjee. PLL Performance, Simulation and Design, Second Edition [R]. California: National Semiconductor, 2001.
[6] Curtis Barrent. Fractional/Integer-N PLL Basics [R]. Texas: Texas Instruments, 1999.
[7] WOOGEUN RHEE. MULTI-BIT DELTA-SIGMA MODULATION TECHNIQUE FOR FRACTIONAL-N FREQUENCY SYNTHESIZERS [D]. Illinois: University of Illinois at Urbana-Champaign, 2001.
[8] 张海清．2.4GHz CMOS全集成调制用△∑分数—N PLL频率合成器研究[D]．上海：复旦大学，2003．
[9] Lee K, Park B. A 3-bit 4th-order ∑ △ modulator with metal-connected multipliers for fractional-n frequency synthesizer [A]. In: IEEE Radio Frequency Integrated Circuits Symposium [C]. Philadelphia: IEEE, 2003, 177-180.
[10] Sudhakar Pamarti, Lars Jansson, and Ian Galton. A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL with 1-MB/s In-Loop Modulation [J]. IEEE Journal of Solid-State Circuits, 2004, 39(1), 49-59.
[11] Tom A. D. Riley, Miles A. Copeland, Tad A. Kwasniewski. Delta-Sigma Modulation in Fractional-N Frequency Synthesis [J]. IEEE Journal of Solid-State Circuits, 1993, 28(5), 553-558.
[12] Rhee W, Song G.. A 1.1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order △ ∑ modulator [J]. IEEE Journal of Solid-State Circuits, 2000, 35(11), 1453-1459.
[13] Benyong Zhang. A 2.4GHz, Low Power, Fully-lntegrated CMOS Frequency Synthesizer for Wireless Communication [D]. Georgia: Georgia Institute of Technology, 2001.
[14] Liang Dai. Design of High-Performance CMOS Voltage-Controlled Oscillator [M]. Boston: Kluwer Academic Publishers, 2003.
[15] Emad Hegazi, Henrik Sjoland, A. A. Abidi. A Filtering Technique to Lower LC Oscillator Phase Noise [J]. IEEE Journal of Solid-State Circuits, 2001, 36(12), 1921-1925.
[16] Ali Hajimiri, Thomas H. Lee. Design Issue in CMOS Differential LC Oscillator [J]. IEEE Journal of Solid-State Circuits, 1999, 34(5), 717-724.
[17] Lance hascari. PLL design/analysis worksheet version 3.8 [EB/OL].: Http://www.rfdude.com, 2005-03-01.
[18] 石浩．低噪声宽带∑△小数频率合成器与新型宽频带、多频带压控振荡器的设计和模拟研究[D]．北京：北京大学，2005。
[1] B. Razavi. RF Microelectronics [M]. NJ: Prentice Hall, 1998.
[2] J. Craninckx and M. Steyaert. Low-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks [J]. IEEE Trans. Circuits Syst.- Ⅱ, 1995, 42(12):794-803.
[3] Thomas Dellsperger. Design of 5GHz VCO in CMOS [R]. Zurch: Swiss Federal Institute of Technology, 2002.
[4] 张海清．2.4GHz CMOS全集成调制用△∑分数—N PLL频率合成器研究[D]．上海：复旦大学，2003．
[5] 石浩。低噪声宽带∑△小数频率合成器与新型宽频带、多频带压控振荡器的设计和模拟研究[D]．北京：北京大学，2005。
[6] Donhee Ham, A. Hajirimi. Concepts and Methods in Optimization of Integrated LC VCOs [J]. IEEE J. Solid-State Circuits, 2001, 36(6), 896-909.
[7] 唐长文．电感电容压控振荡器[D]．上海：复旦大学，2004．
[8] 褚洪涛．低噪声宽调节范围电感电容压控振荡器设计[D]．上海：上海交通大学，2006．
[9] J. M. Lopez-Vilegas, J. Samitier, C. Cane et al. Improvement of the quality factor of RF integrated inductors by layout optimization [J]. IEEE trans. Microwave theory tech., 2000, 48(1) 76-81.
[10] C. C. Tang, C. H. Wu, S. I. Liu. Miniature 3-D inductors in standard CMOS process [J]. IEEE J. Solid-State Circuits, 2002, 37(4), 471-480.
[11] 菅洪彦．射频集成电路片上电感的分析和优化设计[D]．上海：复旦大学，2005。
[12] J. J. Rael, A. A. Abidi. Physical Processes of Phase Noise in Differential LC Oscillator [A]. In: Proc. of CICC 2000 [C]. Orlando: IEEE, 2000, 569 - 572.
[13] Emad Hegazi, H. Sjoland, A.A. Abidi. A Filtering Technique to Lower LC Oscillator Phase Noise [J]. IEEE J. Solid-State Circuits, 2001, 36(12), 1921-1929.
[14] Pietro Andreani, H. Sjoland. Tail Current Noise Suppression in RF CMOS VCOs [J]. IEEE J. Solid-State Circuits, 2000, 37(3), 342-348.
[15] Anh, Do Manh. Wide-Band/Multi-Band Voltage Controlled Oscillator [P] United States: 6417740, July 9, 2002.
[16] F. Dulger, E. S. Sinencio. Fully-Integrated LC VCOs at RF on Silicon [A]. In: Proc. SSMSD [C]. Texas: IEEE, 2001, 13-18.
[17] Nathan Sneed. A 2-GHz CMOS LC-Tuned VCO using Switch-Capacitors to Compensate for Bond Wire Inductance Variation [D]. California: UCB, 2000.
[18] Yang Fenglin, Min Hao, et al. A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range [J]. Chinese Journal of Semiconductor, 2005, 26(3), 448-452.
[19] F. Svelto, S. Deantoni, R. Castello. A 1.3 GHz Low-Phase Noise Fully Tunable CMOS LC VCO [J]. IEEE J. Solid-State Circuits, 2000,35(3), 356-361.
[20] Young-Mi Lee, Ju-Sang Lee, Ri-A Ju, Kang-Wook Kim, Sang-Dae Yu. A 1.8-V Frequency Synthesizer for WCDMA in O. 18-μm CMOS [A]. In: Proc. MWSCAS [C]. Tulsa, USA: IEEE, 2002, 613-616.
[21] Ahmed H. Mostafa and Monurad. A 12.5 GHz Back-Gated Tuned CMOS Voltage Controlled Oscillator [A]. In: Proc. ICECS [C]. NJ: IEEE, 2000, 243-247.
[22] Pietro Andreani, H. Sjoland. A 2.2GHz CMOS VCO with Inductive Degeneration Noise Suppression [J]. In: Proc. CICC [C]. NJ: IEEE, 2001, 197-200.
[23] F. Svelto, S. Deantoni, R. Castello. A 1.3GHz CMOS VCO with 28% frequency tuning [A]. In: Proc. CICC [C]. NJ: IEEE, 2002, 645-648.
[24] M. Tiebout. A differentially tuned 1.73GHz-1.99GHz Quadrature CMOS VCO for DECT, DCS1800 and GSM900 with a Phase Noise over Tuning Range between - 128dBc/Hz and - 137dBc/Hz at 600KHz Offset [A]. In: Proc. ESSCIRC. NJ: IEEE, 2000.
[25] T. I. Ahrens, T. H. Lee. A 1.4-GHz 3-mW CMOS LC Low Phase Noise VCO Using Tapped Bona Wire Inductances [A]. In: Proc. ACM [C]. Washington: IEEE, 1998, 16-19.
[26] F. Svelto, S. Deantoni, R. Castello. A 1mA, -120.5 dBc/Hz at 600KHz from 1.9GHz fully tuneable LC CMOS VCO [A]. In: Proc. CICC [C]. NJ: IEEE, 2000, 577-580.
[27] J. Bhattacharjee, D. Mukherjee, E. Gebara, S. Nuttinck, J. Laskar. A 5.8GHz Fully Integrated Low Power Low Phase Noise CMOS LC VCO for WLAV Application [A]. In: Proc. RFIC [C]. Seattle: IEEE, 2002, 475-478.
[28] J. H. Chang, Y. S. Youn, Mun-Yang Park, Choong-Ki Kim. A New 6 GHz Fully Integrated Low Power Low Phase Noise CMOS LC Quadrature VCO [A]. In: Proc. RFIC [C]. NJ: IEEE, 2003, 295-298.
[29] Sander L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, V. Boccuzzi. A Low-Phase-Noise 5-GHZ CMOS Quadrature VCO Using Superharmonic Coupling [J]. IEEE J. Solid-Circuits, 2003, 38(7), 1148-1154.
[30] 杨丰林，闵昊．CMOS电感电容压控振荡器中对称噪声滤波技术的研究[J]．微电子学与计算机，已录用，待发表。
[1] Arm M. Fahimo Design and Analysis of Agile Frequency Synthesizer for Mobile Communication [D]. Waterloo: University of Waterloo, 2000.
[2] David A. Johns, Ken Martin. Analog Integrated Circuit Design [M]. Washington: John Wiley & Sons, Inc., 1997.
[3] M. H. Perrott. Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizer [D]. Massachusetts: Massachusetts Institute of Technology, 1997.
[4] KELIU SHU. DESIGN OF A 2.4HHz CMOS MONOLITHIC FRACTIONAL-N FREQUENCY SYNTHESIZER [D]. Texas: Texas A&M University, 2003.
[5] T. A. Riley, M. Copeland, and T. Kwasnieewski. Delta-sigma modulation in fractional-N frequency synthesizer [J]. IEEE J. Solid-State Circuits, 1993, 28(5), 553-559.
[6] L. Wu and W. Black. A low jitter skew -calibrated multi-phase clock generation for time-interleaved applications [A]. In ISSCC Dig. Tech [C]. San Francisco: IEEE, 2001.
[7] Chun Huat Heng. A 1. 8-GHz CMOS Fraction-N Frequency Synthesizer with Randomized Multiphase VCO [D]. Illinois: University of Illinois at Urbana-Champaign, 2003.
[8] L. Sun, T. Lepley, F. Nozalic, et al. Reduced complexity, high performance digital delta-sigma modulator for fraction-N frequency synthesis [A]. In: Proc. ICCAS [C]. Orlando: IEEE, 1999.
[9] T. Musch, I. Rolfes, and B. Schiek. A highly linear frequency ramp generator based on a fractional divider phase-locked loop [J]. IEEE Trans. Instruments Measurements, 1999, 48(1).
[10] Johns D, Martin K. Analog Integrated Circuit Design [M]. NY: Wiley, 1996: 531-573.
[11] Rhee W, Song G.. A 1. 1-GHz CMOS fractional-n frequency synthesizer with a 3-b third-order △(?) modulator [J]. IEEE Journal of Solid-State Circuits, 2000, 35(10), 1453-1459.
[12] Rhee. Multi-bit Delta-Sigma Modulation Technique for Fraction-N frequency Synthesizers [D]. Illinois: University of Illinois-Champaign, 2001.
[13] Lee K, Park B. A 3-bit 4~(th)-order(?) △ modulator with metal-connected multipliers for fractional-n frequency synthesizer[A]. In: IEEE Radio Frequency Integrated Circuits Symposium[C]. Philadelphia: IEEE, 2003, 177-180.
[14] R. I. Hartley. Subexpression sharing in filters using canonic signed digit multipliers [J]. IEEE Trans. Circuits and Sys. II,1996, 43(3), 677-688.
[1] Rhee. Multi-bit Delta-Sigma Modulation Technique for Fraction-N frequency Synthesizers [D]. Illinois: University of Illinois-Champaign, 2001.
[2] 何捷．DVB-T接收机中的频率综合器的研究[D]．上海：复旦大学，2005．
[3] 石浩。低噪声宽带∑△小数频率合成器与新型宽频带、多频带压控振荡器的设计和模拟研究[D]．北京：北京大学，2005。
[4] Sudhakar Pamarti, Lars Jansson, fan Galton. A Wideband 2.4-GHz Delta-Sigma Fracional-N PLL With 1-Mb/s In-Loop Modulation [J]. IEEE Journal of Solid-State Circuits, 2004, 39(1), 49-62.
[5] Keliu Shu, Edgar Sanchez-Sinencio. CMOS PLL Synthesizer: Analysis and Design [M]. Boston: Springer, 2005.
[6] W. Rhee. Design of high performance CMOS charge pumps in phase locked loop [A]. In: Proc. IEEE Int. Symp. Circuits and Systems (ISCAS) [C]. Orlando: IEEE, 1999, 545-548.
[7] J. G. Maneatis. Low-jitter and process-independent DLL and PLL based on self-biased techniques [J]. IEEE, Journal of Solid-State Circuits, 1996, 31(11), 1723-1730.
[8] 李骅．应用于无线通讯系统的高速分频器的研究[D]．上海：复旦大学，2005．
[9] Muhammad Usama, Tad Kwasniewski. New CML Latch Structure for High Speed Prescaler Design [R]. Ontario: Department of electronics, Carleton University.
[10] Jan Craninckx, and Michel S. J. Steyaert. A Fully Integrated CMOS DCS-1800 Frequency Synthesizer [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33(12), 1915-1918.
[11] Ullas Singh, Michael Green. Dynamics of High-freqnency CMOS Dividers [R]. California: University of California Irvine, 2002.
[1] J.J. Rael, A.A. Abidi. Physical Processes of Phase Noise in Differential LC Oscillator [A]. In: Proc. of CICC [C]. Orlando: IEEE, 2000, 569 - 572.
[2] T. P. Kenny, T. A. D. Riley et al. Design and realization of a digital Δ Σ modulator for fraction-n frequency synthesizer [J]. IEEE Transactions on vehicular technology, 1999, 48(2), 510-521.
[3] S. Willingham, M. Perrott, et al. An integrated 2.5GHz Δ Σ frequency synthesizer with 5μs setting and 2Mb/s closed loop modulation [A]. In: IEEE International Solid-State Circuits Conference [C]. California: IEEE, 2000.
[4] W. Rhee, B. Song and A. Ali. A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Δ Σ modulator [J]. IEEE J. Solid-State Circuits, 2000, 35(10), 1453-1460.
[5] B. Bisanti, S. Cipriani, et al. Fully integrated sigma-delta synthesizer suitable for indirect vco modulation in 2.5G application [A]. In: IEEE Radio Frequency Integrated Circuits Symposium [C]. Philadelphia: IEEE, 2003, 515-518.
[6] A. M. Fahim, M. I. Elmasry. A wideband sigma-delta phase-locked-loop modulation for wireless application [J]. IEEE Transactions on Circuits and System-Ⅱ: Analog and Digital Signal Processing, 2003, 50(2), 53-61.
[7] S. Pamarti, L. Jansson, et al. A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-MB/s in-loop modulation [J]. IEEE J. Solid-State Circuits, 2004, 39(1), 49-61.
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