基于精度的12位逐次逼近型ADC的研究与设计
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摘要
本文设计的是12位逐次逼近型ADC(Analog to Digital Converter)，主要包括采样/保持电路、比较器、DAC(Digital to Analog Converter)模块以及带隙基准电流源。采样/保持电路采用的是CMOS开关，比单沟道MOS开关有更大的导通状态动态范围。其中的单位增益运放采用的是rail-to-rail差分输入结构，实现了输入共模范围从0到Vdd的轨到轨输入，电流补偿技术使得输入跨导恒定，从而减小了频率补偿的难度使得相位裕度达到了78°，Class AB的输出方式使得运放在保持高效率输出的情况下减小了信号失真，同时折叠式共源共栅负载和两级放大的结构使运放能够达到90dB的高增益。比较器的输入和负载部分同运放一样，不同的是输出采用的是推挽输出，该结构能够保证在不牺牲速度的情况下，提高其驱动大容性负载的能力。DAC模块采用的是串行电阻电压按比例缩放结构，由相同类型DAC缩放组合分别处理高、低六位有效字，使得该模块的面积尺寸缩小很多。带隙基准电流源的基准电压随温度变化的幅度很小，温度曲线表明三种模型下总的温度系数为46.67 ppm/℃。
整个电路的仿真采用的是0.25 CMOS工艺，电源电压为3.3Vμm。仿真软件采用的是Synopsys公司的Hspice-2005。仿真结果表明，设计的ADC分辨率在允许的共模范围中间电平能够达到12位，功耗为6.6mW，积分非线性INL和微分非线性DNL均超过了1LSB，在性能方面需要提高。
This paper presents the design of a 12bit successive approximation (SAR) ADCmainly including sample/hold circuit, comparator, digital logic control, DAC module andbandgap reference current circuit. The sample/hold circuit adopted CMOS switches toincrease its dynamic area comparing with single channel switch in induced condition. Theunity-gain amplifier in the sample/hold circuit adopted rail-to-rail differential inputarchitecture to improve the common input range from 0 to Vdd to realize full scaleinput.Current compensation ensured input transconductance gm constant to easyfrequency compensation making the phase margin reach 78°.Its Class AB output wayweakened the signal distortion with high output efficiency. Besides, two level amplifieringstage and folded cascode architecture maintained high gain to reach 90dB.As for thecomparator, input and load parts are the same with the unity-gain amplifier. The differencebetween them was that comparator adopted push pull output way to improve its ability ofdriving large capacitance load. DAC module adopted voltage scaling architecture of seriesconnecting resistors to process high six MSB and low six LSB respectively, which larglydecrease the module size.Temperature coefficient of bandgap reached 46.67 ppm/℃.
The whole circuit system was simulated on 0.25μm CMOS process, power supply is3.3V. The simulating software was Synopsys Company’s Hspice-2005. The simulationresult shows that the designing ADC sensitivity is 12bits, power consumption is 6.6mW,INL and DNL exceeds 1LSB which indicates the performance needs to be improved.
整个电路的仿真采用的是0.25 CMOS工艺，电源电压为3.3Vμm。仿真软件采用的是Synopsys公司的Hspice-2005。仿真结果表明，设计的ADC分辨率在允许的共模范围中间电平能够达到12位，功耗为6.6mW，积分非线性INL和微分非线性DNL均超过了1LSB，在性能方面需要提高。
This paper presents the design of a 12bit successive approximation (SAR) ADCmainly including sample/hold circuit, comparator, digital logic control, DAC module andbandgap reference current circuit. The sample/hold circuit adopted CMOS switches toincrease its dynamic area comparing with single channel switch in induced condition. Theunity-gain amplifier in the sample/hold circuit adopted rail-to-rail differential inputarchitecture to improve the common input range from 0 to Vdd to realize full scaleinput.Current compensation ensured input transconductance gm constant to easyfrequency compensation making the phase margin reach 78°.Its Class AB output wayweakened the signal distortion with high output efficiency. Besides, two level amplifieringstage and folded cascode architecture maintained high gain to reach 90dB.As for thecomparator, input and load parts are the same with the unity-gain amplifier. The differencebetween them was that comparator adopted push pull output way to improve its ability ofdriving large capacitance load. DAC module adopted voltage scaling architecture of seriesconnecting resistors to process high six MSB and low six LSB respectively, which larglydecrease the module size.Temperature coefficient of bandgap reached 46.67 ppm/℃.
The whole circuit system was simulated on 0.25μm CMOS process, power supply is3.3V. The simulating software was Synopsys Company’s Hspice-2005. The simulationresult shows that the designing ADC sensitivity is 12bits, power consumption is 6.6mW,INL and DNL exceeds 1LSB which indicates the performance needs to be improved.
引文
[1]宁宁.10 bits 100MSpS pipelined ADC系统结构优化及部分单元设计.电子科技电子科技大学硕士学位论文，2005年1月
[2]何遐龄.高速采样ADC.微电子学，1998，28(4):218~219
[3]江孝国.高精度AD转换器应用中的误差分析.电子测量技术，1997，3:23~25
[4] CLINE D W, GARY P R. A Power Optimized 13-b5Msample/s Pipelined ADC in1.2μm CMOS .IEEE J Sol Sta Circ, 1996, 31(3):294-303
[5] R.E.Suarez, P.R.Gray, D.A.Hodges. An All-MOS Charge-Redistribution ADConversion Technique. ISSCC Dig Tech. Papers, New York: ISSCC.1974
[6]王晓艳.12位逐次逼近型ADC的研究与设计.西北大学硕士学位论文.2007年5月
[7]曹志刚,钱亚生.现代通信原理.清华大学出版社.1992年8月:25-30
[8] Hwang-cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, etc. A1.8V, 0.3mW, 10bitSAR ADC with New Self-timed Timing Control for Biomedical Applications.Circuits and System, 2005.ISCA2005.IEEE International Symposium on 23-26 May2005, Vol. l: 736-739
[9] Bahzad Razavi. Principle of Data Conversion System Design. IEEE press,1995:20
[10] J. Candy, G. Temes. Oversampling Delta-Sigma Data Converters. New York: IEEEPress, 1997
[11] Kevin J. McCall, Michael J.Demler, Michael W.Plante, A 6-bit 125MHz CMOSADC, IEEE 1992 Custom Integrated Circuits Conference, May 1992:16.8.1-16.8.4
[12] Q.Wu, A.Wang. A 12 bits/200MHz resolution/sampling/power-optimized ADC in0.25 SiGe BICMOS. IEEE International Symposium on Circuits and Systems.2005.vol.6:6174~6177
[13] Samiran Haier,et. A 160MSPS 8-bit pipeline based ADC.18th InternationalConference on VLSI Design.2005:313~318
[14] Carlos A. Vega de laCruz，A Switched Opamp Comparator to Improve theConversion Rate of Low-Power Low-Voltage Successive Approximation ADCs.University of Puerto Rico Mayguez Campus doctor’s Thesis 2005
[15] D. johns, K. Martin. Analog Integrated Circuit. John Wiley & Sons, INC. Chap.11-13,1997
[16] M. Steyaert, R. Roovers, J. Craninckx. A 100MHz 8-bit CMOS Interpolating ADC.IEEE Custom Integrated Circuits Conference, San Diego. May 1993:28.1.1-28.1.4
[17] M.P.Flynn, D.J.Allstot. CMOS Folding ADCs with Current-Mode Interpolation.IEEE J. of Solid State Circuits, vol.31, No.9:1248-57, Sept.1996
[18] S. H. Lewis. Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converter for Video-Rate Applications. IEEE Trans. On Circuit and System-11, vol. 39, no. 8:516-23, Aug.1992
[19] Rudy Van De Plassche. Integrated Analog to Digital and Digital to AnalogConverters. Kluwer Academic Publishers，1994
[20] B.E Boser, B. A. Wooley. The Design of Sigma-Delta Modulation Analog to DigitalConverters. IEEE J. Solid State Circuits, Vol.SC-23, pp, 1298~1308, Dec.1988
[21] Steven R. Norsworthy, Richard Schreier, Gabor C.Temes. Delta–Sigma DataConverters Theory Design and Simulation. Institute of Electrical and ElectronicsEngineers, Inc. 1997
[22]刘军.12位流水线ADC的研究与实现.暨南大学硕士学位论：2005年
[23]彭新芒，杨银堂，朱樟明等.一种8通道12位逐次逼近式ADC的设计.电子工程师，2007，33(4):54-56
[24] Phillip E Allen, Douglas R Holberg. CMOS模拟集成电路设计.第二版.冯军，李智群译.北京:电子工业出版社,2005:546
[25]包闻亮,鲍风编著.信号和通信系统.复旦大学出版社,1991:5~6
[26] D.J.Allstot. A Precision Variable-Supply CMOS Comparator. IEEE J.Solid StateCircuit,Vol.SC-17,No.6:1080-1087,Dec.1982
[27]康华光,陈大钦.模拟电子技术基础,第四版.北京:高等教育出版社.2003:205-207
[28] Hogervorst R, Tero J P, Eschauzier R G H, et. A compact power efficient 3V CMOSrail-to-rail input/output operational amplifier for VLSI cell libraries. IEEE J So l StaCirc, 1994; 29 (12): 150521512
[29] Huijsing J H, Linebarger D. Low-voltage operational amplifier with rail-to-rail inputand output ranges. IEEE J. Solid State Circuit, 1985,SC-20:1144~1150
[30] R.Hogervorst et. CMOS Low-Voltage Operational Amplifiers with Constant gmRail-to-Rail Input Stage. Analog Integrated Circuits and SignalProcessing,Vol.5,No.4:135-146,Mar.1994
[31] J.H. Botma et. Rail-to-Rail Constant-Gm Input Stage and Class AB Output Stage forLow-Voltage CMOS Opamps. Analog Integrated Circuits and SignalProcessing,Vol.6,No.2,pp.121-133,Sept.1994
[32]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿，程军，张瑞智等译.西安:西安交通大学出版社, 2003: 248
[33]张强,李攀,田泽,陈贵灿,刘宁.高性能Rail to Rail恒定跨导CMOS运算放大器.微电子学与计算机，Vol . 25 No. 3 March 2008
[34]杨秀丽.基于CMOS工艺的10位SAR ADC的研究与设计.合肥工业大学硕士学位论文，2007年5月
[35]张亮.10位逐次逼近型模数转换器的设计.沈阳工业大学硕士学位论文，2006年3月
[36]王晗,叶青.0.6V电源电压的CMOS基准源设计及稳定性分析.半导体学报Vol .27 No. 8 Aug., 2006
[37]朱磊,杨银堂,朱樟明,付永朝.低压CMOS带隙电压基准源设计,固体电子学研究与进展.Vol . 25, No.2 May, 2005
[38]陈浩琼,高清运,秦世才.CMOS带隙电压基准的误差及其改进.固体电子学研究与进展,Vol .25, No. 4 Nov., 2005
[39] Chester Simpson.美国国家半导体公司应用注释1148,2000年5月
[40] Paulr.Gray, Paul J. Hurst Stephen H. Lewis. Analysis and Design of AnalogIntegrated Circuits. BEUNIG: Higher Education Press,2005:523-576
[2]何遐龄.高速采样ADC.微电子学，1998，28(4):218~219
[3]江孝国.高精度AD转换器应用中的误差分析.电子测量技术，1997，3:23~25
[4] CLINE D W, GARY P R. A Power Optimized 13-b5Msample/s Pipelined ADC in1.2μm CMOS .IEEE J Sol Sta Circ, 1996, 31(3):294-303
[5] R.E.Suarez, P.R.Gray, D.A.Hodges. An All-MOS Charge-Redistribution ADConversion Technique. ISSCC Dig Tech. Papers, New York: ISSCC.1974
[6]王晓艳.12位逐次逼近型ADC的研究与设计.西北大学硕士学位论文.2007年5月
[7]曹志刚,钱亚生.现代通信原理.清华大学出版社.1992年8月:25-30
[8] Hwang-cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, etc. A1.8V, 0.3mW, 10bitSAR ADC with New Self-timed Timing Control for Biomedical Applications.Circuits and System, 2005.ISCA2005.IEEE International Symposium on 23-26 May2005, Vol. l: 736-739
[9] Bahzad Razavi. Principle of Data Conversion System Design. IEEE press,1995:20
[10] J. Candy, G. Temes. Oversampling Delta-Sigma Data Converters. New York: IEEEPress, 1997
[11] Kevin J. McCall, Michael J.Demler, Michael W.Plante, A 6-bit 125MHz CMOSADC, IEEE 1992 Custom Integrated Circuits Conference, May 1992:16.8.1-16.8.4
[12] Q.Wu, A.Wang. A 12 bits/200MHz resolution/sampling/power-optimized ADC in0.25 SiGe BICMOS. IEEE International Symposium on Circuits and Systems.2005.vol.6:6174~6177
[13] Samiran Haier,et. A 160MSPS 8-bit pipeline based ADC.18th InternationalConference on VLSI Design.2005:313~318
[14] Carlos A. Vega de laCruz，A Switched Opamp Comparator to Improve theConversion Rate of Low-Power Low-Voltage Successive Approximation ADCs.University of Puerto Rico Mayguez Campus doctor’s Thesis 2005
[15] D. johns, K. Martin. Analog Integrated Circuit. John Wiley & Sons, INC. Chap.11-13,1997
[16] M. Steyaert, R. Roovers, J. Craninckx. A 100MHz 8-bit CMOS Interpolating ADC.IEEE Custom Integrated Circuits Conference, San Diego. May 1993:28.1.1-28.1.4
[17] M.P.Flynn, D.J.Allstot. CMOS Folding ADCs with Current-Mode Interpolation.IEEE J. of Solid State Circuits, vol.31, No.9:1248-57, Sept.1996
[18] S. H. Lewis. Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converter for Video-Rate Applications. IEEE Trans. On Circuit and System-11, vol. 39, no. 8:516-23, Aug.1992
[19] Rudy Van De Plassche. Integrated Analog to Digital and Digital to AnalogConverters. Kluwer Academic Publishers，1994
[20] B.E Boser, B. A. Wooley. The Design of Sigma-Delta Modulation Analog to DigitalConverters. IEEE J. Solid State Circuits, Vol.SC-23, pp, 1298~1308, Dec.1988
[21] Steven R. Norsworthy, Richard Schreier, Gabor C.Temes. Delta–Sigma DataConverters Theory Design and Simulation. Institute of Electrical and ElectronicsEngineers, Inc. 1997
[22]刘军.12位流水线ADC的研究与实现.暨南大学硕士学位论：2005年
[23]彭新芒，杨银堂，朱樟明等.一种8通道12位逐次逼近式ADC的设计.电子工程师，2007，33(4):54-56
[24] Phillip E Allen, Douglas R Holberg. CMOS模拟集成电路设计.第二版.冯军，李智群译.北京:电子工业出版社,2005:546
[25]包闻亮,鲍风编著.信号和通信系统.复旦大学出版社,1991:5~6
[26] D.J.Allstot. A Precision Variable-Supply CMOS Comparator. IEEE J.Solid StateCircuit,Vol.SC-17,No.6:1080-1087,Dec.1982
[27]康华光,陈大钦.模拟电子技术基础,第四版.北京:高等教育出版社.2003:205-207
[28] Hogervorst R, Tero J P, Eschauzier R G H, et. A compact power efficient 3V CMOSrail-to-rail input/output operational amplifier for VLSI cell libraries. IEEE J So l StaCirc, 1994; 29 (12): 150521512
[29] Huijsing J H, Linebarger D. Low-voltage operational amplifier with rail-to-rail inputand output ranges. IEEE J. Solid State Circuit, 1985,SC-20:1144~1150
[30] R.Hogervorst et. CMOS Low-Voltage Operational Amplifiers with Constant gmRail-to-Rail Input Stage. Analog Integrated Circuits and SignalProcessing,Vol.5,No.4:135-146,Mar.1994
[31] J.H. Botma et. Rail-to-Rail Constant-Gm Input Stage and Class AB Output Stage forLow-Voltage CMOS Opamps. Analog Integrated Circuits and SignalProcessing,Vol.6,No.2,pp.121-133,Sept.1994
[32]毕查德·拉扎维.模拟CMOS集成电路设计.陈贵灿，程军，张瑞智等译.西安:西安交通大学出版社, 2003: 248
[33]张强,李攀,田泽,陈贵灿,刘宁.高性能Rail to Rail恒定跨导CMOS运算放大器.微电子学与计算机，Vol . 25 No. 3 March 2008
[34]杨秀丽.基于CMOS工艺的10位SAR ADC的研究与设计.合肥工业大学硕士学位论文，2007年5月
[35]张亮.10位逐次逼近型模数转换器的设计.沈阳工业大学硕士学位论文，2006年3月
[36]王晗,叶青.0.6V电源电压的CMOS基准源设计及稳定性分析.半导体学报Vol .27 No. 8 Aug., 2006
[37]朱磊,杨银堂,朱樟明,付永朝.低压CMOS带隙电压基准源设计,固体电子学研究与进展.Vol . 25, No.2 May, 2005
[38]陈浩琼,高清运,秦世才.CMOS带隙电压基准的误差及其改进.固体电子学研究与进展,Vol .25, No. 4 Nov., 2005
[39] Chester Simpson.美国国家半导体公司应用注释1148,2000年5月
[40] Paulr.Gray, Paul J. Hurst Stephen H. Lewis. Analysis and Design of AnalogIntegrated Circuits. BEUNIG: Higher Education Press,2005:523-576
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