成本驱动的一种通用三维片上网络设计
摘要
根据ITRS的统计,越来越昂贵的设计成本逐渐成为半导体行业发展的阻力。为了解决这个问题,复用现有的设计资源是大势所趋。大部分传统的复用形式为IP,复用的级别一般是模块级别的复用。但是,当三维堆叠技术逐渐进入量产阶段,而且成为未来的主流技术之后,不同制造工厂生产的裸晶片可以采用三维集成技术自由的组合堆叠。于是本文大胆设想,将复用推广到片的级别,让制造检测好的已知合格片在不同的三维堆叠设计中使用。
在分析了大量现有的片上网络(NoC)的设计之后,本文发现：大部分的片上网络采用的都是相似的拓扑结构,即基于mesh的拓扑结构,而交换策略和路由方式也基本相似。这个发现为通用网络GNet的设计奠定了基础,即可以设计一种通用片上网络,它可以满足大部分片上网络设计的需求。
本文提出了通用网络GNet。它将众多网络服务集成在一个已知合格片中,这个片称为通用网络服务片(GNSD),该片可以与各种裸晶片堆叠为三维芯片,与其它功能片上的处理单元或存储单元组成片上网络。这种采用GNSD构建片上网络的体系结构称为GNet。采用GNet的网络有低功耗、高带宽、低延迟的优点,同时是动态可配置的,可以适用于大量不同的设计需求。
成本往往是决定一个新技术能否被推广使用的关键。为了衡量GNet体系结构的成本问题,本文在研究现有的成本模型的基础上,提出了一种涵盖了设计成本、复用成本和制造成本的综合成本模型。
为了更好的设计通用网络服务片,本文分析了大量的众核处理器的制造成本。实验对象为8、16、24、32、64、96、128、192、256个资源的众核处理器,在分析了它们的二维芯片制造成本,和划分成2—16层的三维芯片的制造成本之后,得出结论：在一定的集成电路制造缺陷密度下,要想获得最低的制造成本,必须让三维堆叠芯片的每个片的面积都接近最优划分面积。并确定了一定的平均电子缺陷密度下的最优划分面积。基于这个结论,本文设计了四种通用网络服务片,它们采用不同的工艺制造,设计者可以根据不同的设计需求来选择合适的通用网络服务片。
为了验证通用网络GNet的成本优势,本文对采用GNet的三维芯片和传统的三维芯片的进行了成本对比。最终得出结论,当一个众核处理器的片上网络的资源数目较小时(数目需要根据具体的工艺、资源大小等各项条件决定),二维芯片的成本低；当资源数目较多时,将该众核处理器采用三维方式来实现的成本更低。对于三维方式的两种实现方式：GNet和传统方式,采用GNet进行三维芯片设计,相比传统的三维芯片设计,设计成本将有大幅度降低,而制造成本变动不大。随着将来芯片复杂度的增加,设计成本迅速上涨,而能够减少设计成本的GNet三维片上网络体系结构会有很大的应用价值。
The expensive design cost has been becoming the greatest threat to continuation of the semiconductor roadmap according to ITRS's statistics. To circumvent this issue, reuse of the existing IC designs is the trend to reduce costs of electronic products. Most traditional reuse in ICs is in the form of IP cores. With emergence of3D IC technology in which KGDs are stacked to form an integrated circuit, a bold move that the reuse is pushed to the die level has been proposed in this work.
After examining the existing NoC architectures, it was found that most of the NoCs have similar architectures, which inspired the concept of GNet:a3D architecture for reusing generic network service dies (GNSDs). GNet-a3D architecture for reusing generic network service dies-is herein proposed to construct a network-on-chip (NoC) by virtue of exploiting reuse of known good dies (KGDs). In GNet, generic network service dies (GNSDs) are KGDs that integrate several networks and can be directly used to bond with other dies in3D stack. Flexible and configurable design of GNet makes it suitable to requirements in various application circumstances.
Cost is often the dominant factor for decision making on architecture selection and identifying the optimal design among various design options. A comprehensive cost model, which combines the design cost model, reuse model and fabrication model, is introduced to evaluate different architectures from the design phase to the fabrication phase.
By using designs whose sizes vary from16resources to256resources, the correlation between the fabrication cost and the die area was established, and an approximate optimal die area under a certain defect density has been identified. Based on the optimal die area, four GNSDs in four processes are designed. Finally, the cost comparison between the GNet implementation and the general3D IC implementation has been studied. For the GNet-based designs, the design costs would drastically drop whereas the fabrication costs would not change much within small deviations by comparison with the general3D ICs. According to statistics of ITRS, the design cost is the greatest threat to continuation of the semiconductor roadmap, and always reaches tens of millions of dollars. Since the design cost will weigh more and more in the total cost, the GNet implementation would become more superior to the traditional architectures.
在分析了大量现有的片上网络(NoC)的设计之后,本文发现：大部分的片上网络采用的都是相似的拓扑结构,即基于mesh的拓扑结构,而交换策略和路由方式也基本相似。这个发现为通用网络GNet的设计奠定了基础,即可以设计一种通用片上网络,它可以满足大部分片上网络设计的需求。
本文提出了通用网络GNet。它将众多网络服务集成在一个已知合格片中,这个片称为通用网络服务片(GNSD),该片可以与各种裸晶片堆叠为三维芯片,与其它功能片上的处理单元或存储单元组成片上网络。这种采用GNSD构建片上网络的体系结构称为GNet。采用GNet的网络有低功耗、高带宽、低延迟的优点,同时是动态可配置的,可以适用于大量不同的设计需求。
成本往往是决定一个新技术能否被推广使用的关键。为了衡量GNet体系结构的成本问题,本文在研究现有的成本模型的基础上,提出了一种涵盖了设计成本、复用成本和制造成本的综合成本模型。
为了更好的设计通用网络服务片,本文分析了大量的众核处理器的制造成本。实验对象为8、16、24、32、64、96、128、192、256个资源的众核处理器,在分析了它们的二维芯片制造成本,和划分成2—16层的三维芯片的制造成本之后,得出结论：在一定的集成电路制造缺陷密度下,要想获得最低的制造成本,必须让三维堆叠芯片的每个片的面积都接近最优划分面积。并确定了一定的平均电子缺陷密度下的最优划分面积。基于这个结论,本文设计了四种通用网络服务片,它们采用不同的工艺制造,设计者可以根据不同的设计需求来选择合适的通用网络服务片。
为了验证通用网络GNet的成本优势,本文对采用GNet的三维芯片和传统的三维芯片的进行了成本对比。最终得出结论,当一个众核处理器的片上网络的资源数目较小时(数目需要根据具体的工艺、资源大小等各项条件决定),二维芯片的成本低；当资源数目较多时,将该众核处理器采用三维方式来实现的成本更低。对于三维方式的两种实现方式：GNet和传统方式,采用GNet进行三维芯片设计,相比传统的三维芯片设计,设计成本将有大幅度降低,而制造成本变动不大。随着将来芯片复杂度的增加,设计成本迅速上涨,而能够减少设计成本的GNet三维片上网络体系结构会有很大的应用价值。
The expensive design cost has been becoming the greatest threat to continuation of the semiconductor roadmap according to ITRS's statistics. To circumvent this issue, reuse of the existing IC designs is the trend to reduce costs of electronic products. Most traditional reuse in ICs is in the form of IP cores. With emergence of3D IC technology in which KGDs are stacked to form an integrated circuit, a bold move that the reuse is pushed to the die level has been proposed in this work.
After examining the existing NoC architectures, it was found that most of the NoCs have similar architectures, which inspired the concept of GNet:a3D architecture for reusing generic network service dies (GNSDs). GNet-a3D architecture for reusing generic network service dies-is herein proposed to construct a network-on-chip (NoC) by virtue of exploiting reuse of known good dies (KGDs). In GNet, generic network service dies (GNSDs) are KGDs that integrate several networks and can be directly used to bond with other dies in3D stack. Flexible and configurable design of GNet makes it suitable to requirements in various application circumstances.
Cost is often the dominant factor for decision making on architecture selection and identifying the optimal design among various design options. A comprehensive cost model, which combines the design cost model, reuse model and fabrication model, is introduced to evaluate different architectures from the design phase to the fabrication phase.
By using designs whose sizes vary from16resources to256resources, the correlation between the fabrication cost and the die area was established, and an approximate optimal die area under a certain defect density has been identified. Based on the optimal die area, four GNSDs in four processes are designed. Finally, the cost comparison between the GNet implementation and the general3D IC implementation has been studied. For the GNet-based designs, the design costs would drastically drop whereas the fabrication costs would not change much within small deviations by comparison with the general3D ICs. According to statistics of ITRS, the design cost is the greatest threat to continuation of the semiconductor roadmap, and always reaches tens of millions of dollars. Since the design cost will weigh more and more in the total cost, the GNet implementation would become more superior to the traditional architectures.
引文
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