高速接口GTL Buffer研究与设计
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摘要
GTL(射集收发器逻辑)接口制约着微处理器性能的发挥,是微处理器重要组成部分。全定制方法设计的GTL接口速度快、可靠性高、兼容性好,具有开创性意义和广泛的应用价值。
本文研究了高性能GTL接口的全定制设计方法。文章从原理、逻辑结构、电路参数、物理版图等多个层次进行设计优化,在0.18μm CMOS工艺下实现了一款高性能GTL接口,并对高速接口的封装和测试方法进行研究,流片后实测结果显示:该接口频率可达600MHz。论文研究成果包括以下几点:
1、熟练掌握GTL接口技术理论,为高速接口理论研究奠定坚实的基础。
2、针对GTL输入接口工作模式特点,提出两级放大器方法实现输入接口,实际测量显示:此方法设计的输入接口具有较高的频率和分辨率。
3、针对传统模式不能实现高性能输出接口的缺点,独创性提出辅助充电方法,应用此方法设计的GTL输出接口的性能处于国际先进水平。
4、为提高GTL接口可靠性,充分模拟工艺、电压和温度对性能的影响,模拟结果显示:设计的GTL接口具有较好的抗PVT特性。
5、针对GTL接口芯片具有较高频率的特点,提出用COB封装减小封装对高频信号的影响,实测结果显示:此类封装满足设计要求。
6、针对GTL高速接口的特点,提出了适合此类特点的测试方法,实际应用显示:此方法具有方便、快捷、直接、准确等优点。
The frequency of GTL I/O Buffer is the bottleneck in the performance of the whole microprocessor, which is one of the most important units. The GTL I/O Buffer designed with the methodology of full custom can achieve high speed, high reliability and good compatibility, and it has great value in application and significant meaning in innovation.
This thesis emphasizes on full custom design methodology of high performance GTL I/O Buffer. The GTL I/O Buffer is optimized at theory level, logic level, circuit level and layout level, and is implemented in 0.18μm CMOS process. Furthermore, the testing technique and packaging technology of the high speed interface is discussed. The result of test is that the frequency of the GTL I/O Buffer has arrived at 600MHz. This thesis mainly contributes to the following aspects:
1. The theory of GTL interface technology has been researched, which is the solid foundation for research on high speed interface.
2. Considering the characteristic of GTL input interface, the input interface is realized with two grade amplifiers. The result of test is that the input interface designed with this method has high frequency and resolving power.
3. Considering the deficiency of traditional output interface, the method of auxiliary charge-up is proposed. The performance of GTL output interface designed with this method arrives at the advanced international level.
4. The infection of process, voltage and temperature on the performance is considered adequately to improve the reliability. The result of simulation is that the designed GTL interface operates stably with the PVT variability.
5. Considering the characteristic of higher frequency of GTL interface, the packaging mode of chip on board is proposed. The result of test is that this kind of packaging satisfies the request of design.
6. Considering the characteristic of GTL interface, the method of testing is proposed which is suitable for the characteristic. The practical application reveals that the advantages of this method are convenience, shortcut, directness, accuracy and so on.
本文研究了高性能GTL接口的全定制设计方法。文章从原理、逻辑结构、电路参数、物理版图等多个层次进行设计优化,在0.18μm CMOS工艺下实现了一款高性能GTL接口,并对高速接口的封装和测试方法进行研究,流片后实测结果显示:该接口频率可达600MHz。论文研究成果包括以下几点:
1、熟练掌握GTL接口技术理论,为高速接口理论研究奠定坚实的基础。
2、针对GTL输入接口工作模式特点,提出两级放大器方法实现输入接口,实际测量显示:此方法设计的输入接口具有较高的频率和分辨率。
3、针对传统模式不能实现高性能输出接口的缺点,独创性提出辅助充电方法,应用此方法设计的GTL输出接口的性能处于国际先进水平。
4、为提高GTL接口可靠性,充分模拟工艺、电压和温度对性能的影响,模拟结果显示:设计的GTL接口具有较好的抗PVT特性。
5、针对GTL接口芯片具有较高频率的特点,提出用COB封装减小封装对高频信号的影响,实测结果显示:此类封装满足设计要求。
6、针对GTL高速接口的特点,提出了适合此类特点的测试方法,实际应用显示:此方法具有方便、快捷、直接、准确等优点。
The frequency of GTL I/O Buffer is the bottleneck in the performance of the whole microprocessor, which is one of the most important units. The GTL I/O Buffer designed with the methodology of full custom can achieve high speed, high reliability and good compatibility, and it has great value in application and significant meaning in innovation.
This thesis emphasizes on full custom design methodology of high performance GTL I/O Buffer. The GTL I/O Buffer is optimized at theory level, logic level, circuit level and layout level, and is implemented in 0.18μm CMOS process. Furthermore, the testing technique and packaging technology of the high speed interface is discussed. The result of test is that the frequency of the GTL I/O Buffer has arrived at 600MHz. This thesis mainly contributes to the following aspects:
1. The theory of GTL interface technology has been researched, which is the solid foundation for research on high speed interface.
2. Considering the characteristic of GTL input interface, the input interface is realized with two grade amplifiers. The result of test is that the input interface designed with this method has high frequency and resolving power.
3. Considering the deficiency of traditional output interface, the method of auxiliary charge-up is proposed. The performance of GTL output interface designed with this method arrives at the advanced international level.
4. The infection of process, voltage and temperature on the performance is considered adequately to improve the reliability. The result of simulation is that the designed GTL interface operates stably with the PVT variability.
5. Considering the characteristic of higher frequency of GTL interface, the packaging mode of chip on board is proposed. The result of test is that this kind of packaging satisfies the request of design.
6. Considering the characteristic of GTL interface, the method of testing is proposed which is suitable for the characteristic. The practical application reveals that the advantages of this method are convenience, shortcut, directness, accuracy and so on.
引文
[1]洪志良编著.模拟集成电路分析与设计.北京:科学出版社,2005
[2]王荣良.计算机接口技术.北京:电子工业出版社,2003
[3]http://standards.ieee.org/reading/ieee/std_public/description/busarch/1596.3-1996desc.html
[4]Schumacher H.-JDikken,J.Seevinck E.CMOS Subnanosecond True-ECL Output Buffer.IEEE Journal of Solid-State Circuits.Volume,25,Issue,1 Feb,1990:150-154
[5]http://www.necel.com/memory/pdfs/M 14439EJ2VODS00.pdf
[6]覃正才.高速数据传输系统接口电路的研究:博士学位论文.上海:复旦大学,2002
[7]JDEC.http://www.jedec.org/download/search/jesd8-3.pdf
[8]Tom Granberg.Digital Techniques for High-Speed Design.America:Prentice Hall Modern Semiconductor Design Series,2004
[9]William F.Gunning,Los Hills,Calif.DRIVERS AND RECEIVERS FOR INTERFACING VLSI CMOS CIRCUITS TO TRANSMISSION LINES.America patent,1991
[10]Robert Russell Williams,Rochester,MN ASSISTED GLrNNING TRANSCEIVER LOGIC BUS DRIVER.America patent,2001
[11]Rodney Ruesch,Eau Claire,WI.GTL+ DRIVER.America patent,2004
[12]Yoji Nishio,Hideo Hara,Masahiro Iwamura,Yasuo Kaminaga,Katsunori Koike,Kosaku Hirose,Takayuki Noto,Satoshi Oguchi,Yoshihiko Yamamoto,Takeshi Ono.ASIC Conference and Exhibit,1994.Proceedings.,Seventh Annual IEEE International 19-23 Sept.1994 Page(s):112-115
[13]Pochang Hsu,Yanmei Tian,Gerald Pasdast.IEEE Transactions on Advanced Packaging,Vol.23,NO.3,August 2000
[14]甘学温编著.数字CMOS VLSI分析与设计基础.北京:大学出版社,1999
[15]朱正涌编著.半导体集成电路.北京:清华大学出版社,2001
[16]Jan M.Rabaey,Anantha Chandrakasan,Borivoje Nikolic著.数字集成电路--设计透视.北京:清华大学出版社,2004
[17]蔡懿慈等.超大规模集成电路设计导论.北京:清华大学出版社,2005
[18]毕查德·拉扎维著,陈贵灿,程军,张瑞智等译.模拟CMOS集成电路设计,西安:西安交通大学出版社,2003
[19]汪庆宝,宿昌厚编著.超大规模集成电路设计技术--从电路到芯片.北京: 电子工业出版社,1996
[20]D A Johns,K Martin.Aanlog Integrated Circuit Design..New York:John Wiley&Sons,1st edition,1997
[21]Tim Frodsham,Portland,Oreg GTL EDGE RATE CONTORL CIRCUIT.America patent,1996
[22]Ramzi Ammar,Charles Ajouri,Texas Instruments.GTL:a low-swing solution for high-speed digital logic.Digital Object Identifier,1995
[23]http://www.intel.com/design/itanium2/datashts/25379504.pdf
[24]http://www.cs.berkeley.edu/～rhuang/rhuang_thesis.pdf
[25]王东林,赵振宇,李少青.高速双终端SSTL输出设计.中国计算机学会第九届计算机工程与工艺学术年会,济南,2005
[26]王东林,李少青,赵振宇.A Design of High Speed AGTL+Output Buffer.The 6th International Conference on ASIC,上海,2005
[27]姚立真编著.可靠性物理.北京:电子工业出版社,2004
[28]Sung-Mo Kang Yusuf Leblebici著,王志功,窦建华等译.北京:电子工业出版社,2005
[29]赵振宇,陈怒兴,罗恒,吴虎成,陈跃跃.超大规模集成电路ESD保护设计技术.第八届计算机工程与工艺学术年会论文,2003
[30]柯明道,http://www.ics.ee.nctu.edu.tw/～mdker/ESD
[31]Christopher Saint,Judy Saint著.IC MASK DESIGN.北京:清华大学出版社,2004
[32]芯片封装技术.www.mcuchina.com/Article/EDA/Package/200412/337.html
[33]Howard Johnson,Martin Graham著,沈立,朱来文,陈宏伟等译.高速数字设计.北京:电子工业出版社,2004
[34]曹跃胜.高速PCB设计技术.计算机工程与科学,1998年第20卷第4期
[35]孙江宏,王艳林,李刚等编著.Prote DXP电路设计与仿真.北京:机械工业出版社,2003
[36]Bonnie.C.Baker.PCB布线设计.电子设计应用,2004年第3期
[2]王荣良.计算机接口技术.北京:电子工业出版社,2003
[3]http://standards.ieee.org/reading/ieee/std_public/description/busarch/1596.3-1996desc.html
[4]Schumacher H.-JDikken,J.Seevinck E.CMOS Subnanosecond True-ECL Output Buffer.IEEE Journal of Solid-State Circuits.Volume,25,Issue,1 Feb,1990:150-154
[5]http://www.necel.com/memory/pdfs/M 14439EJ2VODS00.pdf
[6]覃正才.高速数据传输系统接口电路的研究:博士学位论文.上海:复旦大学,2002
[7]JDEC.http://www.jedec.org/download/search/jesd8-3.pdf
[8]Tom Granberg.Digital Techniques for High-Speed Design.America:Prentice Hall Modern Semiconductor Design Series,2004
[9]William F.Gunning,Los Hills,Calif.DRIVERS AND RECEIVERS FOR INTERFACING VLSI CMOS CIRCUITS TO TRANSMISSION LINES.America patent,1991
[10]Robert Russell Williams,Rochester,MN ASSISTED GLrNNING TRANSCEIVER LOGIC BUS DRIVER.America patent,2001
[11]Rodney Ruesch,Eau Claire,WI.GTL+ DRIVER.America patent,2004
[12]Yoji Nishio,Hideo Hara,Masahiro Iwamura,Yasuo Kaminaga,Katsunori Koike,Kosaku Hirose,Takayuki Noto,Satoshi Oguchi,Yoshihiko Yamamoto,Takeshi Ono.ASIC Conference and Exhibit,1994.Proceedings.,Seventh Annual IEEE International 19-23 Sept.1994 Page(s):112-115
[13]Pochang Hsu,Yanmei Tian,Gerald Pasdast.IEEE Transactions on Advanced Packaging,Vol.23,NO.3,August 2000
[14]甘学温编著.数字CMOS VLSI分析与设计基础.北京:大学出版社,1999
[15]朱正涌编著.半导体集成电路.北京:清华大学出版社,2001
[16]Jan M.Rabaey,Anantha Chandrakasan,Borivoje Nikolic著.数字集成电路--设计透视.北京:清华大学出版社,2004
[17]蔡懿慈等.超大规模集成电路设计导论.北京:清华大学出版社,2005
[18]毕查德·拉扎维著,陈贵灿,程军,张瑞智等译.模拟CMOS集成电路设计,西安:西安交通大学出版社,2003
[19]汪庆宝,宿昌厚编著.超大规模集成电路设计技术--从电路到芯片.北京: 电子工业出版社,1996
[20]D A Johns,K Martin.Aanlog Integrated Circuit Design..New York:John Wiley&Sons,1st edition,1997
[21]Tim Frodsham,Portland,Oreg GTL EDGE RATE CONTORL CIRCUIT.America patent,1996
[22]Ramzi Ammar,Charles Ajouri,Texas Instruments.GTL:a low-swing solution for high-speed digital logic.Digital Object Identifier,1995
[23]http://www.intel.com/design/itanium2/datashts/25379504.pdf
[24]http://www.cs.berkeley.edu/～rhuang/rhuang_thesis.pdf
[25]王东林,赵振宇,李少青.高速双终端SSTL输出设计.中国计算机学会第九届计算机工程与工艺学术年会,济南,2005
[26]王东林,李少青,赵振宇.A Design of High Speed AGTL+Output Buffer.The 6th International Conference on ASIC,上海,2005
[27]姚立真编著.可靠性物理.北京:电子工业出版社,2004
[28]Sung-Mo Kang Yusuf Leblebici著,王志功,窦建华等译.北京:电子工业出版社,2005
[29]赵振宇,陈怒兴,罗恒,吴虎成,陈跃跃.超大规模集成电路ESD保护设计技术.第八届计算机工程与工艺学术年会论文,2003
[30]柯明道,http://www.ics.ee.nctu.edu.tw/～mdker/ESD
[31]Christopher Saint,Judy Saint著.IC MASK DESIGN.北京:清华大学出版社,2004
[32]芯片封装技术.www.mcuchina.com/Article/EDA/Package/200412/337.html
[33]Howard Johnson,Martin Graham著,沈立,朱来文,陈宏伟等译.高速数字设计.北京:电子工业出版社,2004
[34]曹跃胜.高速PCB设计技术.计算机工程与科学,1998年第20卷第4期
[35]孙江宏,王艳林,李刚等编著.Prote DXP电路设计与仿真.北京:机械工业出版社,2003
[36]Bonnie.C.Baker.PCB布线设计.电子设计应用,2004年第3期