基于SoC的实时红外图像高速通道设计与研究
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摘要
随着红外传感器品质及其应用目标的不断提高,要求热像仪中信息处理部件---红外图像高速通道性能与之匹配。信息技术的飞速发展为高速通道性能的提高提供了广阔前景。SoC(System on Chip,片上系统)强调软硬件协同信息处理,充分发挥硬件实时处理和软件功能灵活的优势,提高系统整体性能。
针对红外图像高速通道输入、处理和输出三个部分,设计了同步接口状态机、数据处理逻辑和伪彩色显示三大模块。设计将传统的用户硬联逻辑嵌入到SoC系统中,以Altera SOPC为原型实现了红外图像采集、处理与显示。并在此基础上提出红外图像高速通道模型描述,使红外通道设计提高到设计学的高度。
同步接口作为红外图像高速通道的前端,接收传感器输出信号,完成输入的转换与解码。有两种方式实现视频数据同步采集:方式一为同步A/D采集,完全由用户逻辑控制,特点是设计灵活;另一方式则是利用视频编解码器的中间结果,通过状态机提取同步数据,优点是兼容性好。编解码器通过I2C总线与配置文件,使得逻辑功能与配置参数分离,HDL(Hardware Description Language,硬件描述语言)设计代码维护更加容易。同步状态机的四个核心进程---水平消隐、垂直消隐、水平计数和垂直计数是整个高速通道数据处理基础。
数据处理逻辑接收同步接口状态机转换的传感器数据,对其进行缓存、传输和处理,以期提高数据信噪比和改善图像质量。它包括数据缓存、总线胶合和特征数据处理三个主要模块。数据缓存采用了双口RAM和帧行FIFO两种形式。双口RAM是采集接口和CPU共享数据资源的一个有效且成熟的构架,将用户逻辑与双口逻辑有机融合,与传统双口RAM相比具有更加灵活的总线协议接口。利用FPGA(Field Programmable Gate Array,现场可编程门阵列)片上RAM,提出了帧缓存和行缓存方式以适合不同的系统构成。采用PLD(Programmable Logic Device,可编程逻辑器件)技术的胶合逻辑能够适配多种CPU总线,通过更新其中的逻辑编程以满足不同的系统构架。十字线点温测量硬联逻辑作为数据测量的基本功能,是红外检测的基础。
热像显示是SoC实时红外图像高速通道最终输出结果,一方面提供被测目标客观特征数据,同时也向用户展示可视化温度分布信息,直观全面地了解对象,有助于现场诊断。采用伪彩色图像增强SoC技术在功能上实现了检测数据可视化,在效率上做到了热像实时显示。设计分为两个层次:底层由“数据位直联”和“RAM调色板”逻辑模块完成数据到色彩的基本映射关系;然后通过Altera Nios嵌入式处理器和Avalon片上总线在SoC层实现了伪彩色显示。用户逻辑模块封装体现了IP Core(Intellectual Property Core,知识产权核)再使用原则,充分保护设计投资。
借鉴UML(Unified Modeling Language,统一建模语言)和Petri网建模理论,提出了红外高速通道模型,据此建立了红外图像处理系统高速通道的双FIFO缓存工作模式状态图模型和Petri网模型HDL描述。
研究概述了当前主流设计模式,并给出作者研发的多个模型性能结果。其主要创新点在于:采用SoC技术设计红外图像高速通道,保证信号采集、数据处理和信息显示的实时性;充分利用PLD片上可编程资源,建立了逻辑双口RAM和多FIFO行缓存灵活机制的红外图像高速通道存储构架;运用嵌入式处理器Nios“用户定制指令”和“Avalon模块”手段作为处理关键算法的有效手段,实现红外图像伪彩色实时显示;借鉴UML与Petri网丰富的模型语义提出红外图像高速通道模型规约,保证了较高的抽象层描述的正确性。
最后,根据作者主持的研究课题列出三类红外高速通道的性能结果,揭示了各自特性。即(1)SoC技术采用HDL逻辑功能描述、片上处理器软硬件协同开发模式实现数据实时处理(;2)PLD接口通过其强大的硬件功能作为接口或桥拓展CPU I/O,完成数据的采集与显示;(3)集成电子在原有系统的基础上,整合分散的电子硬件功能,实现系统集成化、小型化。展望未来,掌握SoC设计理念,采用可执行模型描述设计方法学,将ADL(Architecture Description Language,系统结构描述语言)、ASIP(Application Specific Instruction Processor,专用指令集处理器)等先进技术融入系统实现,使红外高速通道性能产生质的飞跃!
With the incessant improvement of the trait and application of the sensor, it requires a performance matching for the high-speed channel of infrared image, which is the process unit of the thermal image instrument. The fast development of information technology provides an extensive prospect for the high-speed channel. SoC(System on Chip) emphasizes the co-operation between hardware and software , exerts the advantage between the real-time processing of hardware and the flexibility of software. It improves the performance of system.
We design three modules that the state machine of synchronous interface, data processing logic and the pseudo color display for the input , processing and output of high-speed channel of infrared image. The project embeds the traditional hard joint logic of user in SoC system and implements the acquisition, processing and display of infrared image based on Altera SOPC. Then the module of high-speed channel of infrared image is present and is make to a new stature.
The synchronous interface, as the front-end of high-speed channel of infrared image, receives the output signal of sensor and achieves the transfer and decode of input from sensor. There are two method implement the synchronous acquisition of video, one is synchronous A/D acquisition, it is entirely controled by user logic and have the trait of flexible design. The other takes the video codec as a transition and obtains synchronous data using state machine, this way has the trait of compatibility. Codec makes logic function and configuration parameters separate and HDL ( Hardware Description Language)designing code maintenance easier through I2C bus and configuration files. The synchronous state machine’s four kernel processes that horizontal blanking, vertical blanking, horizontal counter and vertical counter are the foundation of high-speed channel.
The date processing logic receives transformed data from the state machine of synchronous interface, then buffers, transmits and processes the date for improving the SNR and the quality of image. It includes three main modules that data buffer, bus bind and characteristic data processing. The data buffer adopts dual RAM and frame buffer FIFO. The dual RAM is an effective and mature framework between acquisition interface and the shared data of CPU, it fuses the user logic and dual logic more flexible bus protocol interface than traditional dual RAM. We present frame buffer and line buffer for difference system using the on-chip RAM of FPGA(Field Programmable Gate Array) and introduces the bind logic of PLD(Programmable Logic Device) for various CPU bus. We supply the need for the various system framework by updating the logic programme. The hard joint logic of cross-line contact thermometer, as the fundamental functions of measure, is the base of infrared test.
The thermal imagery display is the final output of SoC high-speed channel of infrared image, it provides the characteristic data of measured object, displays the visual temperature distribution to user, recognizes the object entirely, and makes easy to on-site diagnosis. Image enhancement with pseudo color implements the visualization of measured data and display of real-time image. The project is divided into two hierarchy. bottom layer is composed of“vertical association of data bit”and“RAM color palette”, it achieves the basic mapping from data to color ; top layer is composed of display module based on Altera Nios microcontroller and the on-chip bus of Avalon. The encapsulation of user logical module incarnates the reuse principle of IP core (Intellectual Property Core) and protects the investment.
We present the module of infrared high-speed channel by means of UML(Unified Modeling Language) and the modeling theory of Petri, then we set up the other module which is composed of the state graph of dual FIFO buffer and Petri based on HDL by this module.
The study summarized mainstream design patterns of the current, and presented a number of model performance results the author had researched. Its main innovation is that using SoC Technical to design high-speed infrared image channel, guaranteeing the real-time of signal acquisition, data processing and information display, taking full advantage of the programmable resources of PLD on chip to establish the high-speed infrared image channel storage architecture of a logic dual-port RAM and more flexible row FIFO buffer mechanism, using Customized Orders and Avalon Module of embedded processors as the effective means of dealing with the key algorithms to realize real-time infrared image pseudo-color display and referencing the rich semantic model of UML and Petri Net to have proposed high-speed infrared image channel model statute and have guaranteed the higher accuracy of the abstract description.
At last,the text listed three types of the performance results of high-speed infrared channel according to the author’s research topics And revealed their characteristics. Firstly, SoC Technology uses HDL Description of logic function and Synergy - chip processor hardware and software development model to realize the real-time processing of data, secondly, PLD Interface through its powerful hardware function as interface or a bridge expansion CPU I/O and complete the data acquisition and display, thirdly, the integrated electron on the basis of the original system integrates the scattered electronic hardware function to achieve the Integration and Miniaturization of the System. Looking to the future, mastering SoC designing concept, using the executable model description Design Methodology and putting the advanced technology of ADL( Architecture Description Language,System Architecture Description Language)and ASIP(Application Specific Instruction Processor,Special Instruction Set Processor)into the System Implementation ,all that can make a qualitative leap of Infrared high-speed channel in performance!
针对红外图像高速通道输入、处理和输出三个部分,设计了同步接口状态机、数据处理逻辑和伪彩色显示三大模块。设计将传统的用户硬联逻辑嵌入到SoC系统中,以Altera SOPC为原型实现了红外图像采集、处理与显示。并在此基础上提出红外图像高速通道模型描述,使红外通道设计提高到设计学的高度。
同步接口作为红外图像高速通道的前端,接收传感器输出信号,完成输入的转换与解码。有两种方式实现视频数据同步采集:方式一为同步A/D采集,完全由用户逻辑控制,特点是设计灵活;另一方式则是利用视频编解码器的中间结果,通过状态机提取同步数据,优点是兼容性好。编解码器通过I2C总线与配置文件,使得逻辑功能与配置参数分离,HDL(Hardware Description Language,硬件描述语言)设计代码维护更加容易。同步状态机的四个核心进程---水平消隐、垂直消隐、水平计数和垂直计数是整个高速通道数据处理基础。
数据处理逻辑接收同步接口状态机转换的传感器数据,对其进行缓存、传输和处理,以期提高数据信噪比和改善图像质量。它包括数据缓存、总线胶合和特征数据处理三个主要模块。数据缓存采用了双口RAM和帧行FIFO两种形式。双口RAM是采集接口和CPU共享数据资源的一个有效且成熟的构架,将用户逻辑与双口逻辑有机融合,与传统双口RAM相比具有更加灵活的总线协议接口。利用FPGA(Field Programmable Gate Array,现场可编程门阵列)片上RAM,提出了帧缓存和行缓存方式以适合不同的系统构成。采用PLD(Programmable Logic Device,可编程逻辑器件)技术的胶合逻辑能够适配多种CPU总线,通过更新其中的逻辑编程以满足不同的系统构架。十字线点温测量硬联逻辑作为数据测量的基本功能,是红外检测的基础。
热像显示是SoC实时红外图像高速通道最终输出结果,一方面提供被测目标客观特征数据,同时也向用户展示可视化温度分布信息,直观全面地了解对象,有助于现场诊断。采用伪彩色图像增强SoC技术在功能上实现了检测数据可视化,在效率上做到了热像实时显示。设计分为两个层次:底层由“数据位直联”和“RAM调色板”逻辑模块完成数据到色彩的基本映射关系;然后通过Altera Nios嵌入式处理器和Avalon片上总线在SoC层实现了伪彩色显示。用户逻辑模块封装体现了IP Core(Intellectual Property Core,知识产权核)再使用原则,充分保护设计投资。
借鉴UML(Unified Modeling Language,统一建模语言)和Petri网建模理论,提出了红外高速通道模型,据此建立了红外图像处理系统高速通道的双FIFO缓存工作模式状态图模型和Petri网模型HDL描述。
研究概述了当前主流设计模式,并给出作者研发的多个模型性能结果。其主要创新点在于:采用SoC技术设计红外图像高速通道,保证信号采集、数据处理和信息显示的实时性;充分利用PLD片上可编程资源,建立了逻辑双口RAM和多FIFO行缓存灵活机制的红外图像高速通道存储构架;运用嵌入式处理器Nios“用户定制指令”和“Avalon模块”手段作为处理关键算法的有效手段,实现红外图像伪彩色实时显示;借鉴UML与Petri网丰富的模型语义提出红外图像高速通道模型规约,保证了较高的抽象层描述的正确性。
最后,根据作者主持的研究课题列出三类红外高速通道的性能结果,揭示了各自特性。即(1)SoC技术采用HDL逻辑功能描述、片上处理器软硬件协同开发模式实现数据实时处理(;2)PLD接口通过其强大的硬件功能作为接口或桥拓展CPU I/O,完成数据的采集与显示;(3)集成电子在原有系统的基础上,整合分散的电子硬件功能,实现系统集成化、小型化。展望未来,掌握SoC设计理念,采用可执行模型描述设计方法学,将ADL(Architecture Description Language,系统结构描述语言)、ASIP(Application Specific Instruction Processor,专用指令集处理器)等先进技术融入系统实现,使红外高速通道性能产生质的飞跃!
With the incessant improvement of the trait and application of the sensor, it requires a performance matching for the high-speed channel of infrared image, which is the process unit of the thermal image instrument. The fast development of information technology provides an extensive prospect for the high-speed channel. SoC(System on Chip) emphasizes the co-operation between hardware and software , exerts the advantage between the real-time processing of hardware and the flexibility of software. It improves the performance of system.
We design three modules that the state machine of synchronous interface, data processing logic and the pseudo color display for the input , processing and output of high-speed channel of infrared image. The project embeds the traditional hard joint logic of user in SoC system and implements the acquisition, processing and display of infrared image based on Altera SOPC. Then the module of high-speed channel of infrared image is present and is make to a new stature.
The synchronous interface, as the front-end of high-speed channel of infrared image, receives the output signal of sensor and achieves the transfer and decode of input from sensor. There are two method implement the synchronous acquisition of video, one is synchronous A/D acquisition, it is entirely controled by user logic and have the trait of flexible design. The other takes the video codec as a transition and obtains synchronous data using state machine, this way has the trait of compatibility. Codec makes logic function and configuration parameters separate and HDL ( Hardware Description Language)designing code maintenance easier through I2C bus and configuration files. The synchronous state machine’s four kernel processes that horizontal blanking, vertical blanking, horizontal counter and vertical counter are the foundation of high-speed channel.
The date processing logic receives transformed data from the state machine of synchronous interface, then buffers, transmits and processes the date for improving the SNR and the quality of image. It includes three main modules that data buffer, bus bind and characteristic data processing. The data buffer adopts dual RAM and frame buffer FIFO. The dual RAM is an effective and mature framework between acquisition interface and the shared data of CPU, it fuses the user logic and dual logic more flexible bus protocol interface than traditional dual RAM. We present frame buffer and line buffer for difference system using the on-chip RAM of FPGA(Field Programmable Gate Array) and introduces the bind logic of PLD(Programmable Logic Device) for various CPU bus. We supply the need for the various system framework by updating the logic programme. The hard joint logic of cross-line contact thermometer, as the fundamental functions of measure, is the base of infrared test.
The thermal imagery display is the final output of SoC high-speed channel of infrared image, it provides the characteristic data of measured object, displays the visual temperature distribution to user, recognizes the object entirely, and makes easy to on-site diagnosis. Image enhancement with pseudo color implements the visualization of measured data and display of real-time image. The project is divided into two hierarchy. bottom layer is composed of“vertical association of data bit”and“RAM color palette”, it achieves the basic mapping from data to color ; top layer is composed of display module based on Altera Nios microcontroller and the on-chip bus of Avalon. The encapsulation of user logical module incarnates the reuse principle of IP core (Intellectual Property Core) and protects the investment.
We present the module of infrared high-speed channel by means of UML(Unified Modeling Language) and the modeling theory of Petri, then we set up the other module which is composed of the state graph of dual FIFO buffer and Petri based on HDL by this module.
The study summarized mainstream design patterns of the current, and presented a number of model performance results the author had researched. Its main innovation is that using SoC Technical to design high-speed infrared image channel, guaranteeing the real-time of signal acquisition, data processing and information display, taking full advantage of the programmable resources of PLD on chip to establish the high-speed infrared image channel storage architecture of a logic dual-port RAM and more flexible row FIFO buffer mechanism, using Customized Orders and Avalon Module of embedded processors as the effective means of dealing with the key algorithms to realize real-time infrared image pseudo-color display and referencing the rich semantic model of UML and Petri Net to have proposed high-speed infrared image channel model statute and have guaranteed the higher accuracy of the abstract description.
At last,the text listed three types of the performance results of high-speed infrared channel according to the author’s research topics And revealed their characteristics. Firstly, SoC Technology uses HDL Description of logic function and Synergy - chip processor hardware and software development model to realize the real-time processing of data, secondly, PLD Interface through its powerful hardware function as interface or a bridge expansion CPU I/O and complete the data acquisition and display, thirdly, the integrated electron on the basis of the original system integrates the scattered electronic hardware function to achieve the Integration and Miniaturization of the System. Looking to the future, mastering SoC designing concept, using the executable model description Design Methodology and putting the advanced technology of ADL( Architecture Description Language,System Architecture Description Language)and ASIP(Application Specific Instruction Processor,Special Instruction Set Processor)into the System Implementation ,all that can make a qualitative leap of Infrared high-speed channel in performance!
引文
[1]R. Otten, P. Stravers. Challenges in Physical Chip Design. International Conference on Computer Aided Design (ICCAD), 2000.84-91
[2]B. Hutchings,B. Nelson. Using General-Purpose Programming Languages for FPGA Design. Design Automation Conference, June 2000. 561-566
[3]朱勇.数字逻辑(第一版)[M].北京:中国铁道出版社,2005:253-254
[4]863 -中国高技术研究发展计划.http://159.226.2.5:7777/search.wct
[5]国家自然科学基金重大研究计划.http://www.nsfc.gov.cn/nsfc/cen/02/ htmlcreated/2002-5.htm
[6]Baloch S.,Ahmed I.,Arslan T.,Stoica A. Low power domain-specific reconfigurable array for discrete wavelet transforms targeting multimedia applications[J]. Field Programmable Logic and Applications, 2005. International Conference Aug. 24-26, 2005:618-621
[7]Baloch S.,Ahmed I.,Arslan T. Domainspecific reconfigurable array targeting discrete wavelet transform for system-on-chip applications. Parallel and Distributed Processing Symposium, 2005 Proceedings,19th IEEE International conference 4-8 April 2005
[8]Sajid Baloch et al. Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques. Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)
[9]Frank Vahid. The softening of hardware[J]. Computer, 2003,36(4):27-34.
[10]L.V. Agostini, I.S. Silva, S. Bampi. Pipelined fast 2d DCT architecture for JPEG image compression. In Integrated Circuits and Systems Design, 2001, 14th Symposium on Pirenopolis, Brazil, 2001.226-231
[11]K. Z. Bukhari, G.K. Kuzmanov, S. Vassiliadis. Dct and idct implementations on different fpga technologies. In Proceedings of ProRISC 2002, November2002 .232-235
[12]Antonino Tumeo et al. A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs.IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07)
[13]陈衡,侯善敬.电力设备故障红外诊断(第一版)[M].北京:中国电力出版社,1999:58-100
[14]陆家兵,鲍晓静,唐建博.基于PCI总线的视频图像采集系统设计与实现[J].计算机测量与控制,2004,12(11):1110-1112.
[15]Geoffray , Herve , Guerin , et al. Measured performance of a low2cost thermal infrared pushbroom camera based on uncooled microbolometer FPA for space applications. Proc. SPIE , 2001 , 4540(1):298-308
[16]朱勇.调色板在热象中的应用[J].自动化仪表,2001,22 (3):28-29
[17]朱勇.用OpenGL实现红外图像伪彩色处理[J].微计算机信息,2002,18(9):51-56
[18]Yong Zhu,JiangLing Zhang. The infrared video image pseudocolor processing system. SPIE. APPL OF DIGITAL IMAGE PROCESSING XXVI Vol. 5203,2003,11
[19]Yong Zhu,JiangLing Zhang. The implementation of thermal image visualization by HDL based on pseudo color. SPIE. Applications of Digital Image Processing XXVII Vol. 5558,2004,11
[20]XIE H et al. SAR speckle reduction using wavelet denoising and Markov random field modeling[J]. IEEE Trans. Geosci. Remote Sens. , 2002 , 40 (10) :2196-2212
[21]G.Pajares, J M Cruz. A. wavelet based image fusion tutorial[J]. Pattern Recognition ,2004 ,37 (9) :1855-1872
[22] G Piella. A general framework for multiresolution image fusion :from pixels to regions[J]. Information Fusion ,2003 ,4 (4) :259-280
[23] M N Do, M Vetterli Contourlets , G V Welland. Beyond Wavelets. New York :Academic Press ,2003.
[24] M N Do ,M Vetterli. The contourlet transform : an efficient directional multiresolution image representation[J]. IEEE Transactions on Image Processing ,2005 ,14 (12) :2091-2106
[25]朱勇.基于SoC的红外图像系统数据通道设计.2005年全国单片机与嵌入式系统学术交流会论文集,2005,335-339
[26]朱勇.红外热象数字处理系统[J].仪表技术与传感器,2001,13(9):13-15
[27] HARRIS J G, CHIANG Yu Ming. Nonuniformity correction of infrared image sequences using the constant statistics constraint. IEEE Transactions on Image Processing, 1999, 8(8) :1148-1151.
[28]陈立法等.基于PCI总线的实时红外图像采集处理系统.红外技术,2001,23(5):4-8
[29] Chih-Chin lai, Chuan-Yu chang. A hierarchical genetic algorithm based approach for image segmentation. Networking, Sensing and Control, 2004 IEEE International Conference on, 2004(2) :1284-1288.
[30]邱翰,桑农,李立.基于NiosII的红外图像处理系统设计[J].微电子学,2006,32(6):241-244
[31]孔令彬,王川,许鸿文,戚建汉.基于Nios红外图像实时非均匀性校正研究.华中科技大学学报,2005,33(12):70-72
[32]贺明,王新赛.基于Nios软核的实时红外图像自动跟踪系统设计.红外技术,2007,29(1):34-37
[33] Nobuyuki Ohba,Kohji Takano. An SoC Design Methodology Using FPGAs and Embedded Microprocessors. Proceedings of the 41st Design Automation Conference (DAC’04) .747-752
[34] FENNER J W, SCRIBNER D A. Design of IRFPA nonuniformity correction algorithm to be implemented as a real-time hardware prototype. SPIE,1994,v2225 . 350-359
[35] Vicker V E. Plateau equalization algorithm for real time display of high- quality infrared imagery[J]. Opt Eng,1996, 35 (7) :1821-1826.
[36]王波,吴新建.基于NiosII的红外图像灰度变换系统设计[J].光学与光电技术,2007,5(2):45-51.
[37] iroyuki Tomiyama et al. Architecture Description Language for System-on-Chip Design. http://www.cecs.uci.edu/~aces
[38] George Hadjiyiannis, Silvina Hanono, Srinivas Devadas. IDSL An Instruction Set Description Language for Retargetability. Design Automation Conference,1997
[39] Oliver Schliebusch et al. Architecture Implementation Using the Machine Description Language LISA. Proceedings of the 15th International Conference on VLSI Design (VLSID.02)
[40] Lu L, Li X, Xiong Y et al. XML-ADL, an extensible markup architecture description language. ASIC/SOC Conference, 15th Annual IEEE International, 2002
[41]杨君.专用指令集处理器(ASIP)体系结构设计研究[J].中国科学技术大学博士论文,2006,28(10):1572-1577.
[42] ZHU Yong. The Specification of the Embedded System of Real-time IR. DCABES2007
[43] Schulz M et al. Nonuniformity correction and correctability of infrared focal plane arrays[J]. INFRARED PHYSICS&TECHNOLOGY,1995,2470(36): 763-777.
[44] Harris J G et al. Nonuniformity correction using the constant-ststistics constraint : analog and digital implementations[J]. SPIE,1997, 3061(1):895-905.
[45] Li Xiying. Real-time image histogram equalization using FPGA[J]. SPIE,1998,3561(1):293-299.
[46] Chang D. C. ,Wu W R. Image contrast enhancement based on a histogram transformation of local standard deviation[J]. IEEE TransMedical Imaging , 1998 , 17 (4):518-531.
[47] Kya BERTHE,Yang YANG. Automatic edge and target extraction base on Pulse-Couple Neuron Networks Wavelet theory (PCNNW)[J]. SPIE, 2002 , 4668(1):504-509.
[48] Tzannes A P , Brooks D H. Detecting Small Moving Objects Using Temporal Hypothesis Testing[J]. IEEE Trans on Aerospace and Electronic System , 2002 , 38(2):570-586.
[49] Shimonomuar K,Kameda S,Yagi T. Silicon Retina System Applicable to Robot Vision[J]. Proceedings of the 2002 International Joint Conference on Neural Networks : Vol 3[C],. Madrid : UAM, 2002.2276-2281.
[50] Li S T , Kwok J T , Wang Y N. Using the discrete wavelet frametransform to merge Landsat TM and SPOT panchromatic images. Elsevier Science, Information Fusion, 2002 .17-23
[51] L. Tao and V. K. Asari. An Adaptive and Integrated Neighborhood Dependent Approach for Nonlinear Enhancement of Color Images. SPIE, Journal of Electronic Imaging, 2005,14(4):2216-2548
[52] Li Tao et al. Multi-sensor Image Fusion and Enhancement System for Assisting Drivers in Poor Lighting Conditions. Proceedings of the 34th Applied Imagery and Pattern Recognition Workshop (AIPR05)
[53] Michelle Tomkinson, Brian Teaney, Jeffrey Olson. Dual Band Sensor Fusion for Urban Target Acquisition[J]. Proceedings of SPIE, 2005, 5784(1):27-34
[54] SAA7113H_2. 9-bit video input processor. www.nxp.com/acrobat_download/ datasheets/SAA7113H_2.pdf
[55] Thermal-Eye 3600AS Integration Guide. http://www.thermal-eye.com/Upload/files/ manuals/36-45Integration%20Guide.pdf
[56] Thermal-Eye 3600AS Expansion Port Supplement. http://www.thermal-eye.com/ Upload/files/manuals/36-45Expansion%20Port%20Supplement1.pdf
[57] SCC500? Specifications. http://www.eis.na.baesystems.com/brochures/ pdfs/iis_04 _a09.pdf
[58]朱勇.CPLD显示存储器共享技术[J].电测与仪表,1999,36(7):51-53.
[59] K. Ryu, E. Shin, V. Mooney. A Comparison of Five Different Multiprocessor SoC Bus Architectures. Proceedings of the EUROMICRO Symposium on Digital Systems Design (EUROMICRO' 01), pp202~209, September 2001
[60]朱勇.PC/104总线嵌入式工控计算机系统[J].计算机应用研究,1996,13(6):94-95
[61] Tom Shanley, Don Anderson.刘晖等译. PCI系统结构(第四版)[M].北京:电子工业出版社,2000:1-30
[62]徐江丰等.基于Wishbone-PCI Bridge核的红外图像高速采集系统[J].红外与激光工程,2006,35(6):713-716.
[63] PCI 9054 Data Book. http://www1.plxtech.com/TEMP/82475/9054db-21.pdf
[64] Kanungo T,MountD M,Netanyahu N S. An efficient K-means clustering algorithm: analysis and imp lamentation[J]. IEEE trans. PAM I,2002,24 (7):881-892.
[65]陈国群,付冬梅,常晓辉.基于聚类算法的红外图像伪彩色增强[J].激光与红外,2007, 37(4):384-388.
[66]张文峦,梁敏,李言俊.一种改进的伪彩色图像融合方法[J].探测与控制学报,2007, 29(1):48-51.
[67]黄光华,倪国强,张彬.基于Land实验的可见红外伪彩色图像融合方法[J].光学技术,2007,33(1):98-101.
[68] Lu Yuanlin, Wang Zhigong, Qiao Lufeng, er al. Design and Implementation of Multi-channel High Speed HDLC Data Processor. 2002 International Conference on Communications Circuits and Systems and West Sino Expositions Proceedings LC, Chengdu, China: UESTC Press, 2002. 1471-1475
[69]朱勇,张江陵.RAID高速通道IP设计[J].计算机工程,2003, 29(6):153-154,157.
[70]朱勇,张江陵.RAID光纤通道适配器设计[J].计算机工程与应用,2002,38(14):17-18.
[71] Custom Instructions for the Nios Embedded Processor. http://www.altera.com.cn/ literature/an/an188.pdf
[72] Nios Custom Instructions Tutorial. http://www.altera.com.cn/literature/ tt/tt_nios_ ci.pdf
[73] Avalon Switch Fabric Features. http://www.altera.com.cn/products/software/ products/sopc/avalon/nio-avalon_features.html#figure1
[74] Avalon Interface Specification. http://www.altera.com/literature/manual/ mnl_avalon_ spec.pdf
[75]徐宁仪,周祖成.Avalon总线与SOPC系统架构实例[J].半导体技术,2003, 24(6):17-20.
[76] Frank Engel et al. An Open GNSS Receiver Platform Architecture. The 2004 International Symposium on GNSS/GPS,Sydney, Australia 6–8 December 2004
[77]朱勇.在屏显示器件MC141541及其接口技术[J].国外电子元器件,2002, 18(3) :18-20.
[78] Daniel等著.边计年等译.嵌入式系统的描述与设计(第一版)[M].北京:机械工业出版社,2005:35
[79]朱勇.基于三层逻辑的VIA设计[J].广西师范大学学报,2005,23(1):42-45.
[80]王晓光,冯耀东,梅宏.ABC/ADL:一种基于XML的软件体系结构描述语言[J].计算机研究与发展,2004, 41(6):1521-1531.
[81] Zhang Guangquan. Describing Software Architecture Style with XYZ/E. Proc. Of the 5th Inter. For Young Comp. Sci. International Academic Pblisher,ICYCS-2003 2003,8. 171-174
[82]张广泉,戎玫,陈琳琳.UML与软件体系结构描述语言之间的转换机制研究[J].计算机科学,2007 ,134(6):262-269.
[83] Bruce Power Douglass著.柳翔等译.嵌入式与实时系统开发–实用UML、对象技术、框架与模式[M].北京:机械工业出版社,2005:187-200
[84]林闯.随机Petri网和系统性能评价(第1版)[M].北京:清华大学出版社,2000:1-2
[85] Zhan JY et al. Formal co-verification for SoC design with colored Petri net. eds. Proc. of the ICESS 2004. LNCS 3605, Berlin: Springer-Verlag, 2005. 188-195
[86] Blume H, von Sydow T, Noll TG. Performance analysis of SoC communication by application of deterministic and stochastic Petri nets. In: Pimentel A, Vassiliadis S, eds. Proc. of the SAMOS 2004. LNCS 3133, Berlin: Springer-Verlag, 2004. 484-493
[87]余金山等.基于扩展层次有色Petri网创建SoC高层可执行规约[J].Journal of Software, 2006, 17(11):148-153.
[88]朱赟.基于Petri网的ASIP体系结构形式化建模方法研究[J].小型微型计算机系统,2006, 27(9):1722-1725.
[89]赵不贿等.Petri网的硬件实现[J].软件学报,2002,13(8):1652-1657.
[90] Yakovlev, A., Goes, L., Lavagno, L. Hardware Design and Petri Nets[J]. Boston: Kluwer Academic Publishers, 2000,1806(3):1553-1562.
[91]朱勇,张江陵.基于文件管理系统的扩展存储体高速通道.中国国际存储技术大会论文集, 2002:5
[92]刘仁峰等.一个嵌入式系统的Petri网模型与CPLD实现[J].电子技术应用,2003, 29(9):51-53.
[93]陈林,黄建文.基于SystemC的系统级设计方法[J].计算机应用研究,2003,20(9):113-115.
[94] T. Groetker, S. Liao, G. Martin, S. Swan. System Design with SystemC[M]. Kluwer Academic Publishers, 2002:50-80
[95] L. Cai, D. Gajski. C/C++ Based System Design Flow Using SpecC, VCC and SystemC. CECS Technical Report 02-30, UC Irvine, CA, 2002
[96] D.D. Gajski, J. Zhu, R. Doemer, A. Gerstlauer, and S. Zhao. SpecC: Specification Language and Methodology[M]. Kluwer Academic Publishers, 2000:46-89
[97] A. Gerstlauer, R. Doemer, J. Peng, D.D. Gajski. System Design: A Practical Guide with SpecC[M]. Kluwer Academic Publishers, 2001:36-68
[98] E. B?rger and R. St?rk. Abstract State Machines: A Method for High-Level System Design and Analysis. Springer Verlag, 2003
[99] M. Edwards and P. Green. UML for hardware and software object modeling. UML for real design of embedded real-time systems, 2003:127-147
[100] E. Riccobene, P. Scandurra, A. Rosti, and S. Bocchio. A Model-driven Co-design Flow for Embedded Systems. In FDL’06: Proceedings of Forum on Specification and Design Languages, 2006.
[2]B. Hutchings,B. Nelson. Using General-Purpose Programming Languages for FPGA Design. Design Automation Conference, June 2000. 561-566
[3]朱勇.数字逻辑(第一版)[M].北京:中国铁道出版社,2005:253-254
[4]863 -中国高技术研究发展计划.http://159.226.2.5:7777/search.wct
[5]国家自然科学基金重大研究计划.http://www.nsfc.gov.cn/nsfc/cen/02/ htmlcreated/2002-5.htm
[6]Baloch S.,Ahmed I.,Arslan T.,Stoica A. Low power domain-specific reconfigurable array for discrete wavelet transforms targeting multimedia applications[J]. Field Programmable Logic and Applications, 2005. International Conference Aug. 24-26, 2005:618-621
[7]Baloch S.,Ahmed I.,Arslan T. Domainspecific reconfigurable array targeting discrete wavelet transform for system-on-chip applications. Parallel and Distributed Processing Symposium, 2005 Proceedings,19th IEEE International conference 4-8 April 2005
[8]Sajid Baloch et al. Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques. Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)
[9]Frank Vahid. The softening of hardware[J]. Computer, 2003,36(4):27-34.
[10]L.V. Agostini, I.S. Silva, S. Bampi. Pipelined fast 2d DCT architecture for JPEG image compression. In Integrated Circuits and Systems Design, 2001, 14th Symposium on Pirenopolis, Brazil, 2001.226-231
[11]K. Z. Bukhari, G.K. Kuzmanov, S. Vassiliadis. Dct and idct implementations on different fpga technologies. In Proceedings of ProRISC 2002, November2002 .232-235
[12]Antonino Tumeo et al. A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs.IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07)
[13]陈衡,侯善敬.电力设备故障红外诊断(第一版)[M].北京:中国电力出版社,1999:58-100
[14]陆家兵,鲍晓静,唐建博.基于PCI总线的视频图像采集系统设计与实现[J].计算机测量与控制,2004,12(11):1110-1112.
[15]Geoffray , Herve , Guerin , et al. Measured performance of a low2cost thermal infrared pushbroom camera based on uncooled microbolometer FPA for space applications. Proc. SPIE , 2001 , 4540(1):298-308
[16]朱勇.调色板在热象中的应用[J].自动化仪表,2001,22 (3):28-29
[17]朱勇.用OpenGL实现红外图像伪彩色处理[J].微计算机信息,2002,18(9):51-56
[18]Yong Zhu,JiangLing Zhang. The infrared video image pseudocolor processing system. SPIE. APPL OF DIGITAL IMAGE PROCESSING XXVI Vol. 5203,2003,11
[19]Yong Zhu,JiangLing Zhang. The implementation of thermal image visualization by HDL based on pseudo color. SPIE. Applications of Digital Image Processing XXVII Vol. 5558,2004,11
[20]XIE H et al. SAR speckle reduction using wavelet denoising and Markov random field modeling[J]. IEEE Trans. Geosci. Remote Sens. , 2002 , 40 (10) :2196-2212
[21]G.Pajares, J M Cruz. A. wavelet based image fusion tutorial[J]. Pattern Recognition ,2004 ,37 (9) :1855-1872
[22] G Piella. A general framework for multiresolution image fusion :from pixels to regions[J]. Information Fusion ,2003 ,4 (4) :259-280
[23] M N Do, M Vetterli Contourlets , G V Welland. Beyond Wavelets. New York :Academic Press ,2003.
[24] M N Do ,M Vetterli. The contourlet transform : an efficient directional multiresolution image representation[J]. IEEE Transactions on Image Processing ,2005 ,14 (12) :2091-2106
[25]朱勇.基于SoC的红外图像系统数据通道设计.2005年全国单片机与嵌入式系统学术交流会论文集,2005,335-339
[26]朱勇.红外热象数字处理系统[J].仪表技术与传感器,2001,13(9):13-15
[27] HARRIS J G, CHIANG Yu Ming. Nonuniformity correction of infrared image sequences using the constant statistics constraint. IEEE Transactions on Image Processing, 1999, 8(8) :1148-1151.
[28]陈立法等.基于PCI总线的实时红外图像采集处理系统.红外技术,2001,23(5):4-8
[29] Chih-Chin lai, Chuan-Yu chang. A hierarchical genetic algorithm based approach for image segmentation. Networking, Sensing and Control, 2004 IEEE International Conference on, 2004(2) :1284-1288.
[30]邱翰,桑农,李立.基于NiosII的红外图像处理系统设计[J].微电子学,2006,32(6):241-244
[31]孔令彬,王川,许鸿文,戚建汉.基于Nios红外图像实时非均匀性校正研究.华中科技大学学报,2005,33(12):70-72
[32]贺明,王新赛.基于Nios软核的实时红外图像自动跟踪系统设计.红外技术,2007,29(1):34-37
[33] Nobuyuki Ohba,Kohji Takano. An SoC Design Methodology Using FPGAs and Embedded Microprocessors. Proceedings of the 41st Design Automation Conference (DAC’04) .747-752
[34] FENNER J W, SCRIBNER D A. Design of IRFPA nonuniformity correction algorithm to be implemented as a real-time hardware prototype. SPIE,1994,v2225 . 350-359
[35] Vicker V E. Plateau equalization algorithm for real time display of high- quality infrared imagery[J]. Opt Eng,1996, 35 (7) :1821-1826.
[36]王波,吴新建.基于NiosII的红外图像灰度变换系统设计[J].光学与光电技术,2007,5(2):45-51.
[37] iroyuki Tomiyama et al. Architecture Description Language for System-on-Chip Design. http://www.cecs.uci.edu/~aces
[38] George Hadjiyiannis, Silvina Hanono, Srinivas Devadas. IDSL An Instruction Set Description Language for Retargetability. Design Automation Conference,1997
[39] Oliver Schliebusch et al. Architecture Implementation Using the Machine Description Language LISA. Proceedings of the 15th International Conference on VLSI Design (VLSID.02)
[40] Lu L, Li X, Xiong Y et al. XML-ADL, an extensible markup architecture description language. ASIC/SOC Conference, 15th Annual IEEE International, 2002
[41]杨君.专用指令集处理器(ASIP)体系结构设计研究[J].中国科学技术大学博士论文,2006,28(10):1572-1577.
[42] ZHU Yong. The Specification of the Embedded System of Real-time IR. DCABES2007
[43] Schulz M et al. Nonuniformity correction and correctability of infrared focal plane arrays[J]. INFRARED PHYSICS&TECHNOLOGY,1995,2470(36): 763-777.
[44] Harris J G et al. Nonuniformity correction using the constant-ststistics constraint : analog and digital implementations[J]. SPIE,1997, 3061(1):895-905.
[45] Li Xiying. Real-time image histogram equalization using FPGA[J]. SPIE,1998,3561(1):293-299.
[46] Chang D. C. ,Wu W R. Image contrast enhancement based on a histogram transformation of local standard deviation[J]. IEEE TransMedical Imaging , 1998 , 17 (4):518-531.
[47] Kya BERTHE,Yang YANG. Automatic edge and target extraction base on Pulse-Couple Neuron Networks Wavelet theory (PCNNW)[J]. SPIE, 2002 , 4668(1):504-509.
[48] Tzannes A P , Brooks D H. Detecting Small Moving Objects Using Temporal Hypothesis Testing[J]. IEEE Trans on Aerospace and Electronic System , 2002 , 38(2):570-586.
[49] Shimonomuar K,Kameda S,Yagi T. Silicon Retina System Applicable to Robot Vision[J]. Proceedings of the 2002 International Joint Conference on Neural Networks : Vol 3[C],. Madrid : UAM, 2002.2276-2281.
[50] Li S T , Kwok J T , Wang Y N. Using the discrete wavelet frametransform to merge Landsat TM and SPOT panchromatic images. Elsevier Science, Information Fusion, 2002 .17-23
[51] L. Tao and V. K. Asari. An Adaptive and Integrated Neighborhood Dependent Approach for Nonlinear Enhancement of Color Images. SPIE, Journal of Electronic Imaging, 2005,14(4):2216-2548
[52] Li Tao et al. Multi-sensor Image Fusion and Enhancement System for Assisting Drivers in Poor Lighting Conditions. Proceedings of the 34th Applied Imagery and Pattern Recognition Workshop (AIPR05)
[53] Michelle Tomkinson, Brian Teaney, Jeffrey Olson. Dual Band Sensor Fusion for Urban Target Acquisition[J]. Proceedings of SPIE, 2005, 5784(1):27-34
[54] SAA7113H_2. 9-bit video input processor. www.nxp.com/acrobat_download/ datasheets/SAA7113H_2.pdf
[55] Thermal-Eye 3600AS Integration Guide. http://www.thermal-eye.com/Upload/files/ manuals/36-45Integration%20Guide.pdf
[56] Thermal-Eye 3600AS Expansion Port Supplement. http://www.thermal-eye.com/ Upload/files/manuals/36-45Expansion%20Port%20Supplement1.pdf
[57] SCC500? Specifications. http://www.eis.na.baesystems.com/brochures/ pdfs/iis_04 _a09.pdf
[58]朱勇.CPLD显示存储器共享技术[J].电测与仪表,1999,36(7):51-53.
[59] K. Ryu, E. Shin, V. Mooney. A Comparison of Five Different Multiprocessor SoC Bus Architectures. Proceedings of the EUROMICRO Symposium on Digital Systems Design (EUROMICRO' 01), pp202~209, September 2001
[60]朱勇.PC/104总线嵌入式工控计算机系统[J].计算机应用研究,1996,13(6):94-95
[61] Tom Shanley, Don Anderson.刘晖等译. PCI系统结构(第四版)[M].北京:电子工业出版社,2000:1-30
[62]徐江丰等.基于Wishbone-PCI Bridge核的红外图像高速采集系统[J].红外与激光工程,2006,35(6):713-716.
[63] PCI 9054 Data Book. http://www1.plxtech.com/TEMP/82475/9054db-21.pdf
[64] Kanungo T,MountD M,Netanyahu N S. An efficient K-means clustering algorithm: analysis and imp lamentation[J]. IEEE trans. PAM I,2002,24 (7):881-892.
[65]陈国群,付冬梅,常晓辉.基于聚类算法的红外图像伪彩色增强[J].激光与红外,2007, 37(4):384-388.
[66]张文峦,梁敏,李言俊.一种改进的伪彩色图像融合方法[J].探测与控制学报,2007, 29(1):48-51.
[67]黄光华,倪国强,张彬.基于Land实验的可见红外伪彩色图像融合方法[J].光学技术,2007,33(1):98-101.
[68] Lu Yuanlin, Wang Zhigong, Qiao Lufeng, er al. Design and Implementation of Multi-channel High Speed HDLC Data Processor. 2002 International Conference on Communications Circuits and Systems and West Sino Expositions Proceedings LC, Chengdu, China: UESTC Press, 2002. 1471-1475
[69]朱勇,张江陵.RAID高速通道IP设计[J].计算机工程,2003, 29(6):153-154,157.
[70]朱勇,张江陵.RAID光纤通道适配器设计[J].计算机工程与应用,2002,38(14):17-18.
[71] Custom Instructions for the Nios Embedded Processor. http://www.altera.com.cn/ literature/an/an188.pdf
[72] Nios Custom Instructions Tutorial. http://www.altera.com.cn/literature/ tt/tt_nios_ ci.pdf
[73] Avalon Switch Fabric Features. http://www.altera.com.cn/products/software/ products/sopc/avalon/nio-avalon_features.html#figure1
[74] Avalon Interface Specification. http://www.altera.com/literature/manual/ mnl_avalon_ spec.pdf
[75]徐宁仪,周祖成.Avalon总线与SOPC系统架构实例[J].半导体技术,2003, 24(6):17-20.
[76] Frank Engel et al. An Open GNSS Receiver Platform Architecture. The 2004 International Symposium on GNSS/GPS,Sydney, Australia 6–8 December 2004
[77]朱勇.在屏显示器件MC141541及其接口技术[J].国外电子元器件,2002, 18(3) :18-20.
[78] Daniel等著.边计年等译.嵌入式系统的描述与设计(第一版)[M].北京:机械工业出版社,2005:35
[79]朱勇.基于三层逻辑的VIA设计[J].广西师范大学学报,2005,23(1):42-45.
[80]王晓光,冯耀东,梅宏.ABC/ADL:一种基于XML的软件体系结构描述语言[J].计算机研究与发展,2004, 41(6):1521-1531.
[81] Zhang Guangquan. Describing Software Architecture Style with XYZ/E. Proc. Of the 5th Inter. For Young Comp. Sci. International Academic Pblisher,ICYCS-2003 2003,8. 171-174
[82]张广泉,戎玫,陈琳琳.UML与软件体系结构描述语言之间的转换机制研究[J].计算机科学,2007 ,134(6):262-269.
[83] Bruce Power Douglass著.柳翔等译.嵌入式与实时系统开发–实用UML、对象技术、框架与模式[M].北京:机械工业出版社,2005:187-200
[84]林闯.随机Petri网和系统性能评价(第1版)[M].北京:清华大学出版社,2000:1-2
[85] Zhan JY et al. Formal co-verification for SoC design with colored Petri net. eds. Proc. of the ICESS 2004. LNCS 3605, Berlin: Springer-Verlag, 2005. 188-195
[86] Blume H, von Sydow T, Noll TG. Performance analysis of SoC communication by application of deterministic and stochastic Petri nets. In: Pimentel A, Vassiliadis S, eds. Proc. of the SAMOS 2004. LNCS 3133, Berlin: Springer-Verlag, 2004. 484-493
[87]余金山等.基于扩展层次有色Petri网创建SoC高层可执行规约[J].Journal of Software, 2006, 17(11):148-153.
[88]朱赟.基于Petri网的ASIP体系结构形式化建模方法研究[J].小型微型计算机系统,2006, 27(9):1722-1725.
[89]赵不贿等.Petri网的硬件实现[J].软件学报,2002,13(8):1652-1657.
[90] Yakovlev, A., Goes, L., Lavagno, L. Hardware Design and Petri Nets[J]. Boston: Kluwer Academic Publishers, 2000,1806(3):1553-1562.
[91]朱勇,张江陵.基于文件管理系统的扩展存储体高速通道.中国国际存储技术大会论文集, 2002:5
[92]刘仁峰等.一个嵌入式系统的Petri网模型与CPLD实现[J].电子技术应用,2003, 29(9):51-53.
[93]陈林,黄建文.基于SystemC的系统级设计方法[J].计算机应用研究,2003,20(9):113-115.
[94] T. Groetker, S. Liao, G. Martin, S. Swan. System Design with SystemC[M]. Kluwer Academic Publishers, 2002:50-80
[95] L. Cai, D. Gajski. C/C++ Based System Design Flow Using SpecC, VCC and SystemC. CECS Technical Report 02-30, UC Irvine, CA, 2002
[96] D.D. Gajski, J. Zhu, R. Doemer, A. Gerstlauer, and S. Zhao. SpecC: Specification Language and Methodology[M]. Kluwer Academic Publishers, 2000:46-89
[97] A. Gerstlauer, R. Doemer, J. Peng, D.D. Gajski. System Design: A Practical Guide with SpecC[M]. Kluwer Academic Publishers, 2001:36-68
[98] E. B?rger and R. St?rk. Abstract State Machines: A Method for High-Level System Design and Analysis. Springer Verlag, 2003
[99] M. Edwards and P. Green. UML for hardware and software object modeling. UML for real design of embedded real-time systems, 2003:127-147
[100] E. Riccobene, P. Scandurra, A. Rosti, and S. Bocchio. A Model-driven Co-design Flow for Embedded Systems. In FDL’06: Proceedings of Forum on Specification and Design Languages, 2006.