异构并行计算机容错技术研究
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摘要
并行计算是实现超高性能计算的主要技术手段。当前,随着GPGPU性能的不断提高,利用CPU和GPU构建的异构并行系统已经成为高性能计算机领域的研究热点。然而随着并行计算系统规模的不断增长,高性能计算机面临严峻的挑战。由于异构并行系统更为复杂的体系结构以及其特有的性质,且商用GPGPU容错能力较弱,所以由CPU和GPU构建的大规模异构并行系统的可靠性问题更为尖锐,尚缺乏实用的容错手段。
本文针对异构并行计算机的容错技术展开研究,以异构并行系统硬件故障在软件中的传播行为为理论基础,对应用级checkpointing技术的保存数据量优化问题进行研究;分析了异构并行系统多checkpoint的全局开销最优化问题,并提出了设置方案;同时,针对异构并行系统提出了一种新的面向GPU的多副本容错技术RB-TMR,并对其所具备的关键机制进行了详细的研究与设计实现。本文的主要贡献如下:
1、提出了一种面向一般计算系统的计算可接受模型。建立程序的执行结果可接受以及可接受度的定义,并进一步定义程序多次执行的可接受和多次执行的可接受度,以此为基础得到可接受度的相关定理和推论。针对异构并行系统将可接受度的相关定理和推论进行了扩展,并建立异构并行系统的可接受模型,同时进一步案例分析两种常见的容错技术checkpoint/restart和TMR应用到异构并行系统上时,对可接受模型的影响,从而给出容错机制的指导意见和优化方法。
2、基于过程间相关性理论,提出了由CPU和GPU构成的异构并行系统中硬件故障在软件中传播行为描述方法,我们称其为故障传播模型。同时,根据故障传播模型,设计了针对该系统的checkpointing机制,并针对影响checkpoint/restart开销的主要问题之一——checkpoint保存数据量进行了优化。实验证明该优化方法可以有效的减小开销,提高容错性能。
3、深入研究了面向异构并行系统的多个checkpoint的全局开销最小化问题,提出了面向异构并行系统的同步及异步两种机制的多checkpoint全局开销最小化的优化设置方法。首先提出了两个针对优化设置多个checkpoint位置的基本问题。然后通过对异构并行系统体系结构和程序特性的分析,提出了基于两种机制的异构并行系统的多checkpoint设置方法:同步及异步机制的checkpoint设置方法。同时,根据checkpoint优化设置的两个具体问题分别对这两种机制进行优化设置分析和数学建模,并给出了相应的求解算法。
4、提出了一种回滚机制与TMR技术相结合的容错技术RB-TMR。这一技术可以有效应对fail-stop故障与瞬时故障两种类型的故障进行容错,我们给出了这一技术的实现方法,并针对异构并行系统体系结构及程序模型的特征对其中关键机制的设计进行了具体分析和讨论。同时,设计并实现了一个面向RB-TMR机制的源到源编译辅助工具,可以辅助用户面向CUDA程序完成RB-TMR机制的实现,减轻了用户实现RB-TMR机制的负担。实验结果表明RB-TMR技术能够实现较高的错误检出和纠正率,有效减小可能需要回滚恢复的概率,根据综合评定,其相对于传统checkpointing及TMR技术有更好的容错性能。
Parallel computing is a major ultra-high-performance computing technology. As the performance of GPGPU (General Purpose computation on Graphic Processing Units) keeps improving, heterogeneous parallel systems built based on CPU and GPU become a hot research field of high-performance computers. However, with the increase of the parallel computing system size, high-performance computers encounter serious challenges. Due to more complicated architecture and unique features of heterogeneous parallel systems and weak fault-tolerance of GPGPU, large scale heterogeneous parallel systems built based on CPU and GPU undergoes an acute reliability issue, which is lack of practical means.
This paper studies the fault-tolerance technique of heterogeneous parallel systems. Based on the propagation behaviors of hardware error that propagates in software in heterogeneous parallel systems, this paper optimizes checkpoint size of application-level checkpointing, optimizes the global overhead of multiple checkpoints in heterogeneous parallel systems and proposes configuration solution, and explores a GPU-oriented multi-copies fault tolerance technique (RB-TMR). The main contributions of the paper are summarized as follows:
1. A general computer oriented acceptance model is proposed. The acceptance and its degree of program results and multiple times of program execution are first defined. Based on them, theorems and corollaries regarding acceptance degree are obtained. This paper extends the theorems and corollaries in heterogeneous parallel systems and establishes the acceptance model of heterogeneous parallel systems. Cases are used to analyze the effect of two common fault-tolerance techniques (checkpoint/restart and TMR) on the acceptance model when the two techniques are applied in heterogeneous parallel systems. Therefore, constructive suggestions and optimization methods for fault-tolerance mechanism are obtained.
2. Based on the theory about inter-procedural dependence, a method named error propagation model is proposed. It describes the prorogation behavior of hardware error in software in CPU-GPU heterogeneous parallel systems. Using this model, the system’s checkpointing mechanism is designed and the checkpoint size is optimized. Experimental results show that this method can effectively reduce the overhead and improve the fault tolerance performance.
3. In order to minimize the global overhead of multiple checkpoints, this paper proposes a placement optimization method for both synchronization and asynchronization mechanisms in heterogeneous parallel systems. First of all, two essential issues of placement optimization of multiple checkpoint locations are proposed. Secondly, based on the analysis of architecture and program features, two methods of checkpoint placement in heterogeneous parallel systems are proposed: synchronous checkpoint placement and asynchronous checkpoint placement). Further, for the two issues, the two methods are analyzed and modeled and their solution algorithms are given.
4. A fault-tolerance technique (RB-TMR) combining rollback mechanism and TMR technique is proposed. It can effectively offer fault-tolerance for fail-stop fault and transient fault. We implement this technique according to architecture and program features of heterogeneous parallel systems. Besides, a source-to-source compile assistant tool is designed for the RB-TMR technique. The tool can assist users in implementing the RB-TMR technique in CUDA programs, alleviating their burdens. Experimental results exhibit that the RB-TMR technique can achieve high error checking and correction rate as well as decreases the probability of rollback. It is concluded that the RB-TMR technique demonstrates better fault-tolerance performance than the conventional checkpointing and TMR technique.
本文针对异构并行计算机的容错技术展开研究,以异构并行系统硬件故障在软件中的传播行为为理论基础,对应用级checkpointing技术的保存数据量优化问题进行研究;分析了异构并行系统多checkpoint的全局开销最优化问题,并提出了设置方案;同时,针对异构并行系统提出了一种新的面向GPU的多副本容错技术RB-TMR,并对其所具备的关键机制进行了详细的研究与设计实现。本文的主要贡献如下:
1、提出了一种面向一般计算系统的计算可接受模型。建立程序的执行结果可接受以及可接受度的定义,并进一步定义程序多次执行的可接受和多次执行的可接受度,以此为基础得到可接受度的相关定理和推论。针对异构并行系统将可接受度的相关定理和推论进行了扩展,并建立异构并行系统的可接受模型,同时进一步案例分析两种常见的容错技术checkpoint/restart和TMR应用到异构并行系统上时,对可接受模型的影响,从而给出容错机制的指导意见和优化方法。
2、基于过程间相关性理论,提出了由CPU和GPU构成的异构并行系统中硬件故障在软件中传播行为描述方法,我们称其为故障传播模型。同时,根据故障传播模型,设计了针对该系统的checkpointing机制,并针对影响checkpoint/restart开销的主要问题之一——checkpoint保存数据量进行了优化。实验证明该优化方法可以有效的减小开销,提高容错性能。
3、深入研究了面向异构并行系统的多个checkpoint的全局开销最小化问题,提出了面向异构并行系统的同步及异步两种机制的多checkpoint全局开销最小化的优化设置方法。首先提出了两个针对优化设置多个checkpoint位置的基本问题。然后通过对异构并行系统体系结构和程序特性的分析,提出了基于两种机制的异构并行系统的多checkpoint设置方法:同步及异步机制的checkpoint设置方法。同时,根据checkpoint优化设置的两个具体问题分别对这两种机制进行优化设置分析和数学建模,并给出了相应的求解算法。
4、提出了一种回滚机制与TMR技术相结合的容错技术RB-TMR。这一技术可以有效应对fail-stop故障与瞬时故障两种类型的故障进行容错,我们给出了这一技术的实现方法,并针对异构并行系统体系结构及程序模型的特征对其中关键机制的设计进行了具体分析和讨论。同时,设计并实现了一个面向RB-TMR机制的源到源编译辅助工具,可以辅助用户面向CUDA程序完成RB-TMR机制的实现,减轻了用户实现RB-TMR机制的负担。实验结果表明RB-TMR技术能够实现较高的错误检出和纠正率,有效减小可能需要回滚恢复的概率,根据综合评定,其相对于传统checkpointing及TMR技术有更好的容错性能。
Parallel computing is a major ultra-high-performance computing technology. As the performance of GPGPU (General Purpose computation on Graphic Processing Units) keeps improving, heterogeneous parallel systems built based on CPU and GPU become a hot research field of high-performance computers. However, with the increase of the parallel computing system size, high-performance computers encounter serious challenges. Due to more complicated architecture and unique features of heterogeneous parallel systems and weak fault-tolerance of GPGPU, large scale heterogeneous parallel systems built based on CPU and GPU undergoes an acute reliability issue, which is lack of practical means.
This paper studies the fault-tolerance technique of heterogeneous parallel systems. Based on the propagation behaviors of hardware error that propagates in software in heterogeneous parallel systems, this paper optimizes checkpoint size of application-level checkpointing, optimizes the global overhead of multiple checkpoints in heterogeneous parallel systems and proposes configuration solution, and explores a GPU-oriented multi-copies fault tolerance technique (RB-TMR). The main contributions of the paper are summarized as follows:
1. A general computer oriented acceptance model is proposed. The acceptance and its degree of program results and multiple times of program execution are first defined. Based on them, theorems and corollaries regarding acceptance degree are obtained. This paper extends the theorems and corollaries in heterogeneous parallel systems and establishes the acceptance model of heterogeneous parallel systems. Cases are used to analyze the effect of two common fault-tolerance techniques (checkpoint/restart and TMR) on the acceptance model when the two techniques are applied in heterogeneous parallel systems. Therefore, constructive suggestions and optimization methods for fault-tolerance mechanism are obtained.
2. Based on the theory about inter-procedural dependence, a method named error propagation model is proposed. It describes the prorogation behavior of hardware error in software in CPU-GPU heterogeneous parallel systems. Using this model, the system’s checkpointing mechanism is designed and the checkpoint size is optimized. Experimental results show that this method can effectively reduce the overhead and improve the fault tolerance performance.
3. In order to minimize the global overhead of multiple checkpoints, this paper proposes a placement optimization method for both synchronization and asynchronization mechanisms in heterogeneous parallel systems. First of all, two essential issues of placement optimization of multiple checkpoint locations are proposed. Secondly, based on the analysis of architecture and program features, two methods of checkpoint placement in heterogeneous parallel systems are proposed: synchronous checkpoint placement and asynchronous checkpoint placement). Further, for the two issues, the two methods are analyzed and modeled and their solution algorithms are given.
4. A fault-tolerance technique (RB-TMR) combining rollback mechanism and TMR technique is proposed. It can effectively offer fault-tolerance for fail-stop fault and transient fault. We implement this technique according to architecture and program features of heterogeneous parallel systems. Besides, a source-to-source compile assistant tool is designed for the RB-TMR technique. The tool can assist users in implementing the RB-TMR technique in CUDA programs, alleviating their burdens. Experimental results exhibit that the RB-TMR technique can achieve high error checking and correction rate as well as decreases the probability of rollback. It is concluded that the RB-TMR technique demonstrates better fault-tolerance performance than the conventional checkpointing and TMR technique.
引文
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