分栅型闪存中浮栅氮化物硬掩膜层蚀刻工艺的优化
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摘要
三栅分栅型闪存的浮栅层末梢尖端高度决定了器件在擦除时F-N隧穿电流的大小,过低的尖端高度会使电场强度过低,从而出现器件擦除电流过小,导致擦除时间过长的情况。浮栅层末梢尖端的形成与氮化物硬掩膜蚀刻后的剖面有直接关系。
蚀刻氮化物硬掩膜时,等离子体中的CFx基团会在硬掩膜的侧壁生成一层聚合物,从而阻碍硬掩膜侧壁横向刻蚀的进行。CF2是生成这个聚合物的主要前驱物,等离子气体中CF2基团浓度变化会导致最终刻蚀特性的变化。当等离子体中的CF2减小时,淀积在硬掩膜侧壁上的聚合物随之减小,因此横向同性刻蚀得到加强,横向蚀刻的量越多。
本文通过实验证明:高C/F比和较高的刻蚀腔压力有利于聚合物的产生;O2的加入会有效抑制聚合物的产生,而磁场的加入对于侧壁聚合物的影响不明显。
The floating gate tip of split gate flash memory determines the F-N tunneling current thus impact the erase time significantly. Lower tip will lead to“tail bits”whose erase time is too long. The formation of tip has strong relationship with the vertical profile.
CFX will bring polymer to the sidewall when etching nitride hard mask, therefore blocking the transverse etch.CF2 is the premonitory of the polymer and the fluctuation of its concentration in the plasma will lead to the etching character. The polymer deposit on the side wall will decrease together with the CF2 trend down. Thus the transverse etch will be enhanced.
This paper proved the below theory by 4 experiments: higher C/F ratio and chamber pressure will have positive effect on the polymer deposition while O2 has the negative effect, and the magnet field does not show obvious impact.
蚀刻氮化物硬掩膜时,等离子体中的CFx基团会在硬掩膜的侧壁生成一层聚合物,从而阻碍硬掩膜侧壁横向刻蚀的进行。CF2是生成这个聚合物的主要前驱物,等离子气体中CF2基团浓度变化会导致最终刻蚀特性的变化。当等离子体中的CF2减小时,淀积在硬掩膜侧壁上的聚合物随之减小,因此横向同性刻蚀得到加强,横向蚀刻的量越多。
本文通过实验证明:高C/F比和较高的刻蚀腔压力有利于聚合物的产生;O2的加入会有效抑制聚合物的产生,而磁场的加入对于侧壁聚合物的影响不明显。
The floating gate tip of split gate flash memory determines the F-N tunneling current thus impact the erase time significantly. Lower tip will lead to“tail bits”whose erase time is too long. The formation of tip has strong relationship with the vertical profile.
CFX will bring polymer to the sidewall when etching nitride hard mask, therefore blocking the transverse etch.CF2 is the premonitory of the polymer and the fluctuation of its concentration in the plasma will lead to the etching character. The polymer deposit on the side wall will decrease together with the CF2 trend down. Thus the transverse etch will be enhanced.
This paper proved the below theory by 4 experiments: higher C/F ratio and chamber pressure will have positive effect on the polymer deposition while O2 has the negative effect, and the magnet field does not show obvious impact.
引文
[1] D.Kahng and S.M.Sze,―A floating gate and its application to memory devices,”IEEE Trans. Electron Devices, 1967 (14): 629-629
[2] H.A.R.Wegener, A.J.Lincoln, H.C.Pao, M.R.O'Connell, and R.E.Oleksiak,―The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,”IEEE IEDM Tech. Dig., Washington D.C., 1967
[3] Masuoka F, Asano M, Iwahashi H, et al,―A 256-K bit Flash E2PROM using triple-polysilicon technology,”J.Soid-State Circuits, 1987 (22): 548-552
[4] M. Lenzinger and E. H. Snow,― Fowler-Nordheim Tunneling into Thermally Grown SiO2,”Journal of Applied Physics, 1969: 278
[5] R. Klein, W. Owen, et al.,―5-V-Only, Nonvolatile RAM Owes It All to Polysilicon,”Electronics, 1979 : 111
[6] B. Rossler and R. Muller,― Electrically Erasable and Reprogrammable Read-only Memory Using the N-Channel SIMOS One-Transistor Cell,”IEEE Transactions on Electron Devices, 1977 (24): 806
[7] M. Kamiya, et al.,―EPROM Cell with High Gate Injection Efficiency,”IEEE IEDM Technical Digest, 1981: 741
[8] N. Tsuji, et al.,―New Erase Scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Enhance Characteristics,”IEEE IEDM Technical Digest, 1994: 53
[9] R. H.Fowler and L. Nordheim,―Electron Emission in Intense Electric Fields,“Proceedings of Royal Society, London, Series A, 1928 (119): 173
[10] P.E. Cottrell, P.R. Troutman, and T.H. Ning,―Hot Electron Emission in n-Channel IGFET’s,”IEEE J. Solid-State Circuits, 1979(SC-14):442
[11] B.Eitan and D. Frohman-Bentchkowsky,―Hot Electron Injection into the Oxide in n-Channel MOS-Devices,”IEEE Trans. Electron Devices, 1981(ED-28):328
[12]蒋维楠,等离子蚀刻,半导体国际,2004:1-7
[13]刘万东,等离子体物理导论,中国科学技术大学近代物理系,2002:1-6
[14] James D. Plummer, Michael D. Deal, Peter B. Griffin,硅超大规模集成电路工艺技术,王玉东,熊小义,电子工业出版,2005:453-498
[15]任伟,电介质蚀刻工艺简介,应用材料(中国)有限公司,2007:1-5
[16]虞一青,辛煜,宁兆元,碳氟感应耦合等离子体的SiO2介质蚀刻的研究,真空科学与技术学报,2007,26(2),146-150
[17] Study for plasma etching of dielectric film in semiconductor device manufacturing. Pure Appl. Chem., Vol. 74, No. 3, pp. 381–395, 2002
[18]孙承龙,戈肖鸿,王渭源等,反应离子深蚀刻(RIE)技术的研究,传感器世界,1996(5):31-3
[19] Keri L. Williams, Carmen I. Butoi, and Ellen R. Fisher,Mechanisms for deposition and etching in fluorosilane plasma processing of silicon,2003:1-6, USA
[20] Dongping Liu, Jie Zhou, and Ellen R. Fisher, Correlation of gas-phase composition with film properties in the plasma-enhance, 2007:3-9, USA
[21] M. J. Sowa, M. E. Littau, V. Pohray, and J. L. Cecchi, Fluorocarbon polymer deposition kinetics in a low-pressure, high-density, inductively coupled plasma reactor,2003:5-7, USA
[22] Marcos J. Barela and Harold M. Anderson,Role of C2F4, CF2, and ions in C4F8+Ar plasma discharges under active oxide etch conditions in an inductively coupled GEC cell reactor, 2005, USA
[23] M.Schaepkens, T.E.F.M.Standaert, N.R.Rueger, P.G.M.Sebel, G.S.Oehrleinb, J.M.Cook, J.Vac. Study of the SiO2-to-Si3N4 etch selectivity mechanism in inductively coupled ?uorocarbon plasmas and a comparison with the SiO2-to-Si mechanism, Sci.Technol.A 17(1)1999
[24] Caleb Yu-Sheng Cho,et al.,―A Novel Self-Aligned Highly Reliable Sidewall Split-Gate Flash Memory,”IEEE Transactions On Electron Devices, 2006 (53): 465-473
[25] T.C.Ong, A.Fazio, N.Mielke, S.Pan, N.Righos, G.Atwood, and S.Lai,―Erratic erase in ETOX Flash memory array,”Symp. VLSI Tech. Dig., 1993: 83–84
[26] K.Naruke, S.Yamada, E.Obi, S.Taguchi, and M.Wasa,―A new Flash-erase EEPROM cell with a select-gate on its source side,”IEEE IEDM Tech. Dig., 1989: 603–606
[27] J.V.Houdt, G.Groeseneken, and H.E.Maes,―An analytical model for the optimization of source-side injection flash EEPROM devices,”IEEE Trans. Electron Devices, 1995 (42): 1314–1320
[28] Y.Ma, C.S.Pand, J.Pathak, S.C.Tsao, and C.F. Chang,―A novel high density contactless flash meory array using split-gate source-side injection cell for 5V-only application,“Symp. VLSI Tech. Dig. Tech. Papers, 1994 (5A): 49–50
[29] K.Chang, W.Chen, C.Swift, J.M.Higman, and W.M.Paulson,―A new SONOSmemory using source-side injection for programming,”IEEE Electron Device Lett., 1998 (19): 253–255
[30] A.T.Wu, T.-Y.Chan, PP.-K.Ko, and C.Hu,―A novel high-speed, 5-volt programming EPROM structure with source-side injection,”IEEE IEDM Tech. Dig., 1986:584–587
[31] L.Peters,―Gaining control over STI processes,”Semicond. Int., 2000: 74
[32] C.P.Chang, et al.,―A highly manufactureable corner rounding solution for 0.18-μm shallow trench isolation,”IEEE IEDM Tech. Dig., 1997: 661-664
[33] A.Chatterjee, et al.,―A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/ 0.18-μm CMOS technology & beyond,”IEEE IEDM Tech., 1996:829-832
[34]刘宝峰,李洪峰,金立国,半导体器件钝化层Si3N4薄膜的制备及特性研究,哈尔滨理工大学学报,2003,8(6):105-108
[35] Millard M. M. and Kay E., J. Electrochem. Soc, Difluorocarbene Emission Spectra from Fluorocarbon Plasmas and Its Relationship to Fluorocarbon Polymer Formation, 1982:9
[36] Standaert T E F M, Hedlund C, Joseph E A, et al. Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide [J]. J. Vac. Sci. Technol. A, 2004:53
[37] Millard M. M. and Kay E., J. Electrochem. Soc, Difluorocarbene Emission Spectra from Fluorocarbon Plasmas and Its Relationship to Fluorocarbon Polymer Formation, 1982, 129
[38] Barela M. J., Anderson H. M., Oehrlein G. S., Role of C2F4, CF2, and ions in C4F8/Ar plasma discharges under active oxide etch conditions in an inductively coupled GEC cell reactor. J. Vac. Sci. Technol. A, 2005, 23(3): 408
[39]郝慧娟,张玉林,卢文娟,二氧化硅的反应离子蚀刻,电子工业专用设备,2005(126):48-51
[40] Vivek K. Singh, Eric S. G Shaqfeh, James P. McVittie, Study of silicon etching in CF4+O2 plasmas to establish surface re-emission as the dominant transport mechanism, 1994, USA:1-10
[41]徐新艳,汪家友,杨银堂等,电子回旋共振CF4+O2等离子体中Si3N4蚀刻工艺研究,真空科学与技术,2003, 23(6):425-427
[42] Semiconductor Industry Association (SIA): International Technology Roadmap for Semiconductors (ITRS), online at http://public.itrs.net, ed. 2003
[43] K.Naruke, S. Taguchi, and M.Wada,―Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness,‖IEEE Electron Devices Meeting, Tech. Dig. 1988:424-7.
[2] H.A.R.Wegener, A.J.Lincoln, H.C.Pao, M.R.O'Connell, and R.E.Oleksiak,―The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device,”IEEE IEDM Tech. Dig., Washington D.C., 1967
[3] Masuoka F, Asano M, Iwahashi H, et al,―A 256-K bit Flash E2PROM using triple-polysilicon technology,”J.Soid-State Circuits, 1987 (22): 548-552
[4] M. Lenzinger and E. H. Snow,― Fowler-Nordheim Tunneling into Thermally Grown SiO2,”Journal of Applied Physics, 1969: 278
[5] R. Klein, W. Owen, et al.,―5-V-Only, Nonvolatile RAM Owes It All to Polysilicon,”Electronics, 1979 : 111
[6] B. Rossler and R. Muller,― Electrically Erasable and Reprogrammable Read-only Memory Using the N-Channel SIMOS One-Transistor Cell,”IEEE Transactions on Electron Devices, 1977 (24): 806
[7] M. Kamiya, et al.,―EPROM Cell with High Gate Injection Efficiency,”IEEE IEDM Technical Digest, 1981: 741
[8] N. Tsuji, et al.,―New Erase Scheme for DINOR Flash Memory Enhancing Erase/Write Cycling Enhance Characteristics,”IEEE IEDM Technical Digest, 1994: 53
[9] R. H.Fowler and L. Nordheim,―Electron Emission in Intense Electric Fields,“Proceedings of Royal Society, London, Series A, 1928 (119): 173
[10] P.E. Cottrell, P.R. Troutman, and T.H. Ning,―Hot Electron Emission in n-Channel IGFET’s,”IEEE J. Solid-State Circuits, 1979(SC-14):442
[11] B.Eitan and D. Frohman-Bentchkowsky,―Hot Electron Injection into the Oxide in n-Channel MOS-Devices,”IEEE Trans. Electron Devices, 1981(ED-28):328
[12]蒋维楠,等离子蚀刻,半导体国际,2004:1-7
[13]刘万东,等离子体物理导论,中国科学技术大学近代物理系,2002:1-6
[14] James D. Plummer, Michael D. Deal, Peter B. Griffin,硅超大规模集成电路工艺技术,王玉东,熊小义,电子工业出版,2005:453-498
[15]任伟,电介质蚀刻工艺简介,应用材料(中国)有限公司,2007:1-5
[16]虞一青,辛煜,宁兆元,碳氟感应耦合等离子体的SiO2介质蚀刻的研究,真空科学与技术学报,2007,26(2),146-150
[17] Study for plasma etching of dielectric film in semiconductor device manufacturing. Pure Appl. Chem., Vol. 74, No. 3, pp. 381–395, 2002
[18]孙承龙,戈肖鸿,王渭源等,反应离子深蚀刻(RIE)技术的研究,传感器世界,1996(5):31-3
[19] Keri L. Williams, Carmen I. Butoi, and Ellen R. Fisher,Mechanisms for deposition and etching in fluorosilane plasma processing of silicon,2003:1-6, USA
[20] Dongping Liu, Jie Zhou, and Ellen R. Fisher, Correlation of gas-phase composition with film properties in the plasma-enhance, 2007:3-9, USA
[21] M. J. Sowa, M. E. Littau, V. Pohray, and J. L. Cecchi, Fluorocarbon polymer deposition kinetics in a low-pressure, high-density, inductively coupled plasma reactor,2003:5-7, USA
[22] Marcos J. Barela and Harold M. Anderson,Role of C2F4, CF2, and ions in C4F8+Ar plasma discharges under active oxide etch conditions in an inductively coupled GEC cell reactor, 2005, USA
[23] M.Schaepkens, T.E.F.M.Standaert, N.R.Rueger, P.G.M.Sebel, G.S.Oehrleinb, J.M.Cook, J.Vac. Study of the SiO2-to-Si3N4 etch selectivity mechanism in inductively coupled ?uorocarbon plasmas and a comparison with the SiO2-to-Si mechanism, Sci.Technol.A 17(1)1999
[24] Caleb Yu-Sheng Cho,et al.,―A Novel Self-Aligned Highly Reliable Sidewall Split-Gate Flash Memory,”IEEE Transactions On Electron Devices, 2006 (53): 465-473
[25] T.C.Ong, A.Fazio, N.Mielke, S.Pan, N.Righos, G.Atwood, and S.Lai,―Erratic erase in ETOX Flash memory array,”Symp. VLSI Tech. Dig., 1993: 83–84
[26] K.Naruke, S.Yamada, E.Obi, S.Taguchi, and M.Wasa,―A new Flash-erase EEPROM cell with a select-gate on its source side,”IEEE IEDM Tech. Dig., 1989: 603–606
[27] J.V.Houdt, G.Groeseneken, and H.E.Maes,―An analytical model for the optimization of source-side injection flash EEPROM devices,”IEEE Trans. Electron Devices, 1995 (42): 1314–1320
[28] Y.Ma, C.S.Pand, J.Pathak, S.C.Tsao, and C.F. Chang,―A novel high density contactless flash meory array using split-gate source-side injection cell for 5V-only application,“Symp. VLSI Tech. Dig. Tech. Papers, 1994 (5A): 49–50
[29] K.Chang, W.Chen, C.Swift, J.M.Higman, and W.M.Paulson,―A new SONOSmemory using source-side injection for programming,”IEEE Electron Device Lett., 1998 (19): 253–255
[30] A.T.Wu, T.-Y.Chan, PP.-K.Ko, and C.Hu,―A novel high-speed, 5-volt programming EPROM structure with source-side injection,”IEEE IEDM Tech. Dig., 1986:584–587
[31] L.Peters,―Gaining control over STI processes,”Semicond. Int., 2000: 74
[32] C.P.Chang, et al.,―A highly manufactureable corner rounding solution for 0.18-μm shallow trench isolation,”IEEE IEDM Tech. Dig., 1997: 661-664
[33] A.Chatterjee, et al.,―A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/ 0.18-μm CMOS technology & beyond,”IEEE IEDM Tech., 1996:829-832
[34]刘宝峰,李洪峰,金立国,半导体器件钝化层Si3N4薄膜的制备及特性研究,哈尔滨理工大学学报,2003,8(6):105-108
[35] Millard M. M. and Kay E., J. Electrochem. Soc, Difluorocarbene Emission Spectra from Fluorocarbon Plasmas and Its Relationship to Fluorocarbon Polymer Formation, 1982:9
[36] Standaert T E F M, Hedlund C, Joseph E A, et al. Role of fluorocarbon film formation in the etching of silicon, silicon dioxide, silicon nitride, and amorphous hydrogenated silicon carbide [J]. J. Vac. Sci. Technol. A, 2004:53
[37] Millard M. M. and Kay E., J. Electrochem. Soc, Difluorocarbene Emission Spectra from Fluorocarbon Plasmas and Its Relationship to Fluorocarbon Polymer Formation, 1982, 129
[38] Barela M. J., Anderson H. M., Oehrlein G. S., Role of C2F4, CF2, and ions in C4F8/Ar plasma discharges under active oxide etch conditions in an inductively coupled GEC cell reactor. J. Vac. Sci. Technol. A, 2005, 23(3): 408
[39]郝慧娟,张玉林,卢文娟,二氧化硅的反应离子蚀刻,电子工业专用设备,2005(126):48-51
[40] Vivek K. Singh, Eric S. G Shaqfeh, James P. McVittie, Study of silicon etching in CF4+O2 plasmas to establish surface re-emission as the dominant transport mechanism, 1994, USA:1-10
[41]徐新艳,汪家友,杨银堂等,电子回旋共振CF4+O2等离子体中Si3N4蚀刻工艺研究,真空科学与技术,2003, 23(6):425-427
[42] Semiconductor Industry Association (SIA): International Technology Roadmap for Semiconductors (ITRS), online at http://public.itrs.net, ed. 2003
[43] K.Naruke, S. Taguchi, and M.Wada,―Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness,‖IEEE Electron Devices Meeting, Tech. Dig. 1988:424-7.