一种基于SiGeBiCMOS的高速采样/保持电路的设计
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摘要
A/D转换器是将模拟信号转换成数字信号的数据转换系统,是模拟世界与数字处理系统之间的接口。现代先进的电子系统中几乎都包含A/D转换器,以利用先进的数字处理技术使系统性能更高。所以A/D转换器的性能成为影响到系统性能好坏的关键因素。不断发展的无线通信技术对A/D转换器的指标要求越来越高,比较显著的是受通信高频化、数字化雷达、软件无线电等的推动,A/D转换器呈现出向高速方向发展的趋势。采样/保持电路位于A/D转换器的最前端,是对连续的模拟信号瞬时值进行采样并保持一定时间的电路,且由采样/保持电路引入的误差无法通过后级电路进行校正,所以其采样速率和精度决定了整个A/D转换器的速率和分辨率。由此可见,采样/保持电路是A/D转换器中最关键的模块,对它的研究也一直倍受关注。本文针对超高速A/D转换器设计了一种用于其前端的高速采样/保持电路。
本文首先介绍了超高速A/D转换器和高速采样/保持电路的发展和研究现状。接着概述了A/D转换器的基本原理和类型,并针对高速A/D转换器的常用结构进行了介绍和比较。然后着重介绍了采样/保持电路的设计过程:在比较了开环结构、闭环结构采样/保持电路的优缺点的基础上,根据设计指标的要求提出了一种开环全差分采样/保持电路结构,此结构由输入缓冲器、采样开关和输出缓冲器三个部分构成,每部分通过与其相同功能的其它结构进行比较分析后确定了最终的电路结构。其中由于采样开关(交换式射极跟随器——SEF)是电路获得高速性能的关键部分,所以对其工作原理及主要影响因素做了详细的分析。在最终电路中使用了前馈电容和伪开关的补偿结构,分别改善了保持模式馈通和基座误差这两个主要影响因素,使电路获得了良好的性能。电路设计完成后,进行了采样/保持电路的版图设计。
本设计基于SiGe BiCMOS工艺,该工艺提供了180nm的CMOS和75GHz fT的SiGe HBT。在Cadence Spectre环境下进行仿真,在1.6GSPS的采样速率下,当输入信号为775MHz,1Vpp的正弦波时(相干采样,每周期只采样2个点),该采样/保持电路的SFDR达到55.63dB,THD为-53.93dB,对应于8bits的分辨率。采用的电源电压为3.3V,此时功耗仅99mW。仿真结果证明该电路可以用于8bits 1.5GSPS的超高速ADC中。
A/D converters are data convert systems which convert analog signal to digital signal, they are the interface between analog world and digital world. Almost all modern electronic systems include A/D converters, so as to take advantage of advanced digital signal processing technology to achieve higher performance. Therefore, the performance of A/D converters becomes one of the key factors of whole system. The incessant progress of wireless communication technologies imposes more and more stress on the specifications of A/D converters, an obvious sample is that pushed by high frequency telecommunication, digital radar, soft radio etc, A/D converters show the develop trend of high speed. Sample-and-hold circuits are located on the most front-end of A/D converters, sampling the transient value of the continuous analog signal and holding that for intervals. Because the errors introduced by sample-and-hold circuits can not be corrected by back-end circuits, sample-and-hold circuits determining the whole A/D converters’speed and accuracy. Thus it can be seen, sample-and-hold circuits are the most critical block of A/D converters, and they are always drawn much special attentions. A high speed sample-and-hold circuit is designed in this article which will be used at the front-end of ultra high speed A/D converters.
At the beginning, the present state of developments and researches of ultra high speed A/D converters and high speed sample-and-hold circuits are introduced. Then the fundamental principles and types of A/D converters are summarized, besides this, the popular structures of ultra high speed A/D converters are introduced and compared. After that, the design of sample-and-hold circuit is emphasized: based on the comparison of the advantages and drawbacks between closed loop and open loop, and according to design specifications, a open loop differential sample-and-hold circuit is proposed. It contains three parts which are input buffer, sampling switch and output buffer. Each part was respectively compared with other structures which have the same function as the compared part, and the final structure of this subject is determined in this way. In the designed circuit, because sampling switch (switched emitter follower——SEF) is the critical part to achieve high speed performance, its fundamental principles and main drawbacks are analyzed in detail. Feedforward capacitors and dummy switches are used in the final designed circuit to respectively improve hold mode feed through and pedestal error these two main drawbacks. This leads the designed circuit to achieve good performance. After the schematic is finished, the layout of the circuit is designed.
The designed circuit is implemented in BiCMOS technology, this technology provides 180nm CMOS and 75GHz fT SiGe HBT. Simulate with Cadence Spectre, this sample-and-hold circuit achieves 55.63dB SFDR, -53.93dB THD and 8bits resolution for 1Vpp 775MHz sinusoidal input at 1.6GHz sampling rate (coherent sampling and 2 samples per period). Power consumption is 99mW from a 3.3V supply. Simulation results prove that the designed circuit can be used in 8bits 1.5GSPS ultra high speed A/D converters.
本文首先介绍了超高速A/D转换器和高速采样/保持电路的发展和研究现状。接着概述了A/D转换器的基本原理和类型,并针对高速A/D转换器的常用结构进行了介绍和比较。然后着重介绍了采样/保持电路的设计过程:在比较了开环结构、闭环结构采样/保持电路的优缺点的基础上,根据设计指标的要求提出了一种开环全差分采样/保持电路结构,此结构由输入缓冲器、采样开关和输出缓冲器三个部分构成,每部分通过与其相同功能的其它结构进行比较分析后确定了最终的电路结构。其中由于采样开关(交换式射极跟随器——SEF)是电路获得高速性能的关键部分,所以对其工作原理及主要影响因素做了详细的分析。在最终电路中使用了前馈电容和伪开关的补偿结构,分别改善了保持模式馈通和基座误差这两个主要影响因素,使电路获得了良好的性能。电路设计完成后,进行了采样/保持电路的版图设计。
本设计基于SiGe BiCMOS工艺,该工艺提供了180nm的CMOS和75GHz fT的SiGe HBT。在Cadence Spectre环境下进行仿真,在1.6GSPS的采样速率下,当输入信号为775MHz,1Vpp的正弦波时(相干采样,每周期只采样2个点),该采样/保持电路的SFDR达到55.63dB,THD为-53.93dB,对应于8bits的分辨率。采用的电源电压为3.3V,此时功耗仅99mW。仿真结果证明该电路可以用于8bits 1.5GSPS的超高速ADC中。
A/D converters are data convert systems which convert analog signal to digital signal, they are the interface between analog world and digital world. Almost all modern electronic systems include A/D converters, so as to take advantage of advanced digital signal processing technology to achieve higher performance. Therefore, the performance of A/D converters becomes one of the key factors of whole system. The incessant progress of wireless communication technologies imposes more and more stress on the specifications of A/D converters, an obvious sample is that pushed by high frequency telecommunication, digital radar, soft radio etc, A/D converters show the develop trend of high speed. Sample-and-hold circuits are located on the most front-end of A/D converters, sampling the transient value of the continuous analog signal and holding that for intervals. Because the errors introduced by sample-and-hold circuits can not be corrected by back-end circuits, sample-and-hold circuits determining the whole A/D converters’speed and accuracy. Thus it can be seen, sample-and-hold circuits are the most critical block of A/D converters, and they are always drawn much special attentions. A high speed sample-and-hold circuit is designed in this article which will be used at the front-end of ultra high speed A/D converters.
At the beginning, the present state of developments and researches of ultra high speed A/D converters and high speed sample-and-hold circuits are introduced. Then the fundamental principles and types of A/D converters are summarized, besides this, the popular structures of ultra high speed A/D converters are introduced and compared. After that, the design of sample-and-hold circuit is emphasized: based on the comparison of the advantages and drawbacks between closed loop and open loop, and according to design specifications, a open loop differential sample-and-hold circuit is proposed. It contains three parts which are input buffer, sampling switch and output buffer. Each part was respectively compared with other structures which have the same function as the compared part, and the final structure of this subject is determined in this way. In the designed circuit, because sampling switch (switched emitter follower——SEF) is the critical part to achieve high speed performance, its fundamental principles and main drawbacks are analyzed in detail. Feedforward capacitors and dummy switches are used in the final designed circuit to respectively improve hold mode feed through and pedestal error these two main drawbacks. This leads the designed circuit to achieve good performance. After the schematic is finished, the layout of the circuit is designed.
The designed circuit is implemented in BiCMOS technology, this technology provides 180nm CMOS and 75GHz fT SiGe HBT. Simulate with Cadence Spectre, this sample-and-hold circuit achieves 55.63dB SFDR, -53.93dB THD and 8bits resolution for 1Vpp 775MHz sinusoidal input at 1.6GHz sampling rate (coherent sampling and 2 samples per period). Power consumption is 99mW from a 3.3V supply. Simulation results prove that the designed circuit can be used in 8bits 1.5GSPS ultra high speed A/D converters.
引文
[1]徐世六.模拟/数字混合信号电路技术发展动态[J].微电子学.2008.38(1).26-33
[2] Y. Borokhovych, H. Gustat, B. Tillack, et al. A Low-Power, 10Gs/s Track-and-Hold Amplifier in SiGe BiCMOS Technology[C]. Proceedings of ESSCIRC. Grenoble, France. 2005. Piscataway, United States. IEEE. 2005. 263-266
[3] D. Smola, H. Ploeg, M. Vertregt, et al. An 8-bit, 4-Gsample/s Track-and-Hold in a 67GHz fT SiGe BiCMOS Technology[C]. Proceedings of ESSCIRC. Montreaux, Switzerland. 2006. Piscataway, United States. IEEE. 2006. 408-411
[4] F. Vessal, C.A.T. Salama. A Bipolar 2-GSample/s Track-and-Hold Amplifier (THA) in 0.35um SiGe Technology[C]. Proc IEEE Int Symp Circuits and Systems. Scottsdale, United States. 2002. United States. IEEE. 2002. 573-576
[5] Y. Lu, W.M. Kuo, X. Li, et al. An 8-bit, 12 GSample/sec SiGe Track-and-Hold Amplifier[C]. Proc Bipolar/BiCMOS Circuits and Technology Meeting. Atlanta, United States. 2005. United States. IEEE. 2005. 148-151
[6] B. Pregardier, U. Langmann, W. Hillery. A 1.2-GS/s 8-b Silicon Bipolar Track & Hold IC[J]. IEEE Journal of Solid-State Circuits. 1996. 31(9). 1336-1339
[7] J. Jensen, L. Larson. A Broadband 10-GHz Track-and-Hold in Si/SiGe HBT Technology[J]. IEEE Journal of Solid-State Circuits. 2001. 36(3). 325-330
[8] P.E. Allen著.冯军等译. CMOS模拟集成电路设计[M].第二版.北京.电子工业出版社. 2006. 501-583
[9] D. Dallet, J.M. da Silva. ADC的动态特性[M].第一版(影印版).北京.科学出版社. 2007. 85-92
[10] D.A. Johns, K. Martin著.曾朝阳等译.模拟集成电路设计[M].第一版.北京.机械工业出版社. 2005. 347-377
[11]杨银堂,朱樟明,朱臻.高速CMOS数据转换器[M].第一版.北京.科学出版社. 2006. 19-32
[12]薛亮,沈延钊,张向民.一种CMOS高速采样/保持放大器[J].微电子学. 2008. 34(3). 310-313
[13] Analog Devices Inc.. Data Conversion Handbook[M]. 1st edition. Norwood. NEWNES. 2004. 7.91-7.110
[14] National Semiconductor Corporation. An Introduction to the Sampling Theorem[Z]. Application Note 236. 2002. 1-6
[15]谢孟贤,古妮娜. SiGe半导体在微电子技术发展中的重要作用[J].微电子学. 2008. 38(1). 33-43
[16]徐世六著. SiGe微电子技术[M].北京.国防工业出版社. 2007. 201-230
[17]朱正涌著.半导体集成电路[M].北京.清华大学出版社. 2006. 11-14
[18] M. Sadollahy, K. Hadidi. A High-Speed Highly-Linear CMOS S/H Circuit[C]. ICCCE08. Kuala Lumpur, Malaysia. 2008. Kuala Lumpur, Malaysia. International Islamic University Malaysia. 2008. 550-553
[19] M. Nayebi, B.A. Wooley. A 10-Bit Video BiCMOS Track-and-Hold Amplifier[J]. IEEE Journal of Solid-State Circuits. 24(4). 1989. 1507-1516
[20] W. Xu, E.G. Friedman. A CMOS Miller Hold Capacitence Sample-and-Hold Circuit to Reduce Charge Sharing Effect and Clock Feedthrough[C]. ASIC/SOC Conference, 2002. 15th Annual IEEE International. New York, United States. 2002. New York, United States. IEEE. 2002. 92-96
[21]李伟华著. VLSI设计基础[M].北京.电子工业出版社. 2005. 148-164
[22] C. Fiocchi, U. Gatti, F. Maloberti. Design Issues on High-Speed High-Resolution Track-and-Holds in BiCMOS Technology[J]. IEE Proceedings Circuits, Devices & Systems. 2000. 147(2). 100-106
[23] P. Vorenkamp, J.P. Verdaasdonk. Fully Bipolar, 120-Msample/s 10-b Track-and-Told Circuit[J]. IEEE Journal of Solid-State Circuits. 1992. 27(7). 988-992
[24] Y. Lu. Design of High-Speed SiGe HBT Circuits for Wideband Transceivers[Dissertation]. Atlanta, United States. Georgia Institute of Technology. 2007. 44-58
[25] P.A. Quinn. Feed-Forward Amplifier[P]. United States. Utility. 4146844. Mar. 27, 1979. 1-3
[26] S. Simpkins, W. Gross. Cascomp Feedforward Error Correction in HighSpeed Amplifier Design[J]. IEEE Journal of Solid-State Circuits. 1983. 18(6). 762-764
[27] T. Miki, H. Kouno, T. Kumamoto, et al. A 10-b 50 MS/s 500-mW A/D Converter Using a Differential-Voltage Subconverter[J]. IEEE Journal of Solid-State Circtuts. 1994. 29(4). 516-522
[28] R. Caprio. Precision Differential Voltage-Current Converter[J]. Electronic Letters. 1973. 9(6). 147-148
[29] A.N. Karanicolas. A 2.7-V 300-MS/s Track-and-Hold Amplifier[J]. IEEE Journal of Solid-State Circuits. 1997. 32(12). 1961-1967
[30] B. Razavi著.陈贵灿等译.模拟CMOS集成电路设计[M].第一版.西安.西安交通大学出版社. 2005. 330-359
[31] A.M. Abo. Design for Reliability of Low-voltage, Switched-capacitor Circuit[Dissertation]. Berkeley, United States. UNIVERSITY of CALIFORNIA, Berkeley. 1999. 5-11
[32] B. Razavi. Design of Sample-and-Hold Amplifiers for High-Speed Low-Voltage A/D Converers[C]. CICC’97. Santa Clara, United States. 1997. New York, United States. IEEE. 1997. 59-66
[33] I. Sarkas, D. Mavridis, G. Papadopoulos. Volterra Analysis Using Chebyshev Series[C]. ISCAS. New Orleans, United States. 2007. New Orleans, United States. The Printing House. 2007. 1931-1934
[34] A. Helmy, K. Sharaf, H. Ragai. A Simplified Analytical Model for Nonlinear Distortion in RF Bipolar Circuit[C]. MWSCAS. Lansing, United States. 2000. Piscataway, United States. IEEE. 2000. 966-969
[35] P.R. Gray, P.J. Hurst, S.H. Lewis, et al.模拟集成电路的分析与设计[M].第四版(影印版).北京.高等教育出版社. 2005. 503-509
[36] G.Caiulo, C. Fiocchi, U. Gatti, et al. On the Design of High-Speed High-Resolution Track and Holds[C]. ISCAS. Atlanta, United States. 1996. Piscataway, United States. IEEE. 1996. 73-76
[37] F. Vessal, C.A.T. Salama. An 8-Bit 2-Gsample/s Folding-Interpolating Analog-to-Digital Converter in SiGe Technology[J]. IEEE Journal of Solid-State Circuits. 2004. 39(1). 238-241
[2] Y. Borokhovych, H. Gustat, B. Tillack, et al. A Low-Power, 10Gs/s Track-and-Hold Amplifier in SiGe BiCMOS Technology[C]. Proceedings of ESSCIRC. Grenoble, France. 2005. Piscataway, United States. IEEE. 2005. 263-266
[3] D. Smola, H. Ploeg, M. Vertregt, et al. An 8-bit, 4-Gsample/s Track-and-Hold in a 67GHz fT SiGe BiCMOS Technology[C]. Proceedings of ESSCIRC. Montreaux, Switzerland. 2006. Piscataway, United States. IEEE. 2006. 408-411
[4] F. Vessal, C.A.T. Salama. A Bipolar 2-GSample/s Track-and-Hold Amplifier (THA) in 0.35um SiGe Technology[C]. Proc IEEE Int Symp Circuits and Systems. Scottsdale, United States. 2002. United States. IEEE. 2002. 573-576
[5] Y. Lu, W.M. Kuo, X. Li, et al. An 8-bit, 12 GSample/sec SiGe Track-and-Hold Amplifier[C]. Proc Bipolar/BiCMOS Circuits and Technology Meeting. Atlanta, United States. 2005. United States. IEEE. 2005. 148-151
[6] B. Pregardier, U. Langmann, W. Hillery. A 1.2-GS/s 8-b Silicon Bipolar Track & Hold IC[J]. IEEE Journal of Solid-State Circuits. 1996. 31(9). 1336-1339
[7] J. Jensen, L. Larson. A Broadband 10-GHz Track-and-Hold in Si/SiGe HBT Technology[J]. IEEE Journal of Solid-State Circuits. 2001. 36(3). 325-330
[8] P.E. Allen著.冯军等译. CMOS模拟集成电路设计[M].第二版.北京.电子工业出版社. 2006. 501-583
[9] D. Dallet, J.M. da Silva. ADC的动态特性[M].第一版(影印版).北京.科学出版社. 2007. 85-92
[10] D.A. Johns, K. Martin著.曾朝阳等译.模拟集成电路设计[M].第一版.北京.机械工业出版社. 2005. 347-377
[11]杨银堂,朱樟明,朱臻.高速CMOS数据转换器[M].第一版.北京.科学出版社. 2006. 19-32
[12]薛亮,沈延钊,张向民.一种CMOS高速采样/保持放大器[J].微电子学. 2008. 34(3). 310-313
[13] Analog Devices Inc.. Data Conversion Handbook[M]. 1st edition. Norwood. NEWNES. 2004. 7.91-7.110
[14] National Semiconductor Corporation. An Introduction to the Sampling Theorem[Z]. Application Note 236. 2002. 1-6
[15]谢孟贤,古妮娜. SiGe半导体在微电子技术发展中的重要作用[J].微电子学. 2008. 38(1). 33-43
[16]徐世六著. SiGe微电子技术[M].北京.国防工业出版社. 2007. 201-230
[17]朱正涌著.半导体集成电路[M].北京.清华大学出版社. 2006. 11-14
[18] M. Sadollahy, K. Hadidi. A High-Speed Highly-Linear CMOS S/H Circuit[C]. ICCCE08. Kuala Lumpur, Malaysia. 2008. Kuala Lumpur, Malaysia. International Islamic University Malaysia. 2008. 550-553
[19] M. Nayebi, B.A. Wooley. A 10-Bit Video BiCMOS Track-and-Hold Amplifier[J]. IEEE Journal of Solid-State Circuits. 24(4). 1989. 1507-1516
[20] W. Xu, E.G. Friedman. A CMOS Miller Hold Capacitence Sample-and-Hold Circuit to Reduce Charge Sharing Effect and Clock Feedthrough[C]. ASIC/SOC Conference, 2002. 15th Annual IEEE International. New York, United States. 2002. New York, United States. IEEE. 2002. 92-96
[21]李伟华著. VLSI设计基础[M].北京.电子工业出版社. 2005. 148-164
[22] C. Fiocchi, U. Gatti, F. Maloberti. Design Issues on High-Speed High-Resolution Track-and-Holds in BiCMOS Technology[J]. IEE Proceedings Circuits, Devices & Systems. 2000. 147(2). 100-106
[23] P. Vorenkamp, J.P. Verdaasdonk. Fully Bipolar, 120-Msample/s 10-b Track-and-Told Circuit[J]. IEEE Journal of Solid-State Circuits. 1992. 27(7). 988-992
[24] Y. Lu. Design of High-Speed SiGe HBT Circuits for Wideband Transceivers[Dissertation]. Atlanta, United States. Georgia Institute of Technology. 2007. 44-58
[25] P.A. Quinn. Feed-Forward Amplifier[P]. United States. Utility. 4146844. Mar. 27, 1979. 1-3
[26] S. Simpkins, W. Gross. Cascomp Feedforward Error Correction in HighSpeed Amplifier Design[J]. IEEE Journal of Solid-State Circuits. 1983. 18(6). 762-764
[27] T. Miki, H. Kouno, T. Kumamoto, et al. A 10-b 50 MS/s 500-mW A/D Converter Using a Differential-Voltage Subconverter[J]. IEEE Journal of Solid-State Circtuts. 1994. 29(4). 516-522
[28] R. Caprio. Precision Differential Voltage-Current Converter[J]. Electronic Letters. 1973. 9(6). 147-148
[29] A.N. Karanicolas. A 2.7-V 300-MS/s Track-and-Hold Amplifier[J]. IEEE Journal of Solid-State Circuits. 1997. 32(12). 1961-1967
[30] B. Razavi著.陈贵灿等译.模拟CMOS集成电路设计[M].第一版.西安.西安交通大学出版社. 2005. 330-359
[31] A.M. Abo. Design for Reliability of Low-voltage, Switched-capacitor Circuit[Dissertation]. Berkeley, United States. UNIVERSITY of CALIFORNIA, Berkeley. 1999. 5-11
[32] B. Razavi. Design of Sample-and-Hold Amplifiers for High-Speed Low-Voltage A/D Converers[C]. CICC’97. Santa Clara, United States. 1997. New York, United States. IEEE. 1997. 59-66
[33] I. Sarkas, D. Mavridis, G. Papadopoulos. Volterra Analysis Using Chebyshev Series[C]. ISCAS. New Orleans, United States. 2007. New Orleans, United States. The Printing House. 2007. 1931-1934
[34] A. Helmy, K. Sharaf, H. Ragai. A Simplified Analytical Model for Nonlinear Distortion in RF Bipolar Circuit[C]. MWSCAS. Lansing, United States. 2000. Piscataway, United States. IEEE. 2000. 966-969
[35] P.R. Gray, P.J. Hurst, S.H. Lewis, et al.模拟集成电路的分析与设计[M].第四版(影印版).北京.高等教育出版社. 2005. 503-509
[36] G.Caiulo, C. Fiocchi, U. Gatti, et al. On the Design of High-Speed High-Resolution Track and Holds[C]. ISCAS. Atlanta, United States. 1996. Piscataway, United States. IEEE. 1996. 73-76
[37] F. Vessal, C.A.T. Salama. An 8-Bit 2-Gsample/s Folding-Interpolating Analog-to-Digital Converter in SiGe Technology[J]. IEEE Journal of Solid-State Circuits. 2004. 39(1). 238-241