高密度封装集成电路的高加速应力失效研究
|
摘要
高加速应力试验是可靠性试验领域的重要研究方向,它可以快速有效的激发产品内部缺陷和薄弱环节,确定产品耐受应力极限,大幅度提高试验效率,降低产品研发成本。国内尚未对电子元器件开展系统的高加速应力试验工作,缺乏系统的试验方法研究和相应的极限应力试验的数据积累,因此,本课题针对高密度封装的IC开展了高加速应力试验及失效研究,研究内容包括高加速应力试验方法研究、失效机理研究以及试验剖面模拟仿真。
本文首先针对五种高密度封装的典型微电路进行了高加速应力试验,对每种样品分别系统的开展了温度步进试验、温度循环试验、振动步进试验,以及温度循环加上振动步进的复合应力试验。研制专用夹具和转接板,使用测量静态电源电流和管脚电压监测的在线监测方法,实现了对管脚参数的在线监控。
然后,针对高密度封装IC失效样品,研究了五种样品在高加速应力条件下的性能变化情况,研究了应力条件下暴露出的失效模式和失效机理。试验结果暴露出塑封样品分层开裂、键合点脱落等失效模式,以及陶瓷封装样品键合点化合物生长,导电胶开裂、铝膜氧化、管脚断裂等失效模式,分析了热应力、机械应力下化合物间扩散生长,键合失效等失效机理。
研究结果表明针对高密度封装IC进行高加速应力试验时,温度循环试验是最为有效的应力施加类型,对大多数高密度封装IC,温循剖面采用-65℃~165℃的高低温端点温度,15min的保温时间,循环数保持在5个以内,可以高效地实现样品缺陷的激发。
最后,使用ANSYS有限元分析对温度循环试验剖面的优化进行了讨论,并结合高加速应力试验的试验结果进行了综合分析,分析结果得到针对高密度封装IC,高效的温循试验应设置循环次数4~6次,温变率采用试验仪器最高温变率值,保温时间选择10-20min。结果验证了试验得到的高效温循剖面的正确性。
论文结果为开展高密度封装集成电路的高加速应力筛选提供了一定的技术参考。
Highly accelerated stress test is important research direction of the field of reliability testing. Internal flaws and weaknesses of products can be excited quickly and efficiently by HAST. Products limits of tolerance of stress can be identified. Test efficiency can be increased Substantially. Product development costs can be reduced. China has not carried out systematic work for electronic components on highly accelerated stress test. Systematic test method and corresponding data accumulated of stress test limit is lack. therefor, In this project highly accelerated stress tests and failure research are carried out for high density packaged IC. The study includes highly accelerated stress test method,monitoring design,failure analysis techniques,simulation of test section.
Highly Accelerated stress tests are carried out for high density packaged typical micro circuits. Temperature step test、temperature cycle test、vibration step test and compound stress test are executed for each sample. IDDQ and Pin in-situ monitoring instrument are designed to be used to monitor sample Pin Parameters.
Performances changes by stress are researched for five kinds of samples. Failure mode and mechanism are studied which is exposured by stress. Plastic packaged samples' layered cracking and bond off are exposured. Ceramic packaged samples' bond compound grouth、conductive adhesive cracking、aluminum oxide and pin fracture are exposured. Mechanism including the proliferation of growth in compounds and bond failure under thermal stress and mechanical stress are analyzed.
The results show that Temperature cycle test is the The most effective high accelerated stress test for high-density packaging IC. Efficient Temperature profile Apply -65℃~165℃to be Endpoint temperature、15min to be Holding time、6 to be cycles.
Finally, optimization of the temperature cycle test profile is discussed by ANSYS finite element analysis. Comprehensive analysis was carried out combined with high accelerated stress test results. Analysis Conclusion is that for high density packaged IC, cycle of effective screening test is 3-4. The highest temperature change rate of test equipment should be used. Low-temperature holding time should be 10-20. high-temperature holding time should be 4-5. The results show the correctness of Efficient temperature cycling profile by test.
Thesis results provide technical reference for HASS on high density packaged IC.
本文首先针对五种高密度封装的典型微电路进行了高加速应力试验,对每种样品分别系统的开展了温度步进试验、温度循环试验、振动步进试验,以及温度循环加上振动步进的复合应力试验。研制专用夹具和转接板,使用测量静态电源电流和管脚电压监测的在线监测方法,实现了对管脚参数的在线监控。
然后,针对高密度封装IC失效样品,研究了五种样品在高加速应力条件下的性能变化情况,研究了应力条件下暴露出的失效模式和失效机理。试验结果暴露出塑封样品分层开裂、键合点脱落等失效模式,以及陶瓷封装样品键合点化合物生长,导电胶开裂、铝膜氧化、管脚断裂等失效模式,分析了热应力、机械应力下化合物间扩散生长,键合失效等失效机理。
研究结果表明针对高密度封装IC进行高加速应力试验时,温度循环试验是最为有效的应力施加类型,对大多数高密度封装IC,温循剖面采用-65℃~165℃的高低温端点温度,15min的保温时间,循环数保持在5个以内,可以高效地实现样品缺陷的激发。
最后,使用ANSYS有限元分析对温度循环试验剖面的优化进行了讨论,并结合高加速应力试验的试验结果进行了综合分析,分析结果得到针对高密度封装IC,高效的温循试验应设置循环次数4~6次,温变率采用试验仪器最高温变率值,保温时间选择10-20min。结果验证了试验得到的高效温循剖面的正确性。
论文结果为开展高密度封装集成电路的高加速应力筛选提供了一定的技术参考。
Highly accelerated stress test is important research direction of the field of reliability testing. Internal flaws and weaknesses of products can be excited quickly and efficiently by HAST. Products limits of tolerance of stress can be identified. Test efficiency can be increased Substantially. Product development costs can be reduced. China has not carried out systematic work for electronic components on highly accelerated stress test. Systematic test method and corresponding data accumulated of stress test limit is lack. therefor, In this project highly accelerated stress tests and failure research are carried out for high density packaged IC. The study includes highly accelerated stress test method,monitoring design,failure analysis techniques,simulation of test section.
Highly Accelerated stress tests are carried out for high density packaged typical micro circuits. Temperature step test、temperature cycle test、vibration step test and compound stress test are executed for each sample. IDDQ and Pin in-situ monitoring instrument are designed to be used to monitor sample Pin Parameters.
Performances changes by stress are researched for five kinds of samples. Failure mode and mechanism are studied which is exposured by stress. Plastic packaged samples' layered cracking and bond off are exposured. Ceramic packaged samples' bond compound grouth、conductive adhesive cracking、aluminum oxide and pin fracture are exposured. Mechanism including the proliferation of growth in compounds and bond failure under thermal stress and mechanical stress are analyzed.
The results show that Temperature cycle test is the The most effective high accelerated stress test for high-density packaging IC. Efficient Temperature profile Apply -65℃~165℃to be Endpoint temperature、15min to be Holding time、6 to be cycles.
Finally, optimization of the temperature cycle test profile is discussed by ANSYS finite element analysis. Comprehensive analysis was carried out combined with high accelerated stress test results. Analysis Conclusion is that for high density packaged IC, cycle of effective screening test is 3-4. The highest temperature change rate of test equipment should be used. Low-temperature holding time should be 10-20. high-temperature holding time should be 4-5. The results show the correctness of Efficient temperature cycling profile by test.
Thesis results provide technical reference for HASS on high density packaged IC.
引文
[1]范志峰,齐杏林,雷彬.加速可靠性试验综述[J].装备环境工程, 2008, 5(2), 37-40
[2] Criscimagna N.H. Accelerated Testing[J]. Selected Topics in Assurance Related Technologies,6(4)
[3]陈奇妙.美国可靠性强化试验技术发展点评[J].质量与可靠性, 1998, 44-47
[4] Robert W D. Reliability Enhancement Testing (RET) [C]. 1994 Proceeding Annual Reliability and Maintainabilility Symposium, 91-98.
[5] Hobbs G K. Accelerated Reliability Engineering-HALT and HASS [M]. New York: John Wiley& Sons Ltd. 2000.
[6] Shi Daniel, Fan Xuejun, Xie Bin. A New Method for Equivalent Acceleration of JEDEC Moisture Sensitivity Levels[C]. Electronic Components and Technology Conference, 2008, 907-912
[7] Xie Bin, Shi Xunqing, Fan Xuejun. Accelerated Moisture Sensitivity Test Methodology for Stacked-Die Molded Matrix Array Package[C]. 9th Electronics Packaging Technology Conference, 2007, 100-104
[8] Lee J.B., Song l.K., Kim J.Y., et al. Aging Characteristics of Polymer Lightning Arrester by Multi-Stress Accelerated Aging Test[C]. International Conference on Solid Dielectrics, 2004.
[9] Dalal S.B., Gorur R.S., Dyer M.L. Aging of Distribution Cables in Service and Its Simulation in the Laboratory[C]. IEEE Transactions on Dielectrics and Electrical Insulation, 2005, 139-146
[10] Lall Pradeep. Challenges in Accelerated Life Testing[C]. Inter Socleiy Conference on Thermal Phenomena, 2004, 727
[11] Han Changwoon, Song Byeongsuk. Development of Life Prediction Model for Lead-free Solder at Chip Resistor[C]. Electronics Packaging Technology Conference, 2006, 781-786
[12] Caers J.F.J.M., Zhao X.J., Vries J.W.C.de, et al. HART: A New HighlyAccelerated Robustness Test for Conductive Adhesive Interconnects[C]. Electronic Components and Technology Conference, 2008, 1695-1699
[13] Mirzaie M., Gholami A., Tayyebi H. Life Time Estimation and Reliability Model for Cellulose Insulation[C]. International Conference on Solid Dielectrics, 2007, 102-105
[14] Lee Kang J., Damani Manoj, Pucha Raghuram V. Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates[C]. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2007, 152-162
[15] Alexandrine Guédon-Gracia, Eric Woirgard, Christian Zardini. Reliability of Lead-Free BGA Assembly: Correlation Between Accelerated Ageing Tests and FE Simulations[C]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2008, 449-45
[16]吉国凡,薛宏,王忆文.用于CMOS集成电路的IDDQ测试技术研究[J].微处理机, 1999年,(3),14-15
[17]谭超元,钟征宇. IDDQ测试技术及其实现方法[J].电子产品可靠性与环境试验, 1999年, (1), 38-42
[18]鲍信茹,汪志伟,李文石. IDDQ测试原理及案例[J].中国集成电路, 2006, 15(9), 74-75
[19]温熙森,陈循,张春华,等.可靠性强化试验理论与应用[M].北京:科学出版社, 2007:1-176
[20]蒋瑜,陈循,陶俊勇. HALT试验高效率振动剖面的建立[J].宇航学报, 2006, 27(3), 531-535
[21]褚卫华,陈循,王考,等. HALT试验高效率温度剖面图的建立.宇航学报, 2004, 25(2), 195-200
[22] Drake C. HALT Guideline[S]. Qualmark corporation, 2003
[23] Feero M. HASS Guideline[S]. Qualmark corporation, 2007
[24]宋芳芳,牛付林.塑封电子元器件破坏性物理分析方法[J].电子产品可靠性与环境试验, 2004, (5), 52-55
[25]李新,周毅,孙承松.塑封微电子器件失效机理研究进展[J].半导体技术, 2008, 33(2), 98-101
[26]杨建生. PBGA封装的可靠性研究综述[J].电子产品可靠性与环境试验, 2004,(1), 53-57
[27]孔学东,恩云飞等.电子元器件失效分析与典型案例[M].北京:国防工业出版社, 2006: 1-260
[28]肖久梅,黄继华.微电子互连用导电胶研究进展[J].中国粘结剂, 2004, 13(6), 43-48
[29]徐慧,杭春进,王春青,等.金、铜丝球键合焊点的可靠性对比研究[J].电子工业专用设备, 2006, 35(5), 23-27
[30]马孝松.微电子封装高聚物热_湿_机械特性及其封装可靠性研究[D].西安:西安电子科技大学, 2006
[31]孟宪刚,杨会平.提高CQFP封装器件加工的工艺可靠性试验[J].航天器工程, 2006, 15(4), 64-67
[32]毕锦栋,林长苓.集成电路封装技术可靠性探讨[J].电子产品可靠性与环境试验, 2008, 26(6), 34-38
[33]王呼佳,陈洪军. ANSYS工程分析进阶实例[M].北京:中国水利水电出版社,2006:1-428
[2] Criscimagna N.H. Accelerated Testing[J]. Selected Topics in Assurance Related Technologies,6(4)
[3]陈奇妙.美国可靠性强化试验技术发展点评[J].质量与可靠性, 1998, 44-47
[4] Robert W D. Reliability Enhancement Testing (RET) [C]. 1994 Proceeding Annual Reliability and Maintainabilility Symposium, 91-98.
[5] Hobbs G K. Accelerated Reliability Engineering-HALT and HASS [M]. New York: John Wiley& Sons Ltd. 2000.
[6] Shi Daniel, Fan Xuejun, Xie Bin. A New Method for Equivalent Acceleration of JEDEC Moisture Sensitivity Levels[C]. Electronic Components and Technology Conference, 2008, 907-912
[7] Xie Bin, Shi Xunqing, Fan Xuejun. Accelerated Moisture Sensitivity Test Methodology for Stacked-Die Molded Matrix Array Package[C]. 9th Electronics Packaging Technology Conference, 2007, 100-104
[8] Lee J.B., Song l.K., Kim J.Y., et al. Aging Characteristics of Polymer Lightning Arrester by Multi-Stress Accelerated Aging Test[C]. International Conference on Solid Dielectrics, 2004.
[9] Dalal S.B., Gorur R.S., Dyer M.L. Aging of Distribution Cables in Service and Its Simulation in the Laboratory[C]. IEEE Transactions on Dielectrics and Electrical Insulation, 2005, 139-146
[10] Lall Pradeep. Challenges in Accelerated Life Testing[C]. Inter Socleiy Conference on Thermal Phenomena, 2004, 727
[11] Han Changwoon, Song Byeongsuk. Development of Life Prediction Model for Lead-free Solder at Chip Resistor[C]. Electronics Packaging Technology Conference, 2006, 781-786
[12] Caers J.F.J.M., Zhao X.J., Vries J.W.C.de, et al. HART: A New HighlyAccelerated Robustness Test for Conductive Adhesive Interconnects[C]. Electronic Components and Technology Conference, 2008, 1695-1699
[13] Mirzaie M., Gholami A., Tayyebi H. Life Time Estimation and Reliability Model for Cellulose Insulation[C]. International Conference on Solid Dielectrics, 2007, 102-105
[14] Lee Kang J., Damani Manoj, Pucha Raghuram V. Reliability Modeling and Assessment of Embedded Capacitors in Organic Substrates[C]. IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2007, 152-162
[15] Alexandrine Guédon-Gracia, Eric Woirgard, Christian Zardini. Reliability of Lead-Free BGA Assembly: Correlation Between Accelerated Ageing Tests and FE Simulations[C]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2008, 449-45
[16]吉国凡,薛宏,王忆文.用于CMOS集成电路的IDDQ测试技术研究[J].微处理机, 1999年,(3),14-15
[17]谭超元,钟征宇. IDDQ测试技术及其实现方法[J].电子产品可靠性与环境试验, 1999年, (1), 38-42
[18]鲍信茹,汪志伟,李文石. IDDQ测试原理及案例[J].中国集成电路, 2006, 15(9), 74-75
[19]温熙森,陈循,张春华,等.可靠性强化试验理论与应用[M].北京:科学出版社, 2007:1-176
[20]蒋瑜,陈循,陶俊勇. HALT试验高效率振动剖面的建立[J].宇航学报, 2006, 27(3), 531-535
[21]褚卫华,陈循,王考,等. HALT试验高效率温度剖面图的建立.宇航学报, 2004, 25(2), 195-200
[22] Drake C. HALT Guideline[S]. Qualmark corporation, 2003
[23] Feero M. HASS Guideline[S]. Qualmark corporation, 2007
[24]宋芳芳,牛付林.塑封电子元器件破坏性物理分析方法[J].电子产品可靠性与环境试验, 2004, (5), 52-55
[25]李新,周毅,孙承松.塑封微电子器件失效机理研究进展[J].半导体技术, 2008, 33(2), 98-101
[26]杨建生. PBGA封装的可靠性研究综述[J].电子产品可靠性与环境试验, 2004,(1), 53-57
[27]孔学东,恩云飞等.电子元器件失效分析与典型案例[M].北京:国防工业出版社, 2006: 1-260
[28]肖久梅,黄继华.微电子互连用导电胶研究进展[J].中国粘结剂, 2004, 13(6), 43-48
[29]徐慧,杭春进,王春青,等.金、铜丝球键合焊点的可靠性对比研究[J].电子工业专用设备, 2006, 35(5), 23-27
[30]马孝松.微电子封装高聚物热_湿_机械特性及其封装可靠性研究[D].西安:西安电子科技大学, 2006
[31]孟宪刚,杨会平.提高CQFP封装器件加工的工艺可靠性试验[J].航天器工程, 2006, 15(4), 64-67
[32]毕锦栋,林长苓.集成电路封装技术可靠性探讨[J].电子产品可靠性与环境试验, 2008, 26(6), 34-38
[33]王呼佳,陈洪军. ANSYS工程分析进阶实例[M].北京:中国水利水电出版社,2006:1-428