基于DDS技术的Loran-C信号发生器的设计与实现
摘要
在设计高性能Loran-C数字接收机过程中需要能模拟各种干扰环境下的Loran-C脉冲信号的发生器,利用传统的模拟或数字电路产生Loran-C脉冲信号,存在着实现困难、误差较大、不易调整和难于叠加环境干扰信号的缺点。随着现代电子技术和VLSI技术的发展,利用大规模可编程门阵列(FPGA, Field Programmable Gate Array)与直接频率合成技术(DDS, Direct Digital Synthesizer)相结合可以极大地提高函数发生器的性能,降低开发难度。为此,论文在详细研究前人在Loran-C信号模拟源的研究和设计的基础之上,研究了FPGA和DDS相结合的技术,并以此进行了Loran-C信号发生器的设计与实现。
论文以利用FPGA和DDS技术相结合的方式设计实现Loran-C信号发生器为主要内容。首先,简要介绍了Loran-C无线电导航系统和DDS技术的国内外研究现状和研究意义,接着详细阐述了Loran-C系统的数据结构和DDS技术的基本原理。
然后,在分析信号发生器的设计要求的基础上,确定了本信号发生器采用以FPGA为核心处理器构架的方案,并基于FPGA+DSP构架实现了该信号发生器。其中FPGA芯片选用的是Xilinx公司Virtex-5系列的XC5VSX50TFF665,作为信号模拟源的信号发生器完成Loran-C信号波形的合成与台链信号的控制逻辑生成；DSP芯片选用TI公司TMS320C6713作为主控器,完成对时间信号根据Loran-C信号报文格式进行编码传送到FPGA以控制Loran-C台链信号的发生。在硬件设计时,论文给出了信号发生器的总体框图并详述了信号发生器的工作原理以及选用的主要芯片的特点和硬件系统中主要模块的设计,使用PADS2005设计了信号发生器的硬件原理图并绘制了PCB图,在利用PADSLogic软件完成系统的原理图设计之后,利用HyperLynx7.5对系统重要高速信号线进行仿真,证明了系统原理图设计是正确可靠的,确保了硬件设计正确实现。
论文的最后根据Loran-C脉冲信号的波形理论采用DDS技术在信号发生器上设计实现了一个Loran-C脉冲信号发生模块并产生了标准的Loran-C脉冲信号。
A high performance Loran-C signal generator which can generate Loran-C signals include noise and all kind of interference is needed at the process of design digital Loran-C receiver, the capability of Loran-C signal generator by using traditional analog or digital electrocircuit exist many disadvantage such as diffcult to realize, biggish error in resolving capability, hard to adjust and add noise and environment interference. With steady advances and development in modern electronic technology especially very large scale integration technology (VLSI), the capability of signal generator by using Field Programmable Gate Array (FPGA) combined with direct digital synthesizer (DDS) technique will be improved greatly and the difficulty of designing will be reduce|d observably.So based on the research and design previous, firstly design Loran-C signal generator adopt FPGA combined with DDS technique.
This paper is focused on the design of Loran-C signal generator based on FPGA combined with DDS technology. Firstly, it introduces the development history of the Loran-C System and DDS technique. Secondly, it introduces the data structure of Loran-C system, and then it introduces the basic theory of direct digital synthesizer technique.
Furthermore, this paper introduces the construction of the design which is based on Xilinx Inc high performance FPGA according to the requirement of the signal generator, and the system is implemented based on the DSP and FPGA co-processing. The design chooses Xilinx Inc Virtex-5 family FPGA-XC5VSX50TFF665 as signal generator to generate Loran-C signal and its control logic, and chooses TI Inc TMS320C6713 as central controller to code the time information according to the code structure of Loran-C sent to FPGA used to control the generation of Loran-C datalink signals. For the hardware circuit design of the system, the paper presents the conceptual frame of the signal generator and expands the principle of the signal generator, and expatiates that the main chips used in the signal generator and the main modules of hardware circuit, the designs of the hardware scheme circuit and the PCB of the system board is based on PADS2005, and simulate the signal integrity of the significant signal wires after accomplished the hardware scheme circuit which proves the correctness of the hardware scheme circuit.
At last, the Loran-C signal generation module based on DDS is realized according to Loran-C signal generation theory and the debugging results are given.
论文以利用FPGA和DDS技术相结合的方式设计实现Loran-C信号发生器为主要内容。首先,简要介绍了Loran-C无线电导航系统和DDS技术的国内外研究现状和研究意义,接着详细阐述了Loran-C系统的数据结构和DDS技术的基本原理。
然后,在分析信号发生器的设计要求的基础上,确定了本信号发生器采用以FPGA为核心处理器构架的方案,并基于FPGA+DSP构架实现了该信号发生器。其中FPGA芯片选用的是Xilinx公司Virtex-5系列的XC5VSX50TFF665,作为信号模拟源的信号发生器完成Loran-C信号波形的合成与台链信号的控制逻辑生成；DSP芯片选用TI公司TMS320C6713作为主控器,完成对时间信号根据Loran-C信号报文格式进行编码传送到FPGA以控制Loran-C台链信号的发生。在硬件设计时,论文给出了信号发生器的总体框图并详述了信号发生器的工作原理以及选用的主要芯片的特点和硬件系统中主要模块的设计,使用PADS2005设计了信号发生器的硬件原理图并绘制了PCB图,在利用PADSLogic软件完成系统的原理图设计之后,利用HyperLynx7.5对系统重要高速信号线进行仿真,证明了系统原理图设计是正确可靠的,确保了硬件设计正确实现。
论文的最后根据Loran-C脉冲信号的波形理论采用DDS技术在信号发生器上设计实现了一个Loran-C脉冲信号发生模块并产生了标准的Loran-C脉冲信号。
A high performance Loran-C signal generator which can generate Loran-C signals include noise and all kind of interference is needed at the process of design digital Loran-C receiver, the capability of Loran-C signal generator by using traditional analog or digital electrocircuit exist many disadvantage such as diffcult to realize, biggish error in resolving capability, hard to adjust and add noise and environment interference. With steady advances and development in modern electronic technology especially very large scale integration technology (VLSI), the capability of signal generator by using Field Programmable Gate Array (FPGA) combined with direct digital synthesizer (DDS) technique will be improved greatly and the difficulty of designing will be reduce|d observably.So based on the research and design previous, firstly design Loran-C signal generator adopt FPGA combined with DDS technique.
This paper is focused on the design of Loran-C signal generator based on FPGA combined with DDS technology. Firstly, it introduces the development history of the Loran-C System and DDS technique. Secondly, it introduces the data structure of Loran-C system, and then it introduces the basic theory of direct digital synthesizer technique.
Furthermore, this paper introduces the construction of the design which is based on Xilinx Inc high performance FPGA according to the requirement of the signal generator, and the system is implemented based on the DSP and FPGA co-processing. The design chooses Xilinx Inc Virtex-5 family FPGA-XC5VSX50TFF665 as signal generator to generate Loran-C signal and its control logic, and chooses TI Inc TMS320C6713 as central controller to code the time information according to the code structure of Loran-C sent to FPGA used to control the generation of Loran-C datalink signals. For the hardware circuit design of the system, the paper presents the conceptual frame of the signal generator and expands the principle of the signal generator, and expatiates that the main chips used in the signal generator and the main modules of hardware circuit, the designs of the hardware scheme circuit and the PCB of the system board is based on PADS2005, and simulate the signal integrity of the significant signal wires after accomplished the hardware scheme circuit which proves the correctness of the hardware scheme circuit.
At last, the Loran-C signal generation module based on DDS is realized according to Loran-C signal generation theory and the debugging results are given.
引文
[1]熊伟.Loran-C数字信号处理的关键技术研究.博士学位论文.中国科学院研究生院.2008.5
[2]吴海涛.罗兰C自主授时及其数据通信的研究.博士学位论文.中国科学院研究生院.2002.4
[3]皱德财.Loran-C数字接收机关键技术研究.硕士学位论文.中国科学院研究生院.2006.5
[4]迈迪编著.长河二号工程一远程无线电导航系统[M].北京：电子工业出版社出版,1993年
[5]P021型全自动长波定时校频接收机使用说明书[M].国家授时中心.1999年
[6]朱银兵,曹可劲,崔国恒,胡东亮.罗兰C信号数字处理方法分析.弹箭与制导学报.2008.12.Vol.28.No.6：222-225
[7]1E秀森,张治军,王孝通.罗兰C信号模拟器的设计与实现.海军工程大学学报.2001.13(8)：71-74
[8]修智宏,任光,付凤歧,杨美健.LORAN C导航系统电磁环境模拟器设计与实现.系统工程与电子技术.2002.Vol.24.No.6：119-123
[9]GPS Risk Analysis,Hoplins University. Applied Physics Laboratory,Jan.29,1999.
[10]林慧贞,罗斌凤,胡东亮,杨忠俊.波形匹配法识别罗兰-C信号周期.舰船电子工程.2008.5 Vol 28 No 5
[11]邓君,张辉.改进的卡尔曼滤波算法在罗兰C系统中的应用.军事通信.2006.1：46-48
[12]The Loran Consolidated Control System:"Positioning"Loran Radionavigation for the Year 2000,Radionavigation Bulletin,Fall/.Winter,1997
[13]J.Tierney, C.Rader,B.Gold.A Digital Frequeney Synthesizer. IEEE Transactions on Audio and Electroacoustics,1971.3AU-19(1):48-57
[14]Saul P H. Direct frequency synthesis-a review of techniques and potential. In:IEEE 15th International Conference on Radio Receivers and Associated System. Landon,1990,5-9.
[15]田耘,徐文波,张延伟.无线通信FPGA设计.北京：电子工业出版社.2008
[16]白居宪.直接数字频率合成.西安：西安交通大学出版社.2007
[17]冯朝军.直接数字频率合成(DDS)的软件及硬件实现.硕士学位论文.西南交通大学.2007.3
[18]程国兵,刘拥军,苟彦新.基于FPGA的直接数字频率合成器的实现.通信技术与 设备.2003.Vol.29.No.12：25-26,59
[19]江志浩,孙明珠,蔡德荣.高精度DDS的FPGA资源优化设计.微计算机信息.2009Vol.25.No.1-2：191-193
[20]李志鹏,郭勇,沈军.基于DDS技术实现信号发生器[J].微计算机信息,2007,7-1：175-177.
[21]陈慧琴.基于DDS技术的信号波形产生器.硕士学位论文.电子科技大学.2006.11
[22]郭立浩.基于FPGA的直接数字频率合成器的研究与应用.硕士学位论文.西北工业大学.2006.3
[23]蒋宁.基于DDS的频率合成器设计.硕士学位论文.电子科技大学.2006.5
[24]单玉华,基于DDS频率合成杂散抑制技术的研究,硕士学位论文,电子科技大学,2002
[25]王玉珍,李袁柳.现代频率合成技术发展状况及分析.宇航计测技术.2003.6.Vol.23.No.3：
[26]王文华,基于DDS技术的任意波形发生器研究,硕士学位论文,浙江大学,2002
[27]Texas Instruments.TPS54310 datasheet.2007
[28]Texas Instruments.TPS3307-25 datasheet.2004
[29]Texas Instruments.TMS320C6713 floating Point digital signal Processor datasheet.2005
[30]Texas Instruments. TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide.2002:
[31]Texas Instruments.TMS320C6000 CPU and Instruetion Set Referenee Guide.2000
[32]Texas Instruments.TMS320C6000 Chip Support Library API User's Guide.2002
[33]Texas Instruments.TMS320C6000 DSP EMIF Referenee Guide.2004
[34]Texas Instruments.TMS320C6000 DSP HPI Referenee Guide.2004
[35]Texas Instruments.TMS320C6000 EMIF-to-External Flash Memory.2002
[36]Texas Instruments.TMS320C6000 EMIF-to-External SDRAM Interface.2004
[37]Texas Instruments.TMS320C6000 Memory Test.2002
[38]Analog Device,Inc.AD9762 datasheet.2000
[39]江思敏,刘畅.TMS320C6000 DSP应用开发教程[M].北京：机械工业出版社,2005
[40]李方慧,王飞,何佩琨.TMS320C6000系列DSPs的原理与应用(第二版)[M].北京：电子工业出版社,2003
[41]张雄伟,曹铁勇.DSP芯片的原理与开发应用.北京：电子工业出版社.2001
[42]三恒星科技.TMS320C6-713 DSP原理与应用实例.北京：电子工业出版社.2009
[43]赵加祥.DSP系统设计和BIOS编程及应用实例.北京：机械工业出版社.2008
[44](美)Michael D.Ciletti著,张雅琦,李锵等译.Verilog HDL高级数字设计.北京,电子工业出版社.2008
[45]薛小刚,葛毅敏.：Xilinx ISE 9.X FPGA/CPLD设计指南．北京,人民邮电出版社.2007.6
[46]Samir Palnitkar著.夏宇闻,胡燕祥译.Verilog HDL数字设计与综合.北京：电子工业出版社,2009
[47]王冠,俞一鸣.面向CPLD/FPGA的Verilog设计．北京：机械工业出版社.2008.3
[48]Xilinx Inc.Virtex-5.FPGA user Guide.2009.
[49]Xilinx Inc.Virtex-5 FPGA PCB Designer's Guide.2009
[50]Xilinx Inc. Virtex-5 Family Overview.2009
[51]Xilinx Inc.Virtex-5 FPGA Data Sheet:DC and Switching Characteristics.2009
[52]Xilinx Inc.Virtex-5 FPGA Configuration Guide.2009
[53]Xilinx Inc.Virtex-5 FPGA Packaging and Pinout Specification.2009
[54]孙航,胡灵博,于联锋.Xilinx可编程逻辑器件应用与系统设计[M]．北京：电子工业出版社,2008.
[55](美)Mark I.Montrose著,吕英华,于学萍,张金玲等译.电磁兼容的印制电路板设计.北京：机械工业出版社,2008.12
[56](美)：Eric Bogatin著,李玉山，李丽平等译.信号完整性分析.北京：信号完整性分析,2009
[57](美)Howard Johnson, Martin Graham著,沈立,朱来文,陈宏伟译.高速数字设计.北京：电子工业出版社,2009.
[2]吴海涛.罗兰C自主授时及其数据通信的研究.博士学位论文.中国科学院研究生院.2002.4
[3]皱德财.Loran-C数字接收机关键技术研究.硕士学位论文.中国科学院研究生院.2006.5
[4]迈迪编著.长河二号工程一远程无线电导航系统[M].北京：电子工业出版社出版,1993年
[5]P021型全自动长波定时校频接收机使用说明书[M].国家授时中心.1999年
[6]朱银兵,曹可劲,崔国恒,胡东亮.罗兰C信号数字处理方法分析.弹箭与制导学报.2008.12.Vol.28.No.6：222-225
[7]1E秀森,张治军,王孝通.罗兰C信号模拟器的设计与实现.海军工程大学学报.2001.13(8)：71-74
[8]修智宏,任光,付凤歧,杨美健.LORAN C导航系统电磁环境模拟器设计与实现.系统工程与电子技术.2002.Vol.24.No.6：119-123
[9]GPS Risk Analysis,Hoplins University. Applied Physics Laboratory,Jan.29,1999.
[10]林慧贞,罗斌凤,胡东亮,杨忠俊.波形匹配法识别罗兰-C信号周期.舰船电子工程.2008.5 Vol 28 No 5
[11]邓君,张辉.改进的卡尔曼滤波算法在罗兰C系统中的应用.军事通信.2006.1：46-48
[12]The Loran Consolidated Control System:"Positioning"Loran Radionavigation for the Year 2000,Radionavigation Bulletin,Fall/.Winter,1997
[13]J.Tierney, C.Rader,B.Gold.A Digital Frequeney Synthesizer. IEEE Transactions on Audio and Electroacoustics,1971.3AU-19(1):48-57
[14]Saul P H. Direct frequency synthesis-a review of techniques and potential. In:IEEE 15th International Conference on Radio Receivers and Associated System. Landon,1990,5-9.
[15]田耘,徐文波,张延伟.无线通信FPGA设计.北京：电子工业出版社.2008
[16]白居宪.直接数字频率合成.西安：西安交通大学出版社.2007
[17]冯朝军.直接数字频率合成(DDS)的软件及硬件实现.硕士学位论文.西南交通大学.2007.3
[18]程国兵,刘拥军,苟彦新.基于FPGA的直接数字频率合成器的实现.通信技术与 设备.2003.Vol.29.No.12：25-26,59
[19]江志浩,孙明珠,蔡德荣.高精度DDS的FPGA资源优化设计.微计算机信息.2009Vol.25.No.1-2：191-193
[20]李志鹏,郭勇,沈军.基于DDS技术实现信号发生器[J].微计算机信息,2007,7-1：175-177.
[21]陈慧琴.基于DDS技术的信号波形产生器.硕士学位论文.电子科技大学.2006.11
[22]郭立浩.基于FPGA的直接数字频率合成器的研究与应用.硕士学位论文.西北工业大学.2006.3
[23]蒋宁.基于DDS的频率合成器设计.硕士学位论文.电子科技大学.2006.5
[24]单玉华,基于DDS频率合成杂散抑制技术的研究,硕士学位论文,电子科技大学,2002
[25]王玉珍,李袁柳.现代频率合成技术发展状况及分析.宇航计测技术.2003.6.Vol.23.No.3：
[26]王文华,基于DDS技术的任意波形发生器研究,硕士学位论文,浙江大学,2002
[27]Texas Instruments.TPS54310 datasheet.2007
[28]Texas Instruments.TPS3307-25 datasheet.2004
[29]Texas Instruments.TMS320C6713 floating Point digital signal Processor datasheet.2005
[30]Texas Instruments. TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide.2002:
[31]Texas Instruments.TMS320C6000 CPU and Instruetion Set Referenee Guide.2000
[32]Texas Instruments.TMS320C6000 Chip Support Library API User's Guide.2002
[33]Texas Instruments.TMS320C6000 DSP EMIF Referenee Guide.2004
[34]Texas Instruments.TMS320C6000 DSP HPI Referenee Guide.2004
[35]Texas Instruments.TMS320C6000 EMIF-to-External Flash Memory.2002
[36]Texas Instruments.TMS320C6000 EMIF-to-External SDRAM Interface.2004
[37]Texas Instruments.TMS320C6000 Memory Test.2002
[38]Analog Device,Inc.AD9762 datasheet.2000
[39]江思敏,刘畅.TMS320C6000 DSP应用开发教程[M].北京：机械工业出版社,2005
[40]李方慧,王飞,何佩琨.TMS320C6000系列DSPs的原理与应用(第二版)[M].北京：电子工业出版社,2003
[41]张雄伟,曹铁勇.DSP芯片的原理与开发应用.北京：电子工业出版社.2001
[42]三恒星科技.TMS320C6-713 DSP原理与应用实例.北京：电子工业出版社.2009
[43]赵加祥.DSP系统设计和BIOS编程及应用实例.北京：机械工业出版社.2008
[44](美)Michael D.Ciletti著,张雅琦,李锵等译.Verilog HDL高级数字设计.北京,电子工业出版社.2008
[45]薛小刚,葛毅敏.：Xilinx ISE 9.X FPGA/CPLD设计指南．北京,人民邮电出版社.2007.6
[46]Samir Palnitkar著.夏宇闻,胡燕祥译.Verilog HDL数字设计与综合.北京：电子工业出版社,2009
[47]王冠,俞一鸣.面向CPLD/FPGA的Verilog设计．北京：机械工业出版社.2008.3
[48]Xilinx Inc.Virtex-5.FPGA user Guide.2009.
[49]Xilinx Inc.Virtex-5 FPGA PCB Designer's Guide.2009
[50]Xilinx Inc. Virtex-5 Family Overview.2009
[51]Xilinx Inc.Virtex-5 FPGA Data Sheet:DC and Switching Characteristics.2009
[52]Xilinx Inc.Virtex-5 FPGA Configuration Guide.2009
[53]Xilinx Inc.Virtex-5 FPGA Packaging and Pinout Specification.2009
[54]孙航,胡灵博,于联锋.Xilinx可编程逻辑器件应用与系统设计[M]．北京：电子工业出版社,2008.
[55](美)Mark I.Montrose著,吕英华,于学萍,张金玲等译.电磁兼容的印制电路板设计.北京：机械工业出版社,2008.12
[56](美)：Eric Bogatin著,李玉山，李丽平等译.信号完整性分析.北京：信号完整性分析,2009
[57](美)Howard Johnson, Martin Graham著,沈立,朱来文,陈宏伟译.高速数字设计.北京：电子工业出版社,2009.
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