基于FPGA的电子硬盘控制器设计
摘要
电子硬盘是一种利用非易失性电子类存储器作为存储介质的硬盘。电子硬盘仍采用IDE接口与主机系统相连。硬盘控制器作为硬盘方的主控制芯片负责实现硬盘的功能。基于FPGA的电子硬盘控制器设计主要利用Altera公司的嵌入式微处理器知识产权内核NiosⅡ作为硬盘控制器的主控CPU内核。以Altera公司的FPGA作为硬盘控制器原形设计的实验载体,以QuartusⅡ以及SOPC Builder作为开发环境,按照基于模块的系统芯片设计流实现硬盘控制器FPGA原形的构造、调试和仿真。论文内容包括硬盘工作原理,ATA协议分析,各系统模块的构造实现,调试与功耗估计。涉及利用参数化模块设计系统模块,改进时钟同步设计,全局时钟资源的利用和分配,速度和面积优势的选择,Moore型状态机设计,消除毛刺,自定义模块与系统的连接,嵌入式逻辑分析仪的调试方法等内容。
The Electronical hardisk adopts non-volatility Flash memory to hold data. As the traditional hardisk system, the electronical hardisk communicates with host system on ATA (Advanced Technology Attachment) protocal, its alternative name is IDE interface protocal. Hardisk controller chip charges the whole works of hardisk. It makes a master-slave pair with IDE AT A/AT API master controller on mainbord of host sytem. ATA protocal describe the principle of hardisk's working, consists of instructions set, interface way and states' transition of host-device master-slave couple. Hardisk controller chip was designed based on Altera's Nios ii opencore IP. A Flash control unit is in charge of the operation of Flash memories. It was like the IDE interface module. Both of them are drew, modified as well as realized in Quartus II FPGA development enviomment. That just is the feature of the whole design.
The Electronical hardisk adopts non-volatility Flash memory to hold data. As the traditional hardisk system, the electronical hardisk communicates with host system on ATA (Advanced Technology Attachment) protocal, its alternative name is IDE interface protocal. Hardisk controller chip charges the whole works of hardisk. It makes a master-slave pair with IDE AT A/AT API master controller on mainbord of host sytem. ATA protocal describe the principle of hardisk's working, consists of instructions set, interface way and states' transition of host-device master-slave couple. Hardisk controller chip was designed based on Altera's Nios ii opencore IP. A Flash control unit is in charge of the operation of Flash memories. It was like the IDE interface module. Both of them are drew, modified as well as realized in Quartus II FPGA development enviomment. That just is the feature of the whole design.
引文
[1]·陈利学、孙彪、赵玉连 编著《微机总线与接口设计》电子科技大学出版社
[2]·Stefan sjoholm、Lennart Lindh著 《VHDL for Designers》Premic-Hall
[3]·彭澄廉 主编《挑战SOC-基于Nios的sopc设计与实践》清华大学出版社
[4]·曾繁泰、李冰、李晓林 著《EDA工程概论》清华大学出版社
[5]·曾繁泰、侯亚宁、崔元明著《可编程器件应用导论》清华大学出版社
[6]·魏庆福等著《STD,总线工业控制机的设计与应用》科学出版社
[7]·潘松、黄继业 编著《EDA技术实用教程》科学出版社
[8]·郭书军、王玉花、葛纫秋 编著《嵌入式处理器原理及应用》清华大学出版社
[9]·Michael Keating、Pierre Bricaud 著《片上系统》电子工业出版社
[10]·曾繁泰 王强 盛娜 编著《EDA工程的理论语实践》清华大学出版社
[11]·《AT Attachment with Packet Interface-7 volume 1～3》Amarican National Standard for information system
[12]·《Application Note for NAND Flash memory》www.samsung.com
[13]·《Mass Storage Application》www.samsung.com
[14]·《datasheet—64M x 8Bit NAND Flash memory》www.samsung.com
[15]·《Samsung's ATA Flash Controllers》www.samsung.com
[16]·《datasheet--S3CI9EOX01-updated Flash Interface Chip》www.samsung.com
[17]·Westor《FPGA设计指导性原则》www.eda.com.com
[18]·Synplify guide for synplify pro 7.22 www.synplify.com
[19]·STATE ASSIGNMENTS for statecad www.samsung.com
[20]·AN-synplify & quartus design method www.altera.com
[21]·AN-synplify & logic lock www.altera.com
[22]·Introduce_to_quartus2 www.altera.com
[23]·Spare_assignment_recommendation www.samsung.com
[24]·Timing Analysis www.altera.com
[25]·mn1_nios2_board_cyclone_ 1c20 www.altera.com
[26]·HANDBOOK_Nios2 Cpu www.altera.com
[27]·mn1_avalon_bus www.altera.com
[28]·Software_development_manual_Nios2 www.altera.com
[29]·tt_nios2_hardware_tutorial www.altera.com
[30]·ug_nios2_getting_started www.altera.com
[31]·Using SignalTap Ⅱ Embedded www.altera.com
[32]·Cyclone Device Handbook www.altera.com
[2]·Stefan sjoholm、Lennart Lindh著 《VHDL for Designers》Premic-Hall
[3]·彭澄廉 主编《挑战SOC-基于Nios的sopc设计与实践》清华大学出版社
[4]·曾繁泰、李冰、李晓林 著《EDA工程概论》清华大学出版社
[5]·曾繁泰、侯亚宁、崔元明著《可编程器件应用导论》清华大学出版社
[6]·魏庆福等著《STD,总线工业控制机的设计与应用》科学出版社
[7]·潘松、黄继业 编著《EDA技术实用教程》科学出版社
[8]·郭书军、王玉花、葛纫秋 编著《嵌入式处理器原理及应用》清华大学出版社
[9]·Michael Keating、Pierre Bricaud 著《片上系统》电子工业出版社
[10]·曾繁泰 王强 盛娜 编著《EDA工程的理论语实践》清华大学出版社
[11]·《AT Attachment with Packet Interface-7 volume 1～3》Amarican National Standard for information system
[12]·《Application Note for NAND Flash memory》www.samsung.com
[13]·《Mass Storage Application》www.samsung.com
[14]·《datasheet—64M x 8Bit NAND Flash memory》www.samsung.com
[15]·《Samsung's ATA Flash Controllers》www.samsung.com
[16]·《datasheet--S3CI9EOX01-updated Flash Interface Chip》www.samsung.com
[17]·Westor《FPGA设计指导性原则》www.eda.com.com
[18]·Synplify guide for synplify pro 7.22 www.synplify.com
[19]·STATE ASSIGNMENTS for statecad www.samsung.com
[20]·AN-synplify & quartus design method www.altera.com
[21]·AN-synplify & logic lock www.altera.com
[22]·Introduce_to_quartus2 www.altera.com
[23]·Spare_assignment_recommendation www.samsung.com
[24]·Timing Analysis www.altera.com
[25]·mn1_nios2_board_cyclone_ 1c20 www.altera.com
[26]·HANDBOOK_Nios2 Cpu www.altera.com
[27]·mn1_avalon_bus www.altera.com
[28]·Software_development_manual_Nios2 www.altera.com
[29]·tt_nios2_hardware_tutorial www.altera.com
[30]·ug_nios2_getting_started www.altera.com
[31]·Using SignalTap Ⅱ Embedded www.altera.com
[32]·Cyclone Device Handbook www.altera.com