8位CPU软核设计与应用研究
摘要
随着集成电路制造工艺的发展,芯片设计已进入SoC阶段,即可以把一个完整的应用系统集成到单个芯片中,使得设计复杂性大为提高,由此也产生了新的设计方法学。SoC设计涉及多方面的学科领域,如计算机体系结构、嵌入式软件、IP设计复用等。由于SoC设计是基于IP复用的设计,IP核的设计和使用方法显得尤为重要,设计时要着重考虑IP的可复用性和设计标准化。
8位单片机具有简单、高效、可靠等特点,因此自诞生以来,就一直在工控、通信等领域被广泛使用。单片机的结构、速度、功耗等在20多年间也有了较大的改进,指令集也有了很大的发展,出现了基于RISC指令集的单片机,简化了内部硬件指令译码的过程。以8位单片机为原型的8位CPU IP核也在SoC中有着广泛的应用前景,对于简单或不需进行复杂运算的SoC,8位CPU的IP核可以作为主运算和控制单元,完成数据的传输和运算;而对于复杂的SoC,8位CPU的IP核可作为数据传输、模块通信控制等应用。
本文选择以8位CPU软核的设计和应用为对象,研究了IP核设计以及SoC设计的基本理论与方法。论文的研究是基于项目80C51软核的设计与应用研究,该软核与MCS-51指令集兼容。项目进程中对该软核进行了改进和完善的验证。类似于单片机最小系统,作为软核的应用建立了片上心率系统,系统的开发涉及软件、硬件和验证等多个方面,具备了SoC开发的基本特点。该片上系统已经过FPGA平台验证并采用IBM 0.18um工艺流片。
本文首先介绍了SoC中的架构设计,概述了SoC中的软硬件结构,包括处理器、片上总线等等。然后结合ASIC设计方法对RTL设计、逻辑综合方法进行了较为深入的研究,同时对CPU的设计方法进行了一定的研究。最后通过研究生阶段的项目80C51软核的设计及应用说明了IC设计的流程及8位CPU软核的设计与应用。
本论文的主要研究结果为:
1、深入研究了当前IC前端设计的方法,包括RTL设计、逻辑综合和验证等。
2、研究了8位CPU软核的设计方法。
3、详细研究了80C51软核设计改进方法和验证方法
4、详细研究了片上心率系统的设计和验证方法。
As the development of IC manufacture technology, IC design has stepped in SoC period. SoC can intergrate on a whole system, including software and hardware, into a single chip, so design complexity is increased and new design methodologies are developed. SoC design relates to many subjects such as computer system structure, embedded system, IP design and reuse and so on. IP design and reuse methodologies are very important because SoC design is based on IP.
8-bit SCM (Single Chip Micyoco) is wildly used in industry control, communication fields because of the characteristic of flexity, credibility, simplicity and so on. Structures, speed, power and instructions of SCM are also improved during the 20 year development, such as using RISC instructions. 8-bit CPU IP based on 8-bit SCM structure is also being more and more wildly used is SoC design. 8 bit CPU IP can be used as main operation and control unit in SoCs which have simple structure or less processing function, and as data transmission and communication control unit in complex SoC.
Design and application of 8-bit CPU soft-IP are selected as research objects and IP design methodolgies and SoC design theories are studied in this paper. The research is based on project of 80C51 soft-IP design and application. In this project, 80C51 soft-IP is improved and verified, and similar to SCM applications, Heart-rate-dectect SoC is designed as an IP application. Many IC and software design aspects are involved andsome SoC design methodolges are used in the design process. The design has been verified on FPGA platform and taped out using IBM 0.18um technology.
In this paper, SoC architecture design is firstly introduced, some basic concepts and methods, such as hardware and software architecture, processor cores, bus-on-chip, are referred. Secondly, based on ASIC design, RTL design and logic synthesis methods are studied, at the same time, CPU design methods are also studied and presented. At last, a graduate project, 80C51 IP core redesign and application, is presented and analyzed to show the IC design flow and 8-bit CPU IP design and reuse.
The main results of paper are list below:
1. IC front design flow, including RTL design, logic synthesis and design verification and so on, is studied.
2. 8-bit CPU IP design methods are studied.
3. 80C51 IP core redesign and verification methods are studied in detail.
4. Heart-rate-detect SoC design and verification methods are studied and presented.
8位单片机具有简单、高效、可靠等特点,因此自诞生以来,就一直在工控、通信等领域被广泛使用。单片机的结构、速度、功耗等在20多年间也有了较大的改进,指令集也有了很大的发展,出现了基于RISC指令集的单片机,简化了内部硬件指令译码的过程。以8位单片机为原型的8位CPU IP核也在SoC中有着广泛的应用前景,对于简单或不需进行复杂运算的SoC,8位CPU的IP核可以作为主运算和控制单元,完成数据的传输和运算;而对于复杂的SoC,8位CPU的IP核可作为数据传输、模块通信控制等应用。
本文选择以8位CPU软核的设计和应用为对象,研究了IP核设计以及SoC设计的基本理论与方法。论文的研究是基于项目80C51软核的设计与应用研究,该软核与MCS-51指令集兼容。项目进程中对该软核进行了改进和完善的验证。类似于单片机最小系统,作为软核的应用建立了片上心率系统,系统的开发涉及软件、硬件和验证等多个方面,具备了SoC开发的基本特点。该片上系统已经过FPGA平台验证并采用IBM 0.18um工艺流片。
本文首先介绍了SoC中的架构设计,概述了SoC中的软硬件结构,包括处理器、片上总线等等。然后结合ASIC设计方法对RTL设计、逻辑综合方法进行了较为深入的研究,同时对CPU的设计方法进行了一定的研究。最后通过研究生阶段的项目80C51软核的设计及应用说明了IC设计的流程及8位CPU软核的设计与应用。
本论文的主要研究结果为:
1、深入研究了当前IC前端设计的方法,包括RTL设计、逻辑综合和验证等。
2、研究了8位CPU软核的设计方法。
3、详细研究了80C51软核设计改进方法和验证方法
4、详细研究了片上心率系统的设计和验证方法。
As the development of IC manufacture technology, IC design has stepped in SoC period. SoC can intergrate on a whole system, including software and hardware, into a single chip, so design complexity is increased and new design methodologies are developed. SoC design relates to many subjects such as computer system structure, embedded system, IP design and reuse and so on. IP design and reuse methodologies are very important because SoC design is based on IP.
8-bit SCM (Single Chip Micyoco) is wildly used in industry control, communication fields because of the characteristic of flexity, credibility, simplicity and so on. Structures, speed, power and instructions of SCM are also improved during the 20 year development, such as using RISC instructions. 8-bit CPU IP based on 8-bit SCM structure is also being more and more wildly used is SoC design. 8 bit CPU IP can be used as main operation and control unit in SoCs which have simple structure or less processing function, and as data transmission and communication control unit in complex SoC.
Design and application of 8-bit CPU soft-IP are selected as research objects and IP design methodolgies and SoC design theories are studied in this paper. The research is based on project of 80C51 soft-IP design and application. In this project, 80C51 soft-IP is improved and verified, and similar to SCM applications, Heart-rate-dectect SoC is designed as an IP application. Many IC and software design aspects are involved andsome SoC design methodolges are used in the design process. The design has been verified on FPGA platform and taped out using IBM 0.18um technology.
In this paper, SoC architecture design is firstly introduced, some basic concepts and methods, such as hardware and software architecture, processor cores, bus-on-chip, are referred. Secondly, based on ASIC design, RTL design and logic synthesis methods are studied, at the same time, CPU design methods are also studied and presented. At last, a graduate project, 80C51 IP core redesign and application, is presented and analyzed to show the IC design flow and 8-bit CPU IP design and reuse.
The main results of paper are list below:
1. IC front design flow, including RTL design, logic synthesis and design verification and so on, is studied.
2. 8-bit CPU IP design methods are studied.
3. 80C51 IP core redesign and verification methods are studied in detail.
4. Heart-rate-detect SoC design and verification methods are studied and presented.
引文
[1]郭炜,郭筝,谢憬.SoC设计方法与实现.北京.电子工业出版社.2007.37-41.
[2]郭兵,沈艳,林永宏等.SoC技术原理与应用.北京.清华大学出版社.2006.183-187
[3]AMBA Specification Rev2.www.arm.com.1999
[4]CoreConnect Bus Architecure.www.ibm.com.2001
[5]Wishbone.System on chip Interconnection Architecture for Portable IP Cores.www opencore org.2002
[6]马光胜,冯刚.SoC设计与IP核重用技术.北京.国防工业出版社.2006.48-50
[7]Cris Rowen 著.吴武臣,侯立刚译.复杂SoC设计.北京.机械工业出版社.2006.64
[8]Jan M.Rabaey,Anantha Chandrakasa 等著.周润德等译.数字集成电路--电路、系统与设计.第二版.北京.电子工业出版社.2006.434-437
[9]Zainalabedin Navabi著.夏宇闻改编.Verilog数字系统设计--RTL综合、测试平台与验证.第二版.北京.电子工业出版社.2007.224-227
[10]Synopsys,Inc.Guide to HDL Coding Styles for Synthesis.Version W-2004.12.2004.28-30
[11]Clifford E.Cummings.Nonblocking Assignments in Verilog Synthesis,Coding Styles That Kill!.SNUG San Jose,2000.22
[12]Clifford E.Cummings.Coding and Scripting Techniques For FSM Designs With Synthesis -Optimized,Glitch-Free Outputs.SNUG Boston,2000.2-4
[13]Clifford E.Cummings.Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs.SNUG San Jose,2001.8-10
[14]Clifford E.Cummings.Synchronous Resets? Asynchronous Resets? I am so confused!How will I ever know which to use?.SNUG San Jose,2002.14-16
[15]MCS@51 MICROCONTROLLER FAMILY USER'S MANUAL.www.intel.com
[16]何琨.SoC中的8位CPU嵌入式结构研究[学位论文].北京.北京交通大学.2004.23-24
[17]王志华,邓仰东.数字集成系统的结构化设计与高层次综合.北京.清华大学出版社.2000.143
[18]David A.Patterson,John L.Hennessy 著.郑纬民 等译.计算机组成和设计--硬件/软件接口.第二版.北京.清华大学出版社.2003.310-318
[19]Synopsys,Inc.Design Compiler User Guide.Version W-2004.12.2004.56
[20]Himanshu Bhatnagar 著.张文俊译.高级ASIC芯片综合.第二版.北京.清华大学出版社.2007.78-83
[21]唐杉,徐强,王莉薇.数字IC设计--方法、技巧与实践.北京.机械工业出版社.2006.277-282
[22]oc8051 Design Document.Rev.0.2.www.opencores.org.34
[23]王诚,吴继华,范丽珍,薛宁,薛小刚.Altera FPGA/CPLD设计(基础篇).北京.人民邮电出版社.2005.129-131
[2]郭兵,沈艳,林永宏等.SoC技术原理与应用.北京.清华大学出版社.2006.183-187
[3]AMBA Specification Rev2.www.arm.com.1999
[4]CoreConnect Bus Architecure.www.ibm.com.2001
[5]Wishbone.System on chip Interconnection Architecture for Portable IP Cores.www opencore org.2002
[6]马光胜,冯刚.SoC设计与IP核重用技术.北京.国防工业出版社.2006.48-50
[7]Cris Rowen 著.吴武臣,侯立刚译.复杂SoC设计.北京.机械工业出版社.2006.64
[8]Jan M.Rabaey,Anantha Chandrakasa 等著.周润德等译.数字集成电路--电路、系统与设计.第二版.北京.电子工业出版社.2006.434-437
[9]Zainalabedin Navabi著.夏宇闻改编.Verilog数字系统设计--RTL综合、测试平台与验证.第二版.北京.电子工业出版社.2007.224-227
[10]Synopsys,Inc.Guide to HDL Coding Styles for Synthesis.Version W-2004.12.2004.28-30
[11]Clifford E.Cummings.Nonblocking Assignments in Verilog Synthesis,Coding Styles That Kill!.SNUG San Jose,2000.22
[12]Clifford E.Cummings.Coding and Scripting Techniques For FSM Designs With Synthesis -Optimized,Glitch-Free Outputs.SNUG Boston,2000.2-4
[13]Clifford E.Cummings.Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs.SNUG San Jose,2001.8-10
[14]Clifford E.Cummings.Synchronous Resets? Asynchronous Resets? I am so confused!How will I ever know which to use?.SNUG San Jose,2002.14-16
[15]MCS@51 MICROCONTROLLER FAMILY USER'S MANUAL.www.intel.com
[16]何琨.SoC中的8位CPU嵌入式结构研究[学位论文].北京.北京交通大学.2004.23-24
[17]王志华,邓仰东.数字集成系统的结构化设计与高层次综合.北京.清华大学出版社.2000.143
[18]David A.Patterson,John L.Hennessy 著.郑纬民 等译.计算机组成和设计--硬件/软件接口.第二版.北京.清华大学出版社.2003.310-318
[19]Synopsys,Inc.Design Compiler User Guide.Version W-2004.12.2004.56
[20]Himanshu Bhatnagar 著.张文俊译.高级ASIC芯片综合.第二版.北京.清华大学出版社.2007.78-83
[21]唐杉,徐强,王莉薇.数字IC设计--方法、技巧与实践.北京.机械工业出版社.2006.277-282
[22]oc8051 Design Document.Rev.0.2.www.opencores.org.34
[23]王诚,吴继华,范丽珍,薛宁,薛小刚.Altera FPGA/CPLD设计(基础篇).北京.人民邮电出版社.2005.129-131
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