低压低功耗高精度基准源研究
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摘要
基准电压源电路是模拟集成电路中一个非常重要的模块,被广泛地应用在诸如模拟/数字转换器(A/D Converter),数字/模拟转换器(D/A Converter),电源控制电路(Power management circuit)以及存储器(Memories)等电路中。近年来随着便携式电子系统的普遍应用,对模数转换器的功耗、速度和精度提出了更高的要求。本文设计了一个应用在12bit 100Msps Pipelined ADC中的基准电压源,采用CMOS0.18μm、1.8V工艺,要求基准源在-40℃到85℃的温度范围内温度系数小于6.84ppm/℃,随电源电压(1.5V-2.1V)的变化小于1860ppm/V。
本文首先介绍了带隙基准电压源的各项指标和基本原理,分析了传统带隙基准源(BGR)结构的缺点和不足。在此基础上,利用寄生PNP管的有限增益以及放大系数β的非线性,提出了一个新型的基于电流模式的凹凸曲线补偿技术实现方式,从而实现了低压下的高阶温度补偿,并采用共源共栅结构提高电源电压抑制比。功耗与面积之间存在折衷,为实现低功耗,不可避免地增加了芯片面积,采用Y网络等效网络可以有效降低这一影响。仔细分析了运算放大器对带隙的影响,设计了一个高增益的两级运算放大器。
在输出缓冲器设计过程中,首先分析了带隙基准直接输出将遇到的问题,通过建立基准输出在中的等效模型,得出了缓冲器单位增益带宽和跨导与PipelinedADC速度和精度的关系。设计得到的缓冲器,不仅温度系数低,而且能够很好地抑制噪声。
使用CMOS 0.18μm的工艺库,在Cadence仿真环境下进行了电路仿真。仿真结果表明,-40℃到85℃温度范围内,基准源温度系数为1.77ppm/℃;在1.5V-2.1V电源电压范围内电源电压调整率为864.1ppm/V;室温25℃下,电源电压抑制比为-63dB,启动时间为61ns。随着工艺角的变化,在1.8V工作电源下,本模块消耗的最大功耗为0.65mW,最小功耗为0.46mW。整个电路设计符合项目总体设计要求。
The bandgap voltage reference circuit is a very important block in analog integrated circuits, which is applied widely in Analog to Digital Converter (ADC), Digital to Analog Converter (DAC), Power management circuits and memories. With the popular use of electronic system powered by battery, the power dissipation, speed and precision of ADC are more important. Based on CMOS 0.18μm and 1.8V power supply process, a bandgap voltage reference circuit applied in 12bit, 100Msps pipelined ADC is investigated and designed. In order to satisfy the requirement of the ADC, the temperature coefficient with the temperature (-40℃～85℃) must be less than 6.84ppm/℃, and the variation with the supply voltage(1.6V～2.1V) must be less than 1860ppm/℃.
This paper presents a general introduction on the bandgap reference firstly, including its performances and principle. A novel curvature-compensated CMOS Bandgap Voltage Reference, which utilizes two first order temperature compensations generated from the nonlinearity of the finite current gainβof vertical PNP bipolar transistor, is presented. This reference is suitable for low voltage by exploiting the superposition of curvature-down and curvature-up currents, which uses a cascode structure to improve the high power supply rejection ratio (PSRR). This is significant in low power applications where resistors need to be large. Thus, a resistive Y-network is utilized to reduce the area. The influence of operation amplifier on voltage reference is analyzed, and at the same time, a high gain two stage operation amplifier is designed.
During the design, the application of voltage reference circuits is analyzed, a model for voltage reference in ADC is proposed and the relationship between the buffer's gain-bandwidth, transconductance and the speed, resolution of ADC is obtained. The designed buffer has both a low temperature coefficient and a capability of rejecting high frequency noise.
The circuit is simulated with the simulation tool of Cadence. The variation of the output voltage with temperature (-40℃～85℃) is 1.77ppm/℃,and with power supply between 1.5V and 2.1V is less than 864.1ppm/V. At the room temperature (25℃), its PSRR is about 63dB and the start-up time is 61ns. Under 1.5V to 2.1V power supply, the output change of voltage is 0.43mV/V. As the process corners vary, the power consumption is 0.65mW at most and 0.46mW at least, under the condition of 1.8V power supply. The whole circuit design fulfils the requirements of the program mentioned above.
本文首先介绍了带隙基准电压源的各项指标和基本原理,分析了传统带隙基准源(BGR)结构的缺点和不足。在此基础上,利用寄生PNP管的有限增益以及放大系数β的非线性,提出了一个新型的基于电流模式的凹凸曲线补偿技术实现方式,从而实现了低压下的高阶温度补偿,并采用共源共栅结构提高电源电压抑制比。功耗与面积之间存在折衷,为实现低功耗,不可避免地增加了芯片面积,采用Y网络等效网络可以有效降低这一影响。仔细分析了运算放大器对带隙的影响,设计了一个高增益的两级运算放大器。
在输出缓冲器设计过程中,首先分析了带隙基准直接输出将遇到的问题,通过建立基准输出在中的等效模型,得出了缓冲器单位增益带宽和跨导与PipelinedADC速度和精度的关系。设计得到的缓冲器,不仅温度系数低,而且能够很好地抑制噪声。
使用CMOS 0.18μm的工艺库,在Cadence仿真环境下进行了电路仿真。仿真结果表明,-40℃到85℃温度范围内,基准源温度系数为1.77ppm/℃;在1.5V-2.1V电源电压范围内电源电压调整率为864.1ppm/V;室温25℃下,电源电压抑制比为-63dB,启动时间为61ns。随着工艺角的变化,在1.8V工作电源下,本模块消耗的最大功耗为0.65mW,最小功耗为0.46mW。整个电路设计符合项目总体设计要求。
The bandgap voltage reference circuit is a very important block in analog integrated circuits, which is applied widely in Analog to Digital Converter (ADC), Digital to Analog Converter (DAC), Power management circuits and memories. With the popular use of electronic system powered by battery, the power dissipation, speed and precision of ADC are more important. Based on CMOS 0.18μm and 1.8V power supply process, a bandgap voltage reference circuit applied in 12bit, 100Msps pipelined ADC is investigated and designed. In order to satisfy the requirement of the ADC, the temperature coefficient with the temperature (-40℃～85℃) must be less than 6.84ppm/℃, and the variation with the supply voltage(1.6V～2.1V) must be less than 1860ppm/℃.
This paper presents a general introduction on the bandgap reference firstly, including its performances and principle. A novel curvature-compensated CMOS Bandgap Voltage Reference, which utilizes two first order temperature compensations generated from the nonlinearity of the finite current gainβof vertical PNP bipolar transistor, is presented. This reference is suitable for low voltage by exploiting the superposition of curvature-down and curvature-up currents, which uses a cascode structure to improve the high power supply rejection ratio (PSRR). This is significant in low power applications where resistors need to be large. Thus, a resistive Y-network is utilized to reduce the area. The influence of operation amplifier on voltage reference is analyzed, and at the same time, a high gain two stage operation amplifier is designed.
During the design, the application of voltage reference circuits is analyzed, a model for voltage reference in ADC is proposed and the relationship between the buffer's gain-bandwidth, transconductance and the speed, resolution of ADC is obtained. The designed buffer has both a low temperature coefficient and a capability of rejecting high frequency noise.
The circuit is simulated with the simulation tool of Cadence. The variation of the output voltage with temperature (-40℃～85℃) is 1.77ppm/℃,and with power supply between 1.5V and 2.1V is less than 864.1ppm/V. At the room temperature (25℃), its PSRR is about 63dB and the start-up time is 61ns. Under 1.5V to 2.1V power supply, the output change of voltage is 0.43mV/V. As the process corners vary, the power consumption is 0.65mW at most and 0.46mW at least, under the condition of 1.8V power supply. The whole circuit design fulfils the requirements of the program mentioned above.
引文
[1].I.Mehr,L.Singer.A 55-mW 10-bit 40-Msample/s Nyquist-rate CMOS ADC.IEEE Journal of Solid-State Circuits,2000,vol.35:318-325
[2].S.H.Lewis,P.R.Gray.A Pipelined 5-Msample/s 9-bit analog-to-digital converter.IEEE Journal of Solid-State Circuits,1987,vol.22:954-961
[3].P.E.Allen,R.H.Douglas.CMOS Analog Circuits Design.Bejing:Publishing House of Electronics Industry,2002,1-2
[4].F.Christian,S.Stephen.Novel Approach to Low-Voltage Low-Power Bandgap Reference Voltage in Standard CMOS Process.IEEE Journal of Solid-State Circuits,2006,208-211
[5].H.Peter,P.Fabrice,T.M.Sung.Low Voltage Buffered Bandgap Reference.Proceedings of the 2007 IEEE International Symposium on Quality Electronic Design,2007
[6].C.W.Chang,T.Y.Lo,C.C.Hung.A Low-Power CMOS Voltage Reference Circuit Based On Sub-threshold Operation.IEEE Journal of Solid-State Circuits,2007,3844-3847
[7].G.Made,C.M.Gerard,F.Jeroen,H.H.Johan.A curvature-corrected low-voltage bandgap reference.IEEE Journal of Solid-State Circuits,1993,vol.28:667-670
[8].Inyeol Lee,Gyudong Kim,Wonchan Kim.Exponential curvature-compensated BiCMOS bandgap references.IEEE Journal of Solid-State Circuits,1994,vol.29:1396-1403
[9].A.Gabriel,R.Mora,P.E.Allen.A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Badgap Reference.IEEE Journal of Solid-State Circuits,1998,vol.33:1551-1554
[10].Ming-Dou Ker,Jung-Sheng Chen.New Curvature-Compensation Technique for CMOS Bandgap Reference with Sub-1-V Operation.IEEE Transactions on circuits and systems,2006,vol.53:667-671
[11].G.C.Vijaya,Ceekala,D.L.Lawrence,B.W.James,Devnath Varadarajan,Jitendra Mohan.A method for reducing the effects of random mismatches in CMOS bandgap references.Proceedings of 2002 IEEE International Solid-State Circuits Conference,2002
[12].H.Atrash,Arlo Aude."A bandgap reference circuit utilizing switching to reduce offsets and a novel technique for leakage current compensation." IEEE Journal of Solid-State Circuits,2004,297-300
[13].Chen-chang Zhan,Wei Wang,Xiao-fang Zhou,Dian Zhou.A New Bandgap Reference for High-Resolution Data Converters.Proceedings of the 2007 IEEEInternational Conference on Integration Technology.Shenzhen:2007,20-24
[14].S.Mehrmanesh,M.B.Vahidfar,H.A.Aslanzadeh,M.Atarodi.A 1-V high PSRR CMOS bandgap voltage reference.IEEE Journal of Solid-State Circuits,2003,381-384
[15].刘鸿雁,来新泉.一款超低噪声快速启动的CMOS带隙基准电路设计.电子工程师,2006,32:5-8
[16].宋浩然.用于Pipeline ADC的参考电压和参考电流的电路系统.世界电子元器件,2006,4:57-60
[17].Yun Chin.High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS:[Ph.D dissertation].Berkeley USA:University of California,2004
[18].Y.I.Park,Karthikeyan.A low power 10 bit,80 MS/s CMOS pipelined ADC at 1.8 V power supply.Proceedings of the 2001 IEEE International Symposium on Quality Electronic Design,2001,vol.1:580-583
[19].刘剑.影响基准源性能的因素研究:[硕士学位论文].成都:电子科技大学大学,2005,6-9
[20].毕查德.拉扎维.模拟CMOS集成电路设计(陈贵灿).西安:西安交通大学出版社,2003,309-324
[21].Y.P.Tsividis.Accurate analysis of temperature effects in I_C-V_(BE) characteristics with application to bandgap reference sources.IEEE Journal of Solid-State Circuits,1980,vol.15:1076-1084
[22].D.F.Hilbiber.A New Semiconductor Voltage Standard.Proceedings of the 1964 IEEE International Solid-State Circuits Conference,1964,vol.7:32-33
[23].W.Bludau,A.Onton,W.Heinke.Temperature dependence of bandgap of silicon.J.Appl.Phys,1974,vol.45:1846-1848
[24].P.R.Gray,P.J.Hurst,S.H.Lewis,et al.Analysis and Design of Analog Integrated Circuits.北京:高等教育出版社,2003,22-431
[25].Andrea Boni.Op-amps and startup circuits for CMOS bandgap references with near 1-V supply.IEEE Journal of Solid-State Circuits,2003,vol.37:1339-1343
[26].丁家平.高速高精度ADC中基准电压源的研究与设计:[硕士学位论文].南京:东南大学,2006,31-32
[2].S.H.Lewis,P.R.Gray.A Pipelined 5-Msample/s 9-bit analog-to-digital converter.IEEE Journal of Solid-State Circuits,1987,vol.22:954-961
[3].P.E.Allen,R.H.Douglas.CMOS Analog Circuits Design.Bejing:Publishing House of Electronics Industry,2002,1-2
[4].F.Christian,S.Stephen.Novel Approach to Low-Voltage Low-Power Bandgap Reference Voltage in Standard CMOS Process.IEEE Journal of Solid-State Circuits,2006,208-211
[5].H.Peter,P.Fabrice,T.M.Sung.Low Voltage Buffered Bandgap Reference.Proceedings of the 2007 IEEE International Symposium on Quality Electronic Design,2007
[6].C.W.Chang,T.Y.Lo,C.C.Hung.A Low-Power CMOS Voltage Reference Circuit Based On Sub-threshold Operation.IEEE Journal of Solid-State Circuits,2007,3844-3847
[7].G.Made,C.M.Gerard,F.Jeroen,H.H.Johan.A curvature-corrected low-voltage bandgap reference.IEEE Journal of Solid-State Circuits,1993,vol.28:667-670
[8].Inyeol Lee,Gyudong Kim,Wonchan Kim.Exponential curvature-compensated BiCMOS bandgap references.IEEE Journal of Solid-State Circuits,1994,vol.29:1396-1403
[9].A.Gabriel,R.Mora,P.E.Allen.A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Badgap Reference.IEEE Journal of Solid-State Circuits,1998,vol.33:1551-1554
[10].Ming-Dou Ker,Jung-Sheng Chen.New Curvature-Compensation Technique for CMOS Bandgap Reference with Sub-1-V Operation.IEEE Transactions on circuits and systems,2006,vol.53:667-671
[11].G.C.Vijaya,Ceekala,D.L.Lawrence,B.W.James,Devnath Varadarajan,Jitendra Mohan.A method for reducing the effects of random mismatches in CMOS bandgap references.Proceedings of 2002 IEEE International Solid-State Circuits Conference,2002
[12].H.Atrash,Arlo Aude."A bandgap reference circuit utilizing switching to reduce offsets and a novel technique for leakage current compensation." IEEE Journal of Solid-State Circuits,2004,297-300
[13].Chen-chang Zhan,Wei Wang,Xiao-fang Zhou,Dian Zhou.A New Bandgap Reference for High-Resolution Data Converters.Proceedings of the 2007 IEEEInternational Conference on Integration Technology.Shenzhen:2007,20-24
[14].S.Mehrmanesh,M.B.Vahidfar,H.A.Aslanzadeh,M.Atarodi.A 1-V high PSRR CMOS bandgap voltage reference.IEEE Journal of Solid-State Circuits,2003,381-384
[15].刘鸿雁,来新泉.一款超低噪声快速启动的CMOS带隙基准电路设计.电子工程师,2006,32:5-8
[16].宋浩然.用于Pipeline ADC的参考电压和参考电流的电路系统.世界电子元器件,2006,4:57-60
[17].Yun Chin.High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS:[Ph.D dissertation].Berkeley USA:University of California,2004
[18].Y.I.Park,Karthikeyan.A low power 10 bit,80 MS/s CMOS pipelined ADC at 1.8 V power supply.Proceedings of the 2001 IEEE International Symposium on Quality Electronic Design,2001,vol.1:580-583
[19].刘剑.影响基准源性能的因素研究:[硕士学位论文].成都:电子科技大学大学,2005,6-9
[20].毕查德.拉扎维.模拟CMOS集成电路设计(陈贵灿).西安:西安交通大学出版社,2003,309-324
[21].Y.P.Tsividis.Accurate analysis of temperature effects in I_C-V_(BE) characteristics with application to bandgap reference sources.IEEE Journal of Solid-State Circuits,1980,vol.15:1076-1084
[22].D.F.Hilbiber.A New Semiconductor Voltage Standard.Proceedings of the 1964 IEEE International Solid-State Circuits Conference,1964,vol.7:32-33
[23].W.Bludau,A.Onton,W.Heinke.Temperature dependence of bandgap of silicon.J.Appl.Phys,1974,vol.45:1846-1848
[24].P.R.Gray,P.J.Hurst,S.H.Lewis,et al.Analysis and Design of Analog Integrated Circuits.北京:高等教育出版社,2003,22-431
[25].Andrea Boni.Op-amps and startup circuits for CMOS bandgap references with near 1-V supply.IEEE Journal of Solid-State Circuits,2003,vol.37:1339-1343
[26].丁家平.高速高精度ADC中基准电压源的研究与设计:[硕士学位论文].南京:东南大学,2006,31-32
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