基于Spartan-3 FPGA的DDR2 SDRAM存储器接口设计
摘要
内部存储器(简称内存)负责计算机系统内部数据的中转、存储与读取,作为计算机系统中必不可少的三大件之一(其余的两个是主板与CPU),它对计算机系统性能至关重要。内存可以说是CPU处理数据的“大仓库”,所有经过CPU处理的指令和数据都要经过内存传递到电脑其他配件上,因此内存性能的好坏,直接影响到系统的稳定性和运行性能。
在当今的电子系统设计中,内存被使用得越来越多,并且对内存的要求越来越高。既要求内存读写速度尽可能的快、容量尽可能的大,同时由于竞争的加剧以及利润率的下降,人们希望在保持、甚至提高系统性能的同时也能降低内存产品的成本。面对这种趋势,设计和实现大容量高速读写的内存显得尤为重要。因此,近年来内存产品正经历着从小容量到大容量、从低速到高速的不断变化,从技术上也就有了从DRAM到SDRAM,再到DDR SDRAM及DDR2 SDRAM等的不断演进。和普通SDRAM的接口设计相比,DDR2 SDRAM存储器在获得大容量和高速率的同时,对存储器的接口设计也提出了更高的要求,其接口设计复杂度也大幅增加。一方面,由于I/O块中的资源是有限的,数据多路分解和时钟转换逻辑必须在FPGA核心逻辑中实现,设计者可能不得不对接口逻辑进行手工布线以确保临界时序。而另一方面,不得不处理好与DDR2接口有关的时序问题(包括温度和电压补偿)。要正确的实现DDR2接口需要非常细致的工作,并在提供设计灵活性的同时确保系统性能和可靠性。
本文对通过Xilinx的Spartan3 FPGA实现DDR2内存接口的设计与实现进行了详细阐述。通过Xilinx FPGA提供了I/O模块和逻辑资源,从而使接口设计变得更简单、更可靠。本设计中对I/O模块及其他逻辑在RTL代码中进行了配置、严整、执行,并正确连接到FPGA上,经过仔细仿真,然后在硬件中验证,以确保存储器接口系统的可靠性。
The inner memory is in charge of the data transfer,storage and read/write in the computer system, as one of the three most important parts of the computer system (the other two are main-board and CPU), it plays great role in computer systems. Allegorically the inner memory is the“big storehouse”of the CPU data processing, all the instructions and data processed by CPU must be transferred by inner memory to the other parts of computer system. So that the performance of the inner memory will heavily impact the stability and running performance of computer system.
In current electronics system designing, inner memory is used more and more broadly, meanwhile we are expecting more and more from the inner memory. It’s required to be read/written more quickly, larger in capacity and lower cost as the marketing competent is more and more tight, while keeping the same or seeking higher performance. With this trend, the design and implementation of inner memory with large capacity and high speed are very important. In recent years, the inner memory products evolved from small capacity to big capacity, from low speed to high speed. From the technology point of view, it evolved from DRAM to SDRAM and then DDR SDRAM and DDR2 SDRAM. Compared with the normal SDRAM, the interface design of DDR2 SDRAM is much more complicated as the capacity and speed are increased significantly. On the one hand, as the I/O module resource is limited, the data multiplex and clock transferring must be implemented in the core logic bank of FPGA, the designer have to draw schematic by hand to ensure critical clock scheduling for the interface. On the other hand, we have to pay much attention to the time clock issues (including temperature and voltage compensation) related to the DDR2 interface. To implementing the DDR2 interface correctly, much careful work is needed and the compatibility design is needed to ensure the performance and stability of the system.
The thesis is the implementation of DDR2 memory interface based on Spartan-3 FPGA of Xilinx corporation. Xilinx FPGA provides I/O blocks and logic resources that make the interface design easier and more reliable. The I/O blocks, along with the logic modules are configured, verified, implemented and properly connected to FPGA in the RTL code, carefully simulated and then verified in hardware to ensure a reliable memory interface system.
在当今的电子系统设计中,内存被使用得越来越多,并且对内存的要求越来越高。既要求内存读写速度尽可能的快、容量尽可能的大,同时由于竞争的加剧以及利润率的下降,人们希望在保持、甚至提高系统性能的同时也能降低内存产品的成本。面对这种趋势,设计和实现大容量高速读写的内存显得尤为重要。因此,近年来内存产品正经历着从小容量到大容量、从低速到高速的不断变化,从技术上也就有了从DRAM到SDRAM,再到DDR SDRAM及DDR2 SDRAM等的不断演进。和普通SDRAM的接口设计相比,DDR2 SDRAM存储器在获得大容量和高速率的同时,对存储器的接口设计也提出了更高的要求,其接口设计复杂度也大幅增加。一方面,由于I/O块中的资源是有限的,数据多路分解和时钟转换逻辑必须在FPGA核心逻辑中实现,设计者可能不得不对接口逻辑进行手工布线以确保临界时序。而另一方面,不得不处理好与DDR2接口有关的时序问题(包括温度和电压补偿)。要正确的实现DDR2接口需要非常细致的工作,并在提供设计灵活性的同时确保系统性能和可靠性。
本文对通过Xilinx的Spartan3 FPGA实现DDR2内存接口的设计与实现进行了详细阐述。通过Xilinx FPGA提供了I/O模块和逻辑资源,从而使接口设计变得更简单、更可靠。本设计中对I/O模块及其他逻辑在RTL代码中进行了配置、严整、执行,并正确连接到FPGA上,经过仔细仿真,然后在硬件中验证,以确保存储器接口系统的可靠性。
The inner memory is in charge of the data transfer,storage and read/write in the computer system, as one of the three most important parts of the computer system (the other two are main-board and CPU), it plays great role in computer systems. Allegorically the inner memory is the“big storehouse”of the CPU data processing, all the instructions and data processed by CPU must be transferred by inner memory to the other parts of computer system. So that the performance of the inner memory will heavily impact the stability and running performance of computer system.
In current electronics system designing, inner memory is used more and more broadly, meanwhile we are expecting more and more from the inner memory. It’s required to be read/written more quickly, larger in capacity and lower cost as the marketing competent is more and more tight, while keeping the same or seeking higher performance. With this trend, the design and implementation of inner memory with large capacity and high speed are very important. In recent years, the inner memory products evolved from small capacity to big capacity, from low speed to high speed. From the technology point of view, it evolved from DRAM to SDRAM and then DDR SDRAM and DDR2 SDRAM. Compared with the normal SDRAM, the interface design of DDR2 SDRAM is much more complicated as the capacity and speed are increased significantly. On the one hand, as the I/O module resource is limited, the data multiplex and clock transferring must be implemented in the core logic bank of FPGA, the designer have to draw schematic by hand to ensure critical clock scheduling for the interface. On the other hand, we have to pay much attention to the time clock issues (including temperature and voltage compensation) related to the DDR2 interface. To implementing the DDR2 interface correctly, much careful work is needed and the compatibility design is needed to ensure the performance and stability of the system.
The thesis is the implementation of DDR2 memory interface based on Spartan-3 FPGA of Xilinx corporation. Xilinx FPGA provides I/O blocks and logic resources that make the interface design easier and more reliable. The I/O blocks, along with the logic modules are configured, verified, implemented and properly connected to FPGA in the RTL code, carefully simulated and then verified in hardware to ensure a reliable memory interface system.
引文
[1] 赵雅兴,“FPGA 原理及应用”,天津大学出版社,1999
[2] Micron Corporation,“DDR2 Datasheet”,2005
[3] Xilinx Corporation,“Spartan-3 Complete Data Sheet”,April 2006
[4] Xilinx Corporation,“Spartan-3 Generation Configuration User Guide”2006
[5] Xilinx Corporation,“Spartan-3 Generation FPGA User Guide”2006
[6] Howard W.Johnson,PHD.,Martin Graham,PHD.,“HIGH-SPEED DIGITAL DESIGN---A Handbook of Black Magic”,2001
[7] Clifford E.Cummings,“Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs”,2001
[8] J.BHASKER,“Verilog HDL Syntesis---A Practical Primer”,1998
[9] 边计年,薛宏熙,“用 VHDL 设计电子线路”,北京:清华大学出版社,2000
[10] Samir Palnitkar, “ Verilog HDL, A Guide to Digital Design and Synthesis”,Sunsoft Press A Prentice Hall Title,1996
[11] Veendrick,Harry J.M.,“The Behavior of Flip-Flop Used as Synchronizers and Prediction of Their Failure Rate ” ,IEEE Journal of Solid-State Circuits,Vol. SC-15,No.2.,April 1980
[12] E.A.Lee and D.G.Messerschmidt,“Digital Communication”.Norwell,1994
[13] F.Krummenacher and N.Joehl,“A4-MHz CMOS continuous-time filter with on-chip automatic tuning”,IEEE J.Solid-state Circuits,vol23,June 1988
[14] Y.-T.Wang and B.Razavi,“An 8-bit 150-MHz CMOS A/D converter”,IEEE J.Solid-State Circuits,vol.35,Mar 2000
[15]“ TMS626162,TMS626812 16Mb Synchronous DRAMs Technical Reference”, TI Corporation,1996
[16]“ Shared Memory Interface With the TMS320C54x DSP”,TI Corporation,1998
[17] 侯伯亨,顾新著,“VHDL 硬件描述语言与数字逻辑电路设计” 西安电子科技大学出版社,2001
[18] Douglas L. Perry,“电子设计硬件描述语言 VHDL”,北京:学苑出版社,1994
[19] J. Bhasker,“Verilog HDL Synthesis-- A practical Primer”, Star Galaxy Publishing, ISBN
[20] 潘松,黄继业.“EDA 技术实用教程”.北京:科学出版社,2002
[21] 王金明,杨吉斌.“数字系统设计与 Verilog HDL”.北京:电子工业出版社,2002
[22] 黄正瑾.“在系统编程技术及其应用”.南京:东南大学出版社,1997
[23] David Comer Donald Comer, “电子电路设计”, 中国计量出版社,2005
[2] Micron Corporation,“DDR2 Datasheet”,2005
[3] Xilinx Corporation,“Spartan-3 Complete Data Sheet”,April 2006
[4] Xilinx Corporation,“Spartan-3 Generation Configuration User Guide”2006
[5] Xilinx Corporation,“Spartan-3 Generation FPGA User Guide”2006
[6] Howard W.Johnson,PHD.,Martin Graham,PHD.,“HIGH-SPEED DIGITAL DESIGN---A Handbook of Black Magic”,2001
[7] Clifford E.Cummings,“Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs”,2001
[8] J.BHASKER,“Verilog HDL Syntesis---A Practical Primer”,1998
[9] 边计年,薛宏熙,“用 VHDL 设计电子线路”,北京:清华大学出版社,2000
[10] Samir Palnitkar, “ Verilog HDL, A Guide to Digital Design and Synthesis”,Sunsoft Press A Prentice Hall Title,1996
[11] Veendrick,Harry J.M.,“The Behavior of Flip-Flop Used as Synchronizers and Prediction of Their Failure Rate ” ,IEEE Journal of Solid-State Circuits,Vol. SC-15,No.2.,April 1980
[12] E.A.Lee and D.G.Messerschmidt,“Digital Communication”.Norwell,1994
[13] F.Krummenacher and N.Joehl,“A4-MHz CMOS continuous-time filter with on-chip automatic tuning”,IEEE J.Solid-state Circuits,vol23,June 1988
[14] Y.-T.Wang and B.Razavi,“An 8-bit 150-MHz CMOS A/D converter”,IEEE J.Solid-State Circuits,vol.35,Mar 2000
[15]“ TMS626162,TMS626812 16Mb Synchronous DRAMs Technical Reference”, TI Corporation,1996
[16]“ Shared Memory Interface With the TMS320C54x DSP”,TI Corporation,1998
[17] 侯伯亨,顾新著,“VHDL 硬件描述语言与数字逻辑电路设计” 西安电子科技大学出版社,2001
[18] Douglas L. Perry,“电子设计硬件描述语言 VHDL”,北京:学苑出版社,1994
[19] J. Bhasker,“Verilog HDL Synthesis-- A practical Primer”, Star Galaxy Publishing, ISBN
[20] 潘松,黄继业.“EDA 技术实用教程”.北京:科学出版社,2002
[21] 王金明,杨吉斌.“数字系统设计与 Verilog HDL”.北京:电子工业出版社,2002
[22] 黄正瑾.“在系统编程技术及其应用”.南京:东南大学出版社,1997
[23] David Comer Donald Comer, “电子电路设计”, 中国计量出版社,2005