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基于FPGA的数字视频光纤传输系统的设计
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摘要
随着计算机技术和通信技术的迅速发展,数字视频在信息社会中发挥着越来越重要的作用,视频传输系统已经被广泛应用于交通管理、工业监控、广播电视、银行、商场等多个领域。同时,FPGA单片规模的不断扩大,在FPGA芯片内部实现复杂的数字信号处理系统也成为现实,因此采用FPGA实现视频压缩和传输已成为一种最佳选择。
     本文将视频压缩技术和光纤传输技术相结合,设计了一种基于无损压缩算法的多路数字视频光纤传输系统,系统利用时分复用和无损压缩技术,采用串行数字视频传输的方式,可在一根光纤中同时传输8路以上视频信号。系统在总体设计时,确定了基于FPGA的设计方案,采用ADI公司的AD9280和AD9708芯片实现A/D转换和D/A转换,在FPGA里实现系统的时分复用/解复用、视频数据压缩/解压缩和线路码编解码,利用光收发一体模块实现电光转换和光电转换。视频压缩采用LZW无损压缩算法,用Verilog语言设计了压缩模块和解压缩模块,利用Xilinx公司的IP核生成工具Core Generator生成FIFO来缓存压缩/解压缩单元的输入输出数据,光纤线路码采用CIMT码,设计了编解码模块,解码过程中,利用数字锁相环来实现发射与接收的帧同步,在ISE8.2和Modelsim仿真环境下对FPGA模块进行了功能仿真和时序仿真,并在Spartan-3E开发板和视频扩展板上完成了系统的硬件调试与验证工作,实验证明,系统工作稳定,图像清晰,实时传输效果好,可用于交通、安防、工业监控等多个领域。
     本文将视频压缩和线路码编解码在FPGA里实现,利用FPGA的并行处理优势,大大提高了系统的处理速度,使系统具有集成度高、灵活性强、调试方便、抗干扰能力强、易于升级等特点。
With the rapid development of computer and communication technology, digital video plays a more and more important role in information society; video transmission system has been applied to many fields such as industrial surveillance, traffic management, videocast, etc. Meanwhile, the scale of single FPGA continues to expand, the complex digital signal processing system on FPGA has become realizable, and therefore the use of video compression and transmission on FPGA has become an optimum section.
     Combining digital video compression technology with optical fiber transmission, this thesis presents a multichannel digital video transmission system based on LZW compression. Based on video compression technology, time-division multiplexing technology and the serial digital video transmission, the proposed system can transfer eight channels of standard video signal over a single optical fiber. The system adopts a design scheme based on FPGA, The A/D conversion circuit and D/A conversion circuit adopt AD9280 and AD9708 chip, which are high performance from ADI company; the TDMA module, video compression module, video decompression module and line code/decode module are implemented on FPGA; The photo-electric conversion and the electric-photo conversion are implemented by optic transceiver module. The video compression/decompression module is designed by verilog HDL. The input data and output data of compression/decompression module are storaged in FIFO, which is generated by Core Generator. The system adopts CIMT line code, and CIMT code/decode module is designed by verilog HDL. The frame synchronization is realized by digital phase locked loop. The FPGA modules are simulated under ISE8.2 and Modelsim environment and in the end, the whole debugging and testing of system is done using Spartan-3E starter kit board. Experiment demonatrates that the system is stability and has a good effect of real-time transmission. It is a good practical scheme for security and surveillance systems.
     The system processing speed is improved greatly with the advantage of FPGA parallel processing, and the system have many characteristics such as high processing speed, high integrated level and strong antijamming ability.
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