功率集成电路兼容技术的研究
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摘要
在微电子技术和电力电子技术的交叉推动下，功率集成电路(Power Integrated Circuit，简称PIC)得到迅速的发展，其应用领域也在不断扩大，目前已经广泛运用于马达驱动、电源管理、汽车电子和平板显示等领域当中。特别是近几年随着新工艺和新器件的不断出现，PIC也逐步向PSoC(Power System on Chip)方向迈进，但是其成本和工艺复杂度等问题始终限制着PIC的进一步发展。因此，开展功率集成电路兼容技术的相关研究，开发具有自主知识产权的BCD工艺，并研制相应的各类功率集成电路仍有着非常重要的现实意义。
本文围绕着PIC兼容技术及其研发的整个过程，对PIC的工艺流程、器件结构和电路设计等方面展开了一些深入研究。主要工作和创新点有：
1、提出了适用于超高压(＞500V)单片智能功率IC制造的BCD_Z1工艺技术方案。该工艺方案能将无外延的双RESURF结构横向功率LDMOS器件与PWM低压控制器兼容在一起，共同组成PWM开关电源智能功率集成电路。该电路流片结果表明该LDMOS器件性能良好，击穿电压可达700V左右，低压PWM开关电源部分亦工作正常，所有参数均达到设计指标。该PIC芯片的流片成功(在国内未见同水平报导)，验证了BCD_Z1工艺技术方案的正确性与切实可行性。
2、提出了适用于高压(＜200V)、低导通电阻的功率IC制造的BCD_Z2工艺技术方案。该工艺方案能将纵向功率VDMOS器件、电平位移电路和低压控制电路等兼容在一起，共同组成高压平板显示器中的高压驱动集成电路。该工艺流程具有工艺相对简单、工艺层次少和成本低等特点。经过流片和测试表明，不仅所有元器件的性能均能达到预先设定的要求，而且该PDP显示扫描驱动IC的功能和性能全部达到设计指标。该PDP扫描驱动IC的流片成功，也验证了BCD_Z2工艺技术方案的可行性和正确性。
3、为了验证BCD_Z2工艺技术方案的正确性与可行性，开发设计了一种用于PDP显示的扫描驱动IC。该扫描驱动IC实现PDP显示系统所需求的所有功能，能工作在15～160V高压下，并具有相当大的驱动电流能力。在完成电路设计、版图绘制和验证的基础上，进行了流片验证。测试结果表明该扫描驱动IC的所有功能和性能指标均达到了预先设计的要求，最大工作频率达到20MHz。作为检验驱动能力的两个关键参数，它的上升沿和下降沿时间分别为165ns和30ns(高压电源V_(pp)=90V和负载C_L=200pF情况下)。
4、针对BCD_Z2工艺技术方案中出现的HV-VDMOS器件，为了更好的降低其导通电阻，提出了一种计算其导通电阻和特征导通电阻的三维解析模型。由于集成VDMOS器件的漏极要从芯片表面引出，其横向埋层和漏极注入等寄生电阻会对导通电阻产生极大的影响，因而这就需要对VDMOS器件的布局和元胞数做最优化的处理。利用该3D模型，可以很好地预测器件元胞布局和漏极接触边数对特征导通电阻的影响，从而可以计算出限定面积下达到最小导通电阻的最佳元胞数和漏极接触边数以及器件结构布局。
整个论文围绕着PIC兼容技术及其工艺方案实现这一主线，研究提出了两种不同PIC类型的BCD工艺技术方案，并在此基础上成功研制了两种相应类型的PIC芯片。这两种工艺技术方案由于针对的PIC需求不同，其工艺方案也是截然不同的，以此来满足不同PIC对耐电压、电流等特殊的需求，这也一定程度上为PIC设计者提供了选择余地。该类芯片的研制成功，一方面意味着可以打破该类芯片只能依赖进口的落后局面，另一方面意味着具有完全自主知识产权的高压集成电路工艺生产线的国产化也不是不可能的。本文的工作为今后进一步进行PIC工艺和电路国产化研究积累了技术经验，同时通过全方位地对PIC研发整个流程的尝试，为相关技术推广及产业化打下了基础。
Driven by the development of microelectronics technology and powerelectronics, the Power Integrated Circuits (PICs) are booming quickly, and arewidely used in motor drivers, power management, automotive and flat-panel display.Recently, many new technologies and devices are raised and PSoC (Power Systemon Chip) is coming to the fore. However, the further development of the PICs isrestricted by the cost and process complexity of integration. Therefore, it issignificant to do research into the compatibility technology and design flow of PICs,to develop the BCD (Bipolar-CMOS-DMOS) process with our own intellectualproperty (IP) rights and to implement the corresponding power IC chips.
The work of this dissertation is devoted to the research on the compatibilitytechnology and the PIC design flow, including the process flow, device structure andcircuit design. The main contents and innovative points of this dissertation are listedbelow.
A BCD technology scheme named BCD_Z1 is proposed for the manufacture ofmonolithic smart PICs, in which high blocking voltage more than 500V is achieved.In the BCD_Z1 process scheme, the no-epitaxial double-RESURF LDMOS isintegrated with the low-voltage PWM controller to constitute a PWM switch smartpower IC. The test results show that the breakvoltage of the LDMOS is about 700V,and good function and performance of the PWM switch power IC with the LDMOSare achieved. Then the PIC is used in the switch power supply applications, andworks very well. The feasibility and the validity of BCD_Z1 technology scheme areverified.
A BCD technology scheme named BCD_Z2 is proposed for the manufacture ofthe PICs with high blocking voltage below 200V and low on-resistance. In theBCD_Z2 process scheme, the vertical DMOS is integrated with the level-shifter andlow-voltage control circuit, and a high-voltage fiat-display driver IC is implemented.This BCD_Z2 technology scheme further simplifies the process steps, reduces process complexity and cost. The test results show that all the devices implementedwith BCD_Z2 have reached the design specifications and the corresponding PDPscan driver IC is realized. The success of the PDP scan driver IC also confirms thevalidity of the proposed BCD_Z2 technology scheme.
A PDP scan driver IC is designed and implemented to verify the feasibility ofthe BCD_Z2 technology scheme. All of the functions of the PDP system requiredare realized by the PDP scan driver IC. It is able to work under the voltage 15～160V,and also provides high driving current. The PIC is implemented with the BCD_Z2process. The test results show that the functions and performance of this PDP scandriver IC are achieved, and the maximum operational frequency is 20MHz. As thekey parameters estimating the driving capability, the rising and falling time are165ns and 30ns under test conditions of V_(pp)=90V and C_L=200pF, respectively.
An in-depth study is carded out to reduce the on-resistance of the integratedVertical DMOS in the BCD_Z2 technology scheme. A 3-dimension analytical modelis proposed to calculate its on-resistance and specific on-resistance. Since all thecontacts of the integrated VDMOS are on the top side of the chip, the calculationand characteristic of its on-resistance are not identical with the conventionalVDMOS. The on-resistance of an integrated VDMOS varies with the placement andthe number of source cells. So the cell layout and the side number of drain contactsneed to be considered in the design of the integrated VDMOS. Using this model, theoptimal layout of the integrated VDMOS with a minimal specific on-resistance canbe achieved within a limited chip area, and the corresponding number of cells M×Nand side number of drain contacts can be calculated.
The work of this dissertation is focused on the PIC compatibility technologyand the corresponding design realization. It provides two different BCD technologyschemes for PIC design, and two corresponding PIC chips are designed andmanufactured. The two technology schemes are distinct obviously for differentapplications, and they provide some degrees of freedom of the PIC design. Thesuccess of two BCD process indicates that the domestic manufacture of BCD process with our own intellectual property rights is realizable. The work of thisdissertation provides some experiments for further PIC process and circuitryresearch, and also makes some preparation for technology transfer andindustrialization.
本文围绕着PIC兼容技术及其研发的整个过程，对PIC的工艺流程、器件结构和电路设计等方面展开了一些深入研究。主要工作和创新点有：
1、提出了适用于超高压(＞500V)单片智能功率IC制造的BCD_Z1工艺技术方案。该工艺方案能将无外延的双RESURF结构横向功率LDMOS器件与PWM低压控制器兼容在一起，共同组成PWM开关电源智能功率集成电路。该电路流片结果表明该LDMOS器件性能良好，击穿电压可达700V左右，低压PWM开关电源部分亦工作正常，所有参数均达到设计指标。该PIC芯片的流片成功(在国内未见同水平报导)，验证了BCD_Z1工艺技术方案的正确性与切实可行性。
2、提出了适用于高压(＜200V)、低导通电阻的功率IC制造的BCD_Z2工艺技术方案。该工艺方案能将纵向功率VDMOS器件、电平位移电路和低压控制电路等兼容在一起，共同组成高压平板显示器中的高压驱动集成电路。该工艺流程具有工艺相对简单、工艺层次少和成本低等特点。经过流片和测试表明，不仅所有元器件的性能均能达到预先设定的要求，而且该PDP显示扫描驱动IC的功能和性能全部达到设计指标。该PDP扫描驱动IC的流片成功，也验证了BCD_Z2工艺技术方案的可行性和正确性。
3、为了验证BCD_Z2工艺技术方案的正确性与可行性，开发设计了一种用于PDP显示的扫描驱动IC。该扫描驱动IC实现PDP显示系统所需求的所有功能，能工作在15～160V高压下，并具有相当大的驱动电流能力。在完成电路设计、版图绘制和验证的基础上，进行了流片验证。测试结果表明该扫描驱动IC的所有功能和性能指标均达到了预先设计的要求，最大工作频率达到20MHz。作为检验驱动能力的两个关键参数，它的上升沿和下降沿时间分别为165ns和30ns(高压电源V_(pp)=90V和负载C_L=200pF情况下)。
4、针对BCD_Z2工艺技术方案中出现的HV-VDMOS器件，为了更好的降低其导通电阻，提出了一种计算其导通电阻和特征导通电阻的三维解析模型。由于集成VDMOS器件的漏极要从芯片表面引出，其横向埋层和漏极注入等寄生电阻会对导通电阻产生极大的影响，因而这就需要对VDMOS器件的布局和元胞数做最优化的处理。利用该3D模型，可以很好地预测器件元胞布局和漏极接触边数对特征导通电阻的影响，从而可以计算出限定面积下达到最小导通电阻的最佳元胞数和漏极接触边数以及器件结构布局。
整个论文围绕着PIC兼容技术及其工艺方案实现这一主线，研究提出了两种不同PIC类型的BCD工艺技术方案，并在此基础上成功研制了两种相应类型的PIC芯片。这两种工艺技术方案由于针对的PIC需求不同，其工艺方案也是截然不同的，以此来满足不同PIC对耐电压、电流等特殊的需求，这也一定程度上为PIC设计者提供了选择余地。该类芯片的研制成功，一方面意味着可以打破该类芯片只能依赖进口的落后局面，另一方面意味着具有完全自主知识产权的高压集成电路工艺生产线的国产化也不是不可能的。本文的工作为今后进一步进行PIC工艺和电路国产化研究积累了技术经验，同时通过全方位地对PIC研发整个流程的尝试，为相关技术推广及产业化打下了基础。
Driven by the development of microelectronics technology and powerelectronics, the Power Integrated Circuits (PICs) are booming quickly, and arewidely used in motor drivers, power management, automotive and flat-panel display.Recently, many new technologies and devices are raised and PSoC (Power Systemon Chip) is coming to the fore. However, the further development of the PICs isrestricted by the cost and process complexity of integration. Therefore, it issignificant to do research into the compatibility technology and design flow of PICs,to develop the BCD (Bipolar-CMOS-DMOS) process with our own intellectualproperty (IP) rights and to implement the corresponding power IC chips.
The work of this dissertation is devoted to the research on the compatibilitytechnology and the PIC design flow, including the process flow, device structure andcircuit design. The main contents and innovative points of this dissertation are listedbelow.
A BCD technology scheme named BCD_Z1 is proposed for the manufacture ofmonolithic smart PICs, in which high blocking voltage more than 500V is achieved.In the BCD_Z1 process scheme, the no-epitaxial double-RESURF LDMOS isintegrated with the low-voltage PWM controller to constitute a PWM switch smartpower IC. The test results show that the breakvoltage of the LDMOS is about 700V,and good function and performance of the PWM switch power IC with the LDMOSare achieved. Then the PIC is used in the switch power supply applications, andworks very well. The feasibility and the validity of BCD_Z1 technology scheme areverified.
A BCD technology scheme named BCD_Z2 is proposed for the manufacture ofthe PICs with high blocking voltage below 200V and low on-resistance. In theBCD_Z2 process scheme, the vertical DMOS is integrated with the level-shifter andlow-voltage control circuit, and a high-voltage fiat-display driver IC is implemented.This BCD_Z2 technology scheme further simplifies the process steps, reduces process complexity and cost. The test results show that all the devices implementedwith BCD_Z2 have reached the design specifications and the corresponding PDPscan driver IC is realized. The success of the PDP scan driver IC also confirms thevalidity of the proposed BCD_Z2 technology scheme.
A PDP scan driver IC is designed and implemented to verify the feasibility ofthe BCD_Z2 technology scheme. All of the functions of the PDP system requiredare realized by the PDP scan driver IC. It is able to work under the voltage 15～160V,and also provides high driving current. The PIC is implemented with the BCD_Z2process. The test results show that the functions and performance of this PDP scandriver IC are achieved, and the maximum operational frequency is 20MHz. As thekey parameters estimating the driving capability, the rising and falling time are165ns and 30ns under test conditions of V_(pp)=90V and C_L=200pF, respectively.
An in-depth study is carded out to reduce the on-resistance of the integratedVertical DMOS in the BCD_Z2 technology scheme. A 3-dimension analytical modelis proposed to calculate its on-resistance and specific on-resistance. Since all thecontacts of the integrated VDMOS are on the top side of the chip, the calculationand characteristic of its on-resistance are not identical with the conventionalVDMOS. The on-resistance of an integrated VDMOS varies with the placement andthe number of source cells. So the cell layout and the side number of drain contactsneed to be considered in the design of the integrated VDMOS. Using this model, theoptimal layout of the integrated VDMOS with a minimal specific on-resistance canbe achieved within a limited chip area, and the corresponding number of cells M×Nand side number of drain contacts can be calculated.
The work of this dissertation is focused on the PIC compatibility technologyand the corresponding design realization. It provides two different BCD technologyschemes for PIC design, and two corresponding PIC chips are designed andmanufactured. The two technology schemes are distinct obviously for differentapplications, and they provide some degrees of freedom of the PIC design. Thesuccess of two BCD process indicates that the domestic manufacture of BCD process with our own intellectual property rights is realizable. The work of thisdissertation provides some experiments for further PIC process and circuitryresearch, and also makes some preparation for technology transfer andindustrialization.
引文
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