片上网络低能耗和低延迟研究
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摘要
片上网络(NoC)是当前片上系统发展的一个重要方向,其中功耗和速度是设计NoC时的主要约束。随着带宽需求的增加,NoC在通信互连结构上消耗的能量所占的比例在逐步的扩大;同时,系统中处理器核的速度越来越快、数目越来越多,核之间通信的延迟将极大地影响系统整体性能。随着对高性能嵌入式计算需求的增加以及散热和电池电量有限问题的突出,能耗和延迟已经成为NoC走向实际应用必须解决的重要问题。
本文针对NoC的能耗和延迟问题,通过对当前片上网络低能耗和低延迟设计技术优缺点的分析,在体系结构级通信层面上,提出了带路径标号的并行通信边求解算法来优化片上网络延迟。该算法利用NoC上各IP核之间通信的相对可预测性以及各通信事件之间的时序关系来求解各通信链路上的并发通信量,并以链路并发通信量的均衡来减少延迟。在所提算法的基础上,结合片上网络低能耗映射蚁群优化算法,本文设计了一种低能耗和低延迟综合优化方案。在蚁群优化的过程中以链路并发通信量标准偏差和能耗的乘积作为目标评价函数,实现延迟和能耗的综合优化。
为了评价NoC系统的能耗和延迟综合优化效果,本文利用能耗延迟积作为衡量系统的能量-性能效率的指标。基于该指标,利用基于SystemC的NoC仿真器对文中的综合优化方案进行了仿真实验。结果表明,本文所提出的综合优化方法的能量-性能效率比链路平衡的方法优越。
Network-on-chip(NoC) is an important direction of development of system on chip, and the power consumption as well as speed are the main constraints in the design of NoC. With the increase in bandwidth requirement in the NoC, the energy consumption of communication infrastructure accounts for a large proportion of the system, which is still gradually increasing; At the same time, because of the increase in terms of speed and the number of processor cores, the communication delay between these processor cores greatly affects the overall performance of the system. With the requirement for high performance embedded computing increasing, as well as the issues of heat elimination and limited battery life prominent, energy consumption and delay have became the important issues that must be addressed for NoC to practical application.
This paper focuses on the energy consumption and delay of the NoC. Through the analysis of the advantages and disadvantages of the current research on low energy consumption and low delay design technology, the thesis presents an algorithm used for solving parallel communication arc with labeling in terms of the balance of concurrent traffic on communication links in the communication of the architecture level. With the relative predictability of the communication between the IP cores and the timing relationship of these communications, this algorithm solves the concurrent traffic of each communication link. Further, the balance of the concurrent traffic of the link can be used to reduce the delay. Base on the proposed algorithm and combination of low energy consumption mapping with ant colony optimization algorithm in the NoC, this thesis designs an integrated scheme for low energy consumption and low delay. Through the product of the standard deviation of the link’s concurrent traffic and energy consumption as a target evaluation function, we achieve an integrated optimization of the energy consumption and delay in the process of ant colony optimization.
To comprehensively evaluate the optimization effect of the energy consumption and delay of the NoC system, this paper uses energy-delay product(EDP) as the metrics of energy-performance efficiency. Based on this metrics, we conduct some simulation experiments for the proposed integrated optimization scheme through using the SystemC-based NoC simulator. The results show that the presented method used in this paper is better than the method of link balance in terms of energy-performance efficiency.
本文针对NoC的能耗和延迟问题,通过对当前片上网络低能耗和低延迟设计技术优缺点的分析,在体系结构级通信层面上,提出了带路径标号的并行通信边求解算法来优化片上网络延迟。该算法利用NoC上各IP核之间通信的相对可预测性以及各通信事件之间的时序关系来求解各通信链路上的并发通信量,并以链路并发通信量的均衡来减少延迟。在所提算法的基础上,结合片上网络低能耗映射蚁群优化算法,本文设计了一种低能耗和低延迟综合优化方案。在蚁群优化的过程中以链路并发通信量标准偏差和能耗的乘积作为目标评价函数,实现延迟和能耗的综合优化。
为了评价NoC系统的能耗和延迟综合优化效果,本文利用能耗延迟积作为衡量系统的能量-性能效率的指标。基于该指标,利用基于SystemC的NoC仿真器对文中的综合优化方案进行了仿真实验。结果表明,本文所提出的综合优化方法的能量-性能效率比链路平衡的方法优越。
Network-on-chip(NoC) is an important direction of development of system on chip, and the power consumption as well as speed are the main constraints in the design of NoC. With the increase in bandwidth requirement in the NoC, the energy consumption of communication infrastructure accounts for a large proportion of the system, which is still gradually increasing; At the same time, because of the increase in terms of speed and the number of processor cores, the communication delay between these processor cores greatly affects the overall performance of the system. With the requirement for high performance embedded computing increasing, as well as the issues of heat elimination and limited battery life prominent, energy consumption and delay have became the important issues that must be addressed for NoC to practical application.
This paper focuses on the energy consumption and delay of the NoC. Through the analysis of the advantages and disadvantages of the current research on low energy consumption and low delay design technology, the thesis presents an algorithm used for solving parallel communication arc with labeling in terms of the balance of concurrent traffic on communication links in the communication of the architecture level. With the relative predictability of the communication between the IP cores and the timing relationship of these communications, this algorithm solves the concurrent traffic of each communication link. Further, the balance of the concurrent traffic of the link can be used to reduce the delay. Base on the proposed algorithm and combination of low energy consumption mapping with ant colony optimization algorithm in the NoC, this thesis designs an integrated scheme for low energy consumption and low delay. Through the product of the standard deviation of the link’s concurrent traffic and energy consumption as a target evaluation function, we achieve an integrated optimization of the energy consumption and delay in the process of ant colony optimization.
To comprehensively evaluate the optimization effect of the energy consumption and delay of the NoC system, this paper uses energy-delay product(EDP) as the metrics of energy-performance efficiency. Based on this metrics, we conduct some simulation experiments for the proposed integrated optimization scheme through using the SystemC-based NoC simulator. The results show that the presented method used in this paper is better than the method of link balance in terms of energy-performance efficiency.
引文
[1]章隆兵.高级微处理器技术组2008年度研究成果.中国科学院计算技术研究所内部刊物信息技术快报, 2009, 76(1): 22-25
[2] Guttag K, Robert J, Jerry R, et a1. A single-chip multiprocessor for multimedia: the MVP. Computer Graphics and Application, 1992, 12(6): 53-64
[3] Chaoui J, Cyr K, de Gregorio S, et al. Open multimedia application platform: enabling multimedia applications in third generation wireless terminals through a combined RISC/DSP architecture. In: Proceedings of the IEEE International Conference on Acoustic, Speech, and Signal Processing. Washington, DC, USA: IEEE Computer Society, 2001, 1009-1012
[4]陈国兵.嵌入式异构多核体系的片上通信:[浙江大学硕士学位论文].浙江:浙江大学, 2007, 1-2
[5] Chris R. Engineering the complex SoC: fast, flexible design with configurable processors.吴武臣,候立刚译.北京:机械工业出版社, 2006, I-II
[6] Gordon M. Cramming more components onto integrated circuits. Electronics Magazine, 1965, 38(8): 114-117
[7]吴强.面向系统芯片的软硬件协同设计方法研究:[清华大学博士学位论文].北京:清华大学, 2004, 1-2
[8]胡伟武,李国杰.纳米级工艺对微处理器设计的挑战.中国集成电路, 2008, 110(7): 10-24
[9] Ho R, Mai K, Horowitz M. The future of wires. Proceedings of the IEEE, 2001, 89(4): 490-504
[10] Anoop I, Diana M. Power and performance evaluation of globally asynchronous locally synchronous processors. In: Proceedings of the 29th Annual International Symposium on Computer Architecture. Washington, DC, USA: IEEE Computer Society, 2002, 158-168
[11] Nilanjan B, Praveen V, Karam S. A power and performance model for Network on Chip architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2004, 1250-1255
[12] Axel J, Hannu T. Networks on Chip.王忠,孙继银,周国昌等译.西安:西安交通大学出版社, 2007, 58-59
[13] Michael K, Pierre B. Reuse methodology manual for System-on-Chip designs. Third Edition. Norwell, MA, USA : Kluwer Academic Publishers, 2002, 5-7
[14] Terry T. Technology for IP reuse and portability. IEEE Design and Test ofComputers, 1999, 16(4): 6-15
[15] Henry C, Larry C, Merrill H, et al. Surviving the SoC revolution: A guide to platform-based design. AH Dordrecht, Netherlands: Kluwer Academic Publishers, 1999, 3-10
[16] Mikael M, Erland N, Rikard T. The Nostrum backbone: A communication protocol stack for Networks-on-Chip. In: Proceedings of the 17th International Conference on VLSI Design. Washington, DC, USA: IEEE Computer Society, 2004, 693-696
[17] Simon M, George T, Robert M, et al. Point to point GALS interconnect. In: Proceedings of the 8th International Symposium on Asynchronous Circuits and Systems. Washington, DC, USA: IEEE Computer Society, 2002, 69-75
[18] Thomas M, Ahmed H, Kumar S, et al. Globally asynchronous locally synchronous architecture for large high performance ASICs. In: Proceedings of the IEEE International Symposium on Circuits and System. Orlando, FL, USA: IEEE Computer Society, 1999, 512-515
[19]李仁发,刘彦,徐成.多处理器片上系统任务调度研究进展评述.计算机研究与发展, 2008, 45(9): 1620-1629
[20] Hemani A, Jantsch A, Kumar S, et al. Network on a Chip: An architecture for billion transistor era. In: Proceedings of the 18th IEEE NorChip Conference. Turku, Finland: Kluwer Academic Publishers, 2000, 166-173
[21]毕克允.微电子技术-信息化武器装备的精灵.第2版.北京:国防工业出版社,2007, 299-300
[22]李侠.低功耗嵌入式微处理器的VLSI设计研究:[复旦大学博士学位论文].上海:复旦大学, 2004, 3-4
[23] Beini L, Castelli G, Macii A, et al. Extending lifetime of portable systems by battery scheduling. In: Proceedings of the Conference on Design, Automation and Test in Europe. Piscataway, NJ, USA : IEEE Press, 2001, 197-203
[24] Hangsheng W, Li-Shiuan P, Malik S. Power-driven design of router microarchitectures in On-Chip Networks. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 2003, 105-116
[25] Shang L, Li-Shiuan P, Niraj K. Dynamic voltage scaling with links for power optimization of interconnection networks. In: Proceedings of the 9th International Symposium on High-Performance Computer Architecture. Washington, DC, USA: IEEE Computer Society, 2003, 91-102
[26] Ogras U, Hu J, Marculescu R. Key research problems in NoC design: A holistic perspective. In: Proceedings of the Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. Washington, DC, USA: IEEE Computer Society, 2005, 69-74
[27]李丽,许居衍.片上网络技术发展现状及趋势浅析.电子产品世界, 2009, 16(1): 32-37
[28] Gaughan P, Yalamanchili S. Adaptive routing protocols for hypercube interconnection networks. IEEE Transaction Surveys, 1993, 30(30): 62-76
[29]刘刚.多计算机互连网络上的聚合通信算法研究:[中国科学技术大学博士学位论文].合肥:中国科学技术大学, 2006, 14-15
[30] Terry T, Benini L, Micheli G. Packetization and routing analysis of on-chip multiprocessor networks. Journal of System Architecture, 2004, 50(2): 81-104
[31] Axel J. Development of a C interface for a Nocsim NoC simulator resource. http://web.it.kth.se/~axel/MSc-Theses, 2006-2-22
[32] VSI Alliance. Virtual component interface. http://www.vsi.org, 2007-7-2
[33] OCP-IP. Open Core Protocol. http://www.ocpip.org/socket/ocpspec/, 2008-4-16
[34] Philips Semiconductors. Device Transaction Level (DTL) Protocol Specification. http://www.philips.com, 2005-9-20
[35] ARM. AMBA AXI Specification. http://www.arm.com/armtech/AXI, 2007-1-17
[36] Mudge T. Power: a first-class architectural design constraint. Computer, 2001, 34(4): 52-58
[37] Keating M, Flynn D, Aitken R, et al. Low power methodology manual for System-on-Chip design. New York, USA: Springer, 2007, 4-5
[38]张志敏,常晓涛. SoC低功耗设计技术发展综述.中国科学院计算技术研究所内部刊物信息技术快报, 2005, 23(4): 27-35
[39] Tadahiro K, Mototsugu H. Low-power CMOS digital design with dual embedded adaptive power supplies. IEEE Journal of Solid State Circuits, 2000, 35(4): 473-476
[40]赵荣彩,唐志敏,张兆庆等.编译指导的多线程低功耗技术研究.计算机研究与发展, 2002, 39(12): 1572-1579
[41] Robert P, Ganesh L, Anand R, et al. Power analysis of embedded operating systems. In: Proceedings of the 37th Conference on Annual ACM IEEE Design Automation. New York, USA: ACM, 2001, 312-315
[42] Suet-Fei L, Roy S, Jan R. Low power operating system for heterogonous wireless communication system. In: Proceedings of the Workshop on Compilers andOperating Systems for Low Power. Norwell, MA, USA: Kluwer Academic Publishers, 2001, 1-16
[43] Benini L, Micheli G. Powering Networks on Chips: Energy-efficient and reliable interconnect design for SoC. In: Proceedings of the 14th International Symposium on Systems Synthesis. New York, USA: ACM, 2001, 33-38
[44] Eisley N, Li-Shiuan P. High-level power analysis for on-chip networks. In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. New York, USA: ACM, 2004, 104-115
[45] Tajana S, Stephen P, Peter G. Managing power consumption in networks on chips. IEEE Transactions on Very Large Scale Integration Systems, 2004, 12(1): 96-107
[46] Jingcao H, Radu M. Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proceedings of the 2003 Conference on Asia South Pacific Design Automation. New York, USA: ACM, 2003, 233-239
[47] Vittorio M. Exact and approximate nondeterministic tree-search procedures for the quadratic assignment problem. INFORMS Journal on Computing, 1999, 11(4): 358-369
[48] Jingcao H, Radu M. Energy-aware communication and task scheduling for Network-on-Chip architectures under real-time constraints. In: Proceedings of the Conference on Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2004, 234-239
[49] Dongkun S, Jihong K. Power-aware communication optimization for networks on chip with voltage scalable links. In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis. New York, USA: ACM, 2004, 170-175
[50] Wayne W. High-performance embedded computing: architecture, application, and methodologies. English Version.北京:机械工业出版社, 2007, 21-22
[51] Giuseppe A, Vincenzo C, Maurizio P, et al. Neighbors-on-Path: A new selection strategy for On-Chip Networks. In: Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia. NJ, USA: IEEE Press, 2006, 79-84
[52]陈国良,吴俊敏,章锋等.并行计算机体系结构.北京:高等教育出版社,2002, 189-190
[53] Jongman K, Dongkook P, Theocharides T, et al. A Low latency router supporting adaptivity for On-Chip interconnects. In: Proceedings of the 42nd Annual Conference on Design Automation. New York, USA: ACM, 2005, 559-564
[54] Goossens K, van Meerbergenm J, Peeters A, et al. Networks on silicon: Combining best-effort and guaranteed services. In: Proceedings of the Design Automation and Test in Europe Conference and Exhibition. Washington, DC, USA: IEEE Computer Society, 2002, 423-425
[55] Mikael M, Erland N, Rikard T, et al. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum Network on Chip. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. Washington, DC, USA: IEEE Computer Society, 2004, 1530-1591
[56] Marcon C, Calazans N, Moraes F, et al. Exploring NoC mapping strategies: An energy and timing aware technique. In: Proceedings of the Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2005, 502-507
[57]周干民,尹勇生,胡永华等.基于蚁群优化算法的NoC映射.计算机工程与应用, 2005, 41(18): 7-10
[58]杨盛光,李丽,高明伦等.面向能耗和延时的NoC映射方法.电子学报, 2008, 36(5): 937-942
[59] Ye T,Benini L,Micheli G. Analysis of power consumption on switch fabrics in network routers. In: Proceedings of the 39th Conference on Design Automation. New York, USA: ACM, 2002, 524-529
[60] Gonzalez R, Horowitz M. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 1996, 31(9): 1277–1284
[61] Jari N, Hannu T, Jouni I, et al. Interconnect-centric design for advanced SoC and NoC. Norwell, MA, USA: Kluwer Academic Publishers, 2004: 156-157
[62] Keith V, David R, Robert D. TGFF. http://ziyang.eecs.umich.edu/~dickrp/tgff, 2008-4-15
[63] Yiran S, Kumar S, Axel J. Simulation and evaluation for a Network on Chip architecture using NS-2. In: Proceedings of the 20th IEEE NorChip Conference. Copenhagen, Denmark: Kluwer Academic Press, 2002, 163-168
[64] Louis S, Luciano L. EDA for IC System Design, Verification, and Testing.陈力颖,王猛译.北京:科学出版社, 2008, 61-62
[65] Open SystemC Initiative. About SystemC. http://www.systemc.org, 2009-3-12
[66] Bhasker J. SystemC Primer. PA, USA: Star Galaxy Publishing, 2002, 10-12
[67] Fabrizio F, Maurizio P, Davide P. Noxim Simulator. http://noxim.sourceforge.net, 2008-11-18
[2] Guttag K, Robert J, Jerry R, et a1. A single-chip multiprocessor for multimedia: the MVP. Computer Graphics and Application, 1992, 12(6): 53-64
[3] Chaoui J, Cyr K, de Gregorio S, et al. Open multimedia application platform: enabling multimedia applications in third generation wireless terminals through a combined RISC/DSP architecture. In: Proceedings of the IEEE International Conference on Acoustic, Speech, and Signal Processing. Washington, DC, USA: IEEE Computer Society, 2001, 1009-1012
[4]陈国兵.嵌入式异构多核体系的片上通信:[浙江大学硕士学位论文].浙江:浙江大学, 2007, 1-2
[5] Chris R. Engineering the complex SoC: fast, flexible design with configurable processors.吴武臣,候立刚译.北京:机械工业出版社, 2006, I-II
[6] Gordon M. Cramming more components onto integrated circuits. Electronics Magazine, 1965, 38(8): 114-117
[7]吴强.面向系统芯片的软硬件协同设计方法研究:[清华大学博士学位论文].北京:清华大学, 2004, 1-2
[8]胡伟武,李国杰.纳米级工艺对微处理器设计的挑战.中国集成电路, 2008, 110(7): 10-24
[9] Ho R, Mai K, Horowitz M. The future of wires. Proceedings of the IEEE, 2001, 89(4): 490-504
[10] Anoop I, Diana M. Power and performance evaluation of globally asynchronous locally synchronous processors. In: Proceedings of the 29th Annual International Symposium on Computer Architecture. Washington, DC, USA: IEEE Computer Society, 2002, 158-168
[11] Nilanjan B, Praveen V, Karam S. A power and performance model for Network on Chip architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2004, 1250-1255
[12] Axel J, Hannu T. Networks on Chip.王忠,孙继银,周国昌等译.西安:西安交通大学出版社, 2007, 58-59
[13] Michael K, Pierre B. Reuse methodology manual for System-on-Chip designs. Third Edition. Norwell, MA, USA : Kluwer Academic Publishers, 2002, 5-7
[14] Terry T. Technology for IP reuse and portability. IEEE Design and Test ofComputers, 1999, 16(4): 6-15
[15] Henry C, Larry C, Merrill H, et al. Surviving the SoC revolution: A guide to platform-based design. AH Dordrecht, Netherlands: Kluwer Academic Publishers, 1999, 3-10
[16] Mikael M, Erland N, Rikard T. The Nostrum backbone: A communication protocol stack for Networks-on-Chip. In: Proceedings of the 17th International Conference on VLSI Design. Washington, DC, USA: IEEE Computer Society, 2004, 693-696
[17] Simon M, George T, Robert M, et al. Point to point GALS interconnect. In: Proceedings of the 8th International Symposium on Asynchronous Circuits and Systems. Washington, DC, USA: IEEE Computer Society, 2002, 69-75
[18] Thomas M, Ahmed H, Kumar S, et al. Globally asynchronous locally synchronous architecture for large high performance ASICs. In: Proceedings of the IEEE International Symposium on Circuits and System. Orlando, FL, USA: IEEE Computer Society, 1999, 512-515
[19]李仁发,刘彦,徐成.多处理器片上系统任务调度研究进展评述.计算机研究与发展, 2008, 45(9): 1620-1629
[20] Hemani A, Jantsch A, Kumar S, et al. Network on a Chip: An architecture for billion transistor era. In: Proceedings of the 18th IEEE NorChip Conference. Turku, Finland: Kluwer Academic Publishers, 2000, 166-173
[21]毕克允.微电子技术-信息化武器装备的精灵.第2版.北京:国防工业出版社,2007, 299-300
[22]李侠.低功耗嵌入式微处理器的VLSI设计研究:[复旦大学博士学位论文].上海:复旦大学, 2004, 3-4
[23] Beini L, Castelli G, Macii A, et al. Extending lifetime of portable systems by battery scheduling. In: Proceedings of the Conference on Design, Automation and Test in Europe. Piscataway, NJ, USA : IEEE Press, 2001, 197-203
[24] Hangsheng W, Li-Shiuan P, Malik S. Power-driven design of router microarchitectures in On-Chip Networks. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 2003, 105-116
[25] Shang L, Li-Shiuan P, Niraj K. Dynamic voltage scaling with links for power optimization of interconnection networks. In: Proceedings of the 9th International Symposium on High-Performance Computer Architecture. Washington, DC, USA: IEEE Computer Society, 2003, 91-102
[26] Ogras U, Hu J, Marculescu R. Key research problems in NoC design: A holistic perspective. In: Proceedings of the Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. Washington, DC, USA: IEEE Computer Society, 2005, 69-74
[27]李丽,许居衍.片上网络技术发展现状及趋势浅析.电子产品世界, 2009, 16(1): 32-37
[28] Gaughan P, Yalamanchili S. Adaptive routing protocols for hypercube interconnection networks. IEEE Transaction Surveys, 1993, 30(30): 62-76
[29]刘刚.多计算机互连网络上的聚合通信算法研究:[中国科学技术大学博士学位论文].合肥:中国科学技术大学, 2006, 14-15
[30] Terry T, Benini L, Micheli G. Packetization and routing analysis of on-chip multiprocessor networks. Journal of System Architecture, 2004, 50(2): 81-104
[31] Axel J. Development of a C interface for a Nocsim NoC simulator resource. http://web.it.kth.se/~axel/MSc-Theses, 2006-2-22
[32] VSI Alliance. Virtual component interface. http://www.vsi.org, 2007-7-2
[33] OCP-IP. Open Core Protocol. http://www.ocpip.org/socket/ocpspec/, 2008-4-16
[34] Philips Semiconductors. Device Transaction Level (DTL) Protocol Specification. http://www.philips.com, 2005-9-20
[35] ARM. AMBA AXI Specification. http://www.arm.com/armtech/AXI, 2007-1-17
[36] Mudge T. Power: a first-class architectural design constraint. Computer, 2001, 34(4): 52-58
[37] Keating M, Flynn D, Aitken R, et al. Low power methodology manual for System-on-Chip design. New York, USA: Springer, 2007, 4-5
[38]张志敏,常晓涛. SoC低功耗设计技术发展综述.中国科学院计算技术研究所内部刊物信息技术快报, 2005, 23(4): 27-35
[39] Tadahiro K, Mototsugu H. Low-power CMOS digital design with dual embedded adaptive power supplies. IEEE Journal of Solid State Circuits, 2000, 35(4): 473-476
[40]赵荣彩,唐志敏,张兆庆等.编译指导的多线程低功耗技术研究.计算机研究与发展, 2002, 39(12): 1572-1579
[41] Robert P, Ganesh L, Anand R, et al. Power analysis of embedded operating systems. In: Proceedings of the 37th Conference on Annual ACM IEEE Design Automation. New York, USA: ACM, 2001, 312-315
[42] Suet-Fei L, Roy S, Jan R. Low power operating system for heterogonous wireless communication system. In: Proceedings of the Workshop on Compilers andOperating Systems for Low Power. Norwell, MA, USA: Kluwer Academic Publishers, 2001, 1-16
[43] Benini L, Micheli G. Powering Networks on Chips: Energy-efficient and reliable interconnect design for SoC. In: Proceedings of the 14th International Symposium on Systems Synthesis. New York, USA: ACM, 2001, 33-38
[44] Eisley N, Li-Shiuan P. High-level power analysis for on-chip networks. In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. New York, USA: ACM, 2004, 104-115
[45] Tajana S, Stephen P, Peter G. Managing power consumption in networks on chips. IEEE Transactions on Very Large Scale Integration Systems, 2004, 12(1): 96-107
[46] Jingcao H, Radu M. Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proceedings of the 2003 Conference on Asia South Pacific Design Automation. New York, USA: ACM, 2003, 233-239
[47] Vittorio M. Exact and approximate nondeterministic tree-search procedures for the quadratic assignment problem. INFORMS Journal on Computing, 1999, 11(4): 358-369
[48] Jingcao H, Radu M. Energy-aware communication and task scheduling for Network-on-Chip architectures under real-time constraints. In: Proceedings of the Conference on Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2004, 234-239
[49] Dongkun S, Jihong K. Power-aware communication optimization for networks on chip with voltage scalable links. In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis. New York, USA: ACM, 2004, 170-175
[50] Wayne W. High-performance embedded computing: architecture, application, and methodologies. English Version.北京:机械工业出版社, 2007, 21-22
[51] Giuseppe A, Vincenzo C, Maurizio P, et al. Neighbors-on-Path: A new selection strategy for On-Chip Networks. In: Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia. NJ, USA: IEEE Press, 2006, 79-84
[52]陈国良,吴俊敏,章锋等.并行计算机体系结构.北京:高等教育出版社,2002, 189-190
[53] Jongman K, Dongkook P, Theocharides T, et al. A Low latency router supporting adaptivity for On-Chip interconnects. In: Proceedings of the 42nd Annual Conference on Design Automation. New York, USA: ACM, 2005, 559-564
[54] Goossens K, van Meerbergenm J, Peeters A, et al. Networks on silicon: Combining best-effort and guaranteed services. In: Proceedings of the Design Automation and Test in Europe Conference and Exhibition. Washington, DC, USA: IEEE Computer Society, 2002, 423-425
[55] Mikael M, Erland N, Rikard T, et al. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum Network on Chip. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. Washington, DC, USA: IEEE Computer Society, 2004, 1530-1591
[56] Marcon C, Calazans N, Moraes F, et al. Exploring NoC mapping strategies: An energy and timing aware technique. In: Proceedings of the Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2005, 502-507
[57]周干民,尹勇生,胡永华等.基于蚁群优化算法的NoC映射.计算机工程与应用, 2005, 41(18): 7-10
[58]杨盛光,李丽,高明伦等.面向能耗和延时的NoC映射方法.电子学报, 2008, 36(5): 937-942
[59] Ye T,Benini L,Micheli G. Analysis of power consumption on switch fabrics in network routers. In: Proceedings of the 39th Conference on Design Automation. New York, USA: ACM, 2002, 524-529
[60] Gonzalez R, Horowitz M. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 1996, 31(9): 1277–1284
[61] Jari N, Hannu T, Jouni I, et al. Interconnect-centric design for advanced SoC and NoC. Norwell, MA, USA: Kluwer Academic Publishers, 2004: 156-157
[62] Keith V, David R, Robert D. TGFF. http://ziyang.eecs.umich.edu/~dickrp/tgff, 2008-4-15
[63] Yiran S, Kumar S, Axel J. Simulation and evaluation for a Network on Chip architecture using NS-2. In: Proceedings of the 20th IEEE NorChip Conference. Copenhagen, Denmark: Kluwer Academic Press, 2002, 163-168
[64] Louis S, Luciano L. EDA for IC System Design, Verification, and Testing.陈力颖,王猛译.北京:科学出版社, 2008, 61-62
[65] Open SystemC Initiative. About SystemC. http://www.systemc.org, 2009-3-12
[66] Bhasker J. SystemC Primer. PA, USA: Star Galaxy Publishing, 2002, 10-12
[67] Fabrizio F, Maurizio P, Davide P. Noxim Simulator. http://noxim.sourceforge.net, 2008-11-18
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