IC制造中硅片边缘上光刻工艺的波动问题研究
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摘要
光刻工艺是半导体制造中最为重要的工艺步骤之一,其作用是将掩膜板上的图形复制到硅片上,为下一步工序做好准备。光刻工艺的基本要求是具有高的分辨率和低的缺陷密度。随着硅片尺寸越来越大,线宽越来越小,早期工艺中不是很关心的硅片边缘问题,变得越来越严重。因为随着硅片尺寸的增大,硅片的周长成倍的增加,而线宽的变小,导致硅片边缘有效芯片的数量也成倍的增加。硅片边缘光刻工艺的波动问题就变得越来越重要,对提高良率和生产效率有非常大的意义。
实验发现,在0.6微米的HVMOS工艺中,硅片周边是非完整曝光区域,电子显微镜下观察发现,图像中柱状图形部分发生离焦。研究表明,有三种方法可以有效解决周边离焦问题,1)通过聚焦和平坦化有效侦测距离；2)通过向正方向调整聚焦平面；3)手动控制AF的侦测点的位置。
在12英寸90/45纳米工艺中,光刻设备有了较大的改进,同时增加了RET,似乎所有的注意力都放在如何才能把CD做得更小,但分辨率的提高,DOF会成倍的减小,硅片周边的敏感度会变得更高,导致边缘工艺偏差更大的波动。对于12英寸硅片,可以看到缺陷源头存在于硅片的周边,离焦问题比较严重。EBR+WEE的方式清洗硅片周边多余光刻胶,WEE清洗的设定距离比EBR稍微要小些,从而达到准却的清洗宽度以及清除使用EBR带来的毛刺。实验结果可以看到,当EBR&BACKRINSE的时间增加到15s,速度增加到1500r/m时会有一个比较干净的bevel。从原理上就是通过增加去边的药液量以及反应时间可以让更多的溶剂与BEVEL上的光刻胶反应,同时增加转速可以使BACKRINSE有更多的溶液翻到侧面清洗BEVEL,从而消除硅片BEVEL的残留引起的边缘工艺波动。
总之,不管是8寸还是12寸甚至今后的18寸,边缘问题一定会被摆在一个非常重要的地位。引起硅片周边缺陷问题的因素有很多,衬底的厚度差异,bevel部分的污染问题,这些外界因素都是不确定的,但光刻工艺本身有着较复杂灵活的方法和工具。在工厂里产量和成本是最重要的两个要素,每增加一个工艺步骤都会增加工艺成本以及影响流片速度。因此在万不得已的情况下,工程上更希望只是通过光刻工艺的优化在覆盖衬底或是工艺本事带来的问题。因此这对光刻的要求会更高,同时也能更加充分发挥光刻的先进工具和技术。
Lithography process is one of the most important semiconductor manufacturing process steps, it is used to copy mask plate pattern on the silicon wafer for next Lithography step. Lithography process's basic requirement is the high resolution and low defect density. With the wafer size become more and more big, the CD is more and smaller, earlier process is not very concerned with the edge of the silicon wafer, but now it became more and more serious. For the increase of the silicon wafer size, the wafer's perimeter increased. The truth of the CD became smaller, leading to effective chip number around silicon wafer edge also have increased by multiply. So lithography process fluctuation problem in the edge of the silicon wafer becomes more and more important, it has a great significance to improve the yield and production efficiency.
From the experiment, in 0.6 micron HVMOS process, through electron microscopic observation, in the partial shot of wafer edge, the pattern like column is defocus. From the research, there are three effective ways to solve the wafer edge defocus issue, 1)through focus and flatness to detect the width effectively; 2)adjust the focus plane to the positive direction; 3) manual control AF detection point position.
In 12 inch 90/45 nm process, lithographic equipment has a greatly improved, while the increase of RET, it seems that all attention on how to make the CD smaller, but if the improvement of resolution, DOF will exponentially decreases, and the sensitivity of the wafer edge will becomes higher, it will lead to edge process deviation more fluctuations. For the 12 inch wafer, we can find the defect source exists in wafer edge; its defocus problem is very serious. EBR plus WEE mode of silicon wafer can clean wafer edge's photo resist residue, in it, WEE cleaning setting wide is smaller than EBR's, which will achieve the precision cleaning width and removed wafer edge residue from EBR more clearly. From the experiment results, when the EBR&BACKRINSE time increased to 15s, and the spin speed increased to 1500r/m there will be a relatively clean bevel. In principle, it is to increase the volume of liquid medicine and reaction time to edge to let more solvent to remove wafer bevel photo resist residue, while increasing the rotational speed can make the back-rinse more solution turned up to the wafer edge to clean wafer bevel, all these can eliminate the wafer edge process fluctuation from bevel residue.
In short, whether it is 8 inch or 12 inch or 18 inch in the future, wafer edge problem will be placed in a very important position. Wafer edge problems caused by many factors, substrate thickness difference, and wafer bevel pollution problems, these external factors are uncertain, but a photolithographic process itself is relatively complex and flexible methods and tools. In the factory, output and cost are the two most important elements, when adding a process step, the cost will increase and it will impact the wafer throughput. Therefore in common situations, FAB would rather optimize the photo process to cover the substrate or process problems than adjust film thickness or change etch rate. Therefore the lithography will be higher requirements, but it can also play the advanced lithography tools and techniques to the extreme.
实验发现,在0.6微米的HVMOS工艺中,硅片周边是非完整曝光区域,电子显微镜下观察发现,图像中柱状图形部分发生离焦。研究表明,有三种方法可以有效解决周边离焦问题,1)通过聚焦和平坦化有效侦测距离；2)通过向正方向调整聚焦平面；3)手动控制AF的侦测点的位置。
在12英寸90/45纳米工艺中,光刻设备有了较大的改进,同时增加了RET,似乎所有的注意力都放在如何才能把CD做得更小,但分辨率的提高,DOF会成倍的减小,硅片周边的敏感度会变得更高,导致边缘工艺偏差更大的波动。对于12英寸硅片,可以看到缺陷源头存在于硅片的周边,离焦问题比较严重。EBR+WEE的方式清洗硅片周边多余光刻胶,WEE清洗的设定距离比EBR稍微要小些,从而达到准却的清洗宽度以及清除使用EBR带来的毛刺。实验结果可以看到,当EBR&BACKRINSE的时间增加到15s,速度增加到1500r/m时会有一个比较干净的bevel。从原理上就是通过增加去边的药液量以及反应时间可以让更多的溶剂与BEVEL上的光刻胶反应,同时增加转速可以使BACKRINSE有更多的溶液翻到侧面清洗BEVEL,从而消除硅片BEVEL的残留引起的边缘工艺波动。
总之,不管是8寸还是12寸甚至今后的18寸,边缘问题一定会被摆在一个非常重要的地位。引起硅片周边缺陷问题的因素有很多,衬底的厚度差异,bevel部分的污染问题,这些外界因素都是不确定的,但光刻工艺本身有着较复杂灵活的方法和工具。在工厂里产量和成本是最重要的两个要素,每增加一个工艺步骤都会增加工艺成本以及影响流片速度。因此在万不得已的情况下,工程上更希望只是通过光刻工艺的优化在覆盖衬底或是工艺本事带来的问题。因此这对光刻的要求会更高,同时也能更加充分发挥光刻的先进工具和技术。
Lithography process is one of the most important semiconductor manufacturing process steps, it is used to copy mask plate pattern on the silicon wafer for next Lithography step. Lithography process's basic requirement is the high resolution and low defect density. With the wafer size become more and more big, the CD is more and smaller, earlier process is not very concerned with the edge of the silicon wafer, but now it became more and more serious. For the increase of the silicon wafer size, the wafer's perimeter increased. The truth of the CD became smaller, leading to effective chip number around silicon wafer edge also have increased by multiply. So lithography process fluctuation problem in the edge of the silicon wafer becomes more and more important, it has a great significance to improve the yield and production efficiency.
From the experiment, in 0.6 micron HVMOS process, through electron microscopic observation, in the partial shot of wafer edge, the pattern like column is defocus. From the research, there are three effective ways to solve the wafer edge defocus issue, 1)through focus and flatness to detect the width effectively; 2)adjust the focus plane to the positive direction; 3) manual control AF detection point position.
In 12 inch 90/45 nm process, lithographic equipment has a greatly improved, while the increase of RET, it seems that all attention on how to make the CD smaller, but if the improvement of resolution, DOF will exponentially decreases, and the sensitivity of the wafer edge will becomes higher, it will lead to edge process deviation more fluctuations. For the 12 inch wafer, we can find the defect source exists in wafer edge; its defocus problem is very serious. EBR plus WEE mode of silicon wafer can clean wafer edge's photo resist residue, in it, WEE cleaning setting wide is smaller than EBR's, which will achieve the precision cleaning width and removed wafer edge residue from EBR more clearly. From the experiment results, when the EBR&BACKRINSE time increased to 15s, and the spin speed increased to 1500r/m there will be a relatively clean bevel. In principle, it is to increase the volume of liquid medicine and reaction time to edge to let more solvent to remove wafer bevel photo resist residue, while increasing the rotational speed can make the back-rinse more solution turned up to the wafer edge to clean wafer bevel, all these can eliminate the wafer edge process fluctuation from bevel residue.
In short, whether it is 8 inch or 12 inch or 18 inch in the future, wafer edge problem will be placed in a very important position. Wafer edge problems caused by many factors, substrate thickness difference, and wafer bevel pollution problems, these external factors are uncertain, but a photolithographic process itself is relatively complex and flexible methods and tools. In the factory, output and cost are the two most important elements, when adding a process step, the cost will increase and it will impact the wafer throughput. Therefore in common situations, FAB would rather optimize the photo process to cover the substrate or process problems than adjust film thickness or change etch rate. Therefore the lithography will be higher requirements, but it can also play the advanced lithography tools and techniques to the extreme.
引文
[1].斯蒂芬A.坎贝尔.微纳尺寸制造工程(第三版)[N].北京：电子工业大学出版社,2011.
[2]. Peter Van Zant.芯片制造(第四版)[N].北京：电子工业大学出版社,2004.
[3]. Michael Quirk & Julian Serda.半导体制造技术[N].北京：电子工业大学出版社,2009.
[4]. Campbell, S. A.微电子制造科学原理与工程技术(第二版)[N].北京：电子工业出版社,2003.
[5]. SINGER P.45 nm铜互连面临的挑战[J].电子制造China,2004,13(5):30-33
[6]. Torben Heins, Uwe Dersch, Roman Liebe, Jan Richter. Line edge roughness on photo lithographic masks [R]. SPIE-The International Society for Optical Engineering,2006.
[7].赵宇航,朱骏.对通孔消失机理的研究以及相应的解决方案[J].半导体学报,2008,1(6)：3-5.
[8].刘逸轩.光刻中激光线宽影响及分辨率增强技术的研究[D].广东：广东工业大学,2010.
[9].高松波.光刻分辨率增强技术研究[D].北京：中国科学院电工研究所,2008.
[10].陈宝钦,刘明.半导体科学与技术[M].北京：科学出版社,2007：306-350
[11].上海华虹NEC电子有限公司,半导体器件特殊结构的制作方法[P].中国专利：CN200710094365.5,2007-11-30.
[12].王强.用于紫外光刻的聚焦光学系统的研究[D].重庆：重庆大学,2007.
[13].缪小运.先进光刻系统中焦平面测量与控制的研究[D].上海：复旦大学,2006.
[14].翁寿松.193 nm浸入式光刻技术独树一帜[J].电子工业专用设备,2005,34(7)：11-14.
[15].白春礼.中国纳米科技研究的现状及思考[J].物理,2002,31(2)：65-70.
[16]. MONETLIUS L, HEIDARI B, GRACZYK M. Nanoimprint and UV-lithography: Mix & Match process for fabrication of interdigitated nanobiosensors [J]. Microelectronic Engineering,2000,53(2): 521-524.
[17].陈宝钦,赵珉,吴璇,等.微光刻与电子束光刻技术[C]//华人微电子学术论坛文集.北京,中国,2010：159-208.
[18].郭维廉.固态纳米电子器件和分子器件[J].微纳电子技术,2002,39(4)：1.
[19].翁寿松.90nm工艺及其相关技术[J].微纳电子技术,2003,40(4)：40.
[20].井田彻,西森浩友,天井秀美,等.半导体设备与工艺技术的现状及新技术[J].电子工业专用设备,2003,32(3)：6.
[21]. SCHULZ H, KORBES A S, SCHEER H C. Combination of nanoimprint and scanning force lithography for local tailoring of sidewalls of nanometer devices [J]. Microelectronic Engineering,2000,53(2): 221-224.
[22].高腾.面向45纳米制造工艺的技术研究[J].集成电路应用,2003,(7)：49.
[23].翁寿松.300 mm晶圆芯片制造技术的发展趋势[J].半导体技术,2004,29(1)：27.
[24].童志义.光学光刻技术现状及发展趋势[J].电子工业专用设备,2001,30(1)：1.
[25]. WAIKIN L, SOLAK H H, CERRINA F.制作亚50nm L/S图形的极紫外纳米光刻技术[J].电子工业专用设备,2001,30(4)：37.
[26].黎明.深亚微米集成电路工艺制备中的缺陷问题研究[D].上海：复旦大学,2006.
[27].翁寿松.世界半导体设备的“十大”发展趋势[J].集成电路应用,20045(12)：10-13.
[2]. Peter Van Zant.芯片制造(第四版)[N].北京：电子工业大学出版社,2004.
[3]. Michael Quirk & Julian Serda.半导体制造技术[N].北京：电子工业大学出版社,2009.
[4]. Campbell, S. A.微电子制造科学原理与工程技术(第二版)[N].北京：电子工业出版社,2003.
[5]. SINGER P.45 nm铜互连面临的挑战[J].电子制造China,2004,13(5):30-33
[6]. Torben Heins, Uwe Dersch, Roman Liebe, Jan Richter. Line edge roughness on photo lithographic masks [R]. SPIE-The International Society for Optical Engineering,2006.
[7].赵宇航,朱骏.对通孔消失机理的研究以及相应的解决方案[J].半导体学报,2008,1(6)：3-5.
[8].刘逸轩.光刻中激光线宽影响及分辨率增强技术的研究[D].广东：广东工业大学,2010.
[9].高松波.光刻分辨率增强技术研究[D].北京：中国科学院电工研究所,2008.
[10].陈宝钦,刘明.半导体科学与技术[M].北京：科学出版社,2007：306-350
[11].上海华虹NEC电子有限公司,半导体器件特殊结构的制作方法[P].中国专利：CN200710094365.5,2007-11-30.
[12].王强.用于紫外光刻的聚焦光学系统的研究[D].重庆：重庆大学,2007.
[13].缪小运.先进光刻系统中焦平面测量与控制的研究[D].上海：复旦大学,2006.
[14].翁寿松.193 nm浸入式光刻技术独树一帜[J].电子工业专用设备,2005,34(7)：11-14.
[15].白春礼.中国纳米科技研究的现状及思考[J].物理,2002,31(2)：65-70.
[16]. MONETLIUS L, HEIDARI B, GRACZYK M. Nanoimprint and UV-lithography: Mix & Match process for fabrication of interdigitated nanobiosensors [J]. Microelectronic Engineering,2000,53(2): 521-524.
[17].陈宝钦,赵珉,吴璇,等.微光刻与电子束光刻技术[C]//华人微电子学术论坛文集.北京,中国,2010：159-208.
[18].郭维廉.固态纳米电子器件和分子器件[J].微纳电子技术,2002,39(4)：1.
[19].翁寿松.90nm工艺及其相关技术[J].微纳电子技术,2003,40(4)：40.
[20].井田彻,西森浩友,天井秀美,等.半导体设备与工艺技术的现状及新技术[J].电子工业专用设备,2003,32(3)：6.
[21]. SCHULZ H, KORBES A S, SCHEER H C. Combination of nanoimprint and scanning force lithography for local tailoring of sidewalls of nanometer devices [J]. Microelectronic Engineering,2000,53(2): 221-224.
[22].高腾.面向45纳米制造工艺的技术研究[J].集成电路应用,2003,(7)：49.
[23].翁寿松.300 mm晶圆芯片制造技术的发展趋势[J].半导体技术,2004,29(1)：27.
[24].童志义.光学光刻技术现状及发展趋势[J].电子工业专用设备,2001,30(1)：1.
[25]. WAIKIN L, SOLAK H H, CERRINA F.制作亚50nm L/S图形的极紫外纳米光刻技术[J].电子工业专用设备,2001,30(4)：37.
[26].黎明.深亚微米集成电路工艺制备中的缺陷问题研究[D].上海：复旦大学,2006.
[27].翁寿松.世界半导体设备的“十大”发展趋势[J].集成电路应用,20045(12)：10-13.
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