基于分层架构的网络处理器系统性能分析方法研究
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摘要
由于网络处理器(Network Processor,简称NP)具备高性能、可编程、易扩展和开发周期短等特性,自90年代末诞生伊始就受到了众多商业企业和科研机构的关注。30余个厂商生产或提出了500多种产品和设计方案；众多公司(例如：Cisco、ALCATE、Deceng、华为3Com等)采用网络处理器构建了路由、交换、安全等领域的多种网络设备。
近年来,网络处理器技术的发展不尽人意,特别是在利用网络处理器进行应用系统开发时,面临着缺乏能在异构的软硬件体系结构间进行合理的系统设计方案评估,并为网络处理器系统的设计和优化提供技术支撑和参考依据的性能分析方法。
本文的主要研究目的是：开展网络处理器系统的性能分析方法研究,为网络处理器系统研发中的方案评估、系统设计、系统改进等阶段提供技术支撑和参考依据。即对众多的器件和系统设计方案进行评估,选择适合需求的性价比好的方案；分析已有的方案和系统的性能缺陷和瓶颈,并根据这些因素改进和提高系统性能；对将要设计的系统进行性能预测,在性能成本方面实现最佳设计和配置。本文的主要贡献与创新总结如下：
1、提出了扩展的通用网络处理器结构(Extended General Network Processor Topology,简称EGNPT)和网络处理器软件分层描述法,实现了不同网络处理器软硬件体系结构的统一描述以及网络处理器的软件结构和多级并行层次间的映射,为在不同软硬件结构的网络处理器系统间进行性能分析工作奠定了基础。
2、提出了将“可用计算周期”和“访存次数”作为约束条件的网络处理器软硬件结构映射方法,压缩了网络处理器应用设计空间(Design Space)(针对基准测试用例IPv4Forward的实验结果表明该方法的压缩比例高达8947848倍),有效降低了设计空间内搜索的复杂度,形成了合理的性能分析对象集合。
3、提出了“基于分层架构的网络处理器系统性能分析方法”,实现了对网络处理器这种多级并行系统的性能评估。实验结果表明该方法的误差小于8%,高于现有各种性能分析方法的精度(误差为10%—17%)。NPF基准测试用例IPv4 Forward的设计方案评估、“基于网络处理器的网络测试平台”的系统设计、“基于网络处理器的网络监控系统”的系统改进等工程实践证明：该方法可以有效的为网络处理器系统的方案评估、系统设计和系统改进等工作提供技术支撑和参考依据。
4、在应用功能层面,提出了“线段分析法”,实现了对网络处理器处理单元(Processing Element,简称PE)中多线程程序的性能分析。针对IPv4 Forward的实验结果表明该方法误差仅为0.47%,为进一步采用排队网络进行系统平台层面的性能分析提供了高精度的所需参数。
5、在系统平台层面,提出了“基于GI/G/m/∞/FCFS多类型客户开放排队网络”的性能分析模型,利用非乘积形式解排队网络(Non-Product-Form Queueing Networks)描述网络处理器系统,实现了对多类型输入、多服务员服务台的开放网络的性能分析。相对于现有研究成果(仅采用单一客户类型、单服务员服务台和泊松到达过程/负指数服务时间分布的排队网络进行建模),该模型提高了对现实系统的描述贴近度。
6、采用分解法对GI/G/m/∞/FCFS多类型客户输入开放排队网络求解,给出了一种新型流通阶段(Flow)输出流到达时间间隔变异系数(Coefficient of Variation)的求解方法。基于该方法设计了“基于排队网络的包随机发送算法”,并应用到河南省杰出人才创新基金项目“基于网络处理器的网络测试平台”中,实现了高速随机测试流量的生成。
本文在网络处理器软硬件结构抽象描述及其映射、设计空间压缩、具有多级并行机制的网络处理器系统性能分析方法、基于排队网络的性能分析模型等方向做了较为深入细致的研究,但仍存在有待进一步研究的问题,包括：在不同体系结构的网络处理器平台上验证本文提出的“基于分层架构的网络处理器系统性能分析方法”的普适性；研究网络处理器的指令级并行和程序/数据的相关性对网络处理器系统性能的影响；基于本文提出的性能分析方法研发自动化性能分析工具。
From the birth of network processors (NP), they gain lots of attentions from many companies and researchers, because of their high performance, programmable, extendable and fast to markets characteristics. More than 30 companies have brought out more than 500 products or designs. Cisco, ALCATE, Deceng, HuaWei 3Com etc. have built routers, switches and security devices using these processors.
But now, the development of network processors technology doesn't match people's wish. Especially when building a system with NPs, we have to face the fact that the absence of a performance analysis methodology, which can help us evaluate the various designs among different hardware and software architectures, design and optimize NP-based systems.
The main purpose of this dissertation is to solve above problems by the study of performance analysis of NP-based systems. And the dissertation makes the following contributions:
1. The dissertation presents the extended general network processors topology (EGNPT) and level based NP software depiction, which solve the problem of how to depict the different NPs'software and hardware architectures in universal form. The dissertation also realizes the mapping of the NPs'software architecture to multilevel parallelism. This work builds the base for the performance analysis of the NP-based applications with different software and hardware architectures.
2. The dissertation brings out "compute budget" and "times of memory accessing" restrictions when the software being mapped to hardware. These restrictions reduce the number of mapping set's (design space) elements and the complexity of the searching working. The constricting test of IPv4 Forward design space shows the original size is 8947848 times of the reduced size. This work makes the propriety objects for NP-based systems performance analyzing.
3. The dissertation presents a hierarchical performance analysis methodology for network processor applications, which overcomes the difficulties brought by NP's multilevel parallelism characteristic. The test results show that the error of this methodology is less than 8% and other performance analysis methods, whose errors are 10%-17%. The practice of the methodology in "IPv4 Forward", "NP-based Network Testing Platform" and "NP-based Network Inspecting System" shows that it can provide technology supports and references for the NP-based system's performance evaluating, designing and optimizing.
4. On the application/function level, the dissertation presents a line based analysis methodology to solve the multithreads program performance evaluation. The test results of IPv4 Forward show that the error of this methodology is 0.47%. This work provides highly accurate parameters for the performance model on system/platform level.
5. On the system/platform level, the dissertation models the system using a GI/G/m/∞/FCFS queueing network, which solves the performance analysis of multiclass inputs and multiserver node open queueing network. The model depicts the system more closely to the real world than other models, which use one class customer, Poisson arrival process and Exponential serve time distribution queueing network to model the system.
6. The dissertation uses decomposition to solve the GI/G/m/∞/FCFS muliclass open queueing network, and gives a new formula for the coefficient of variation of the interdeparture times. Based on this method, the dissertation designs a queueing network based packet random sending algorithm and implements it in the "NP-based Network Test Platform".
The dissertation make efforts in NP software and hardware depictions and mapping relations, NP's multilevel parallel program performance analysis and queueing networks based performance model. Further researches will be needed, including:
a. more testing and evaluating of difference applications on various hardware platforms to validate the universality of the dissertation's methodology.
b. further studies of NP's instructions parallelism and more analysis of program/data relativity.
c. building performance analyzing software tools with the methodology of this dissertation.
近年来,网络处理器技术的发展不尽人意,特别是在利用网络处理器进行应用系统开发时,面临着缺乏能在异构的软硬件体系结构间进行合理的系统设计方案评估,并为网络处理器系统的设计和优化提供技术支撑和参考依据的性能分析方法。
本文的主要研究目的是：开展网络处理器系统的性能分析方法研究,为网络处理器系统研发中的方案评估、系统设计、系统改进等阶段提供技术支撑和参考依据。即对众多的器件和系统设计方案进行评估,选择适合需求的性价比好的方案；分析已有的方案和系统的性能缺陷和瓶颈,并根据这些因素改进和提高系统性能；对将要设计的系统进行性能预测,在性能成本方面实现最佳设计和配置。本文的主要贡献与创新总结如下：
1、提出了扩展的通用网络处理器结构(Extended General Network Processor Topology,简称EGNPT)和网络处理器软件分层描述法,实现了不同网络处理器软硬件体系结构的统一描述以及网络处理器的软件结构和多级并行层次间的映射,为在不同软硬件结构的网络处理器系统间进行性能分析工作奠定了基础。
2、提出了将“可用计算周期”和“访存次数”作为约束条件的网络处理器软硬件结构映射方法,压缩了网络处理器应用设计空间(Design Space)(针对基准测试用例IPv4Forward的实验结果表明该方法的压缩比例高达8947848倍),有效降低了设计空间内搜索的复杂度,形成了合理的性能分析对象集合。
3、提出了“基于分层架构的网络处理器系统性能分析方法”,实现了对网络处理器这种多级并行系统的性能评估。实验结果表明该方法的误差小于8%,高于现有各种性能分析方法的精度(误差为10%—17%)。NPF基准测试用例IPv4 Forward的设计方案评估、“基于网络处理器的网络测试平台”的系统设计、“基于网络处理器的网络监控系统”的系统改进等工程实践证明：该方法可以有效的为网络处理器系统的方案评估、系统设计和系统改进等工作提供技术支撑和参考依据。
4、在应用功能层面,提出了“线段分析法”,实现了对网络处理器处理单元(Processing Element,简称PE)中多线程程序的性能分析。针对IPv4 Forward的实验结果表明该方法误差仅为0.47%,为进一步采用排队网络进行系统平台层面的性能分析提供了高精度的所需参数。
5、在系统平台层面,提出了“基于GI/G/m/∞/FCFS多类型客户开放排队网络”的性能分析模型,利用非乘积形式解排队网络(Non-Product-Form Queueing Networks)描述网络处理器系统,实现了对多类型输入、多服务员服务台的开放网络的性能分析。相对于现有研究成果(仅采用单一客户类型、单服务员服务台和泊松到达过程/负指数服务时间分布的排队网络进行建模),该模型提高了对现实系统的描述贴近度。
6、采用分解法对GI/G/m/∞/FCFS多类型客户输入开放排队网络求解,给出了一种新型流通阶段(Flow)输出流到达时间间隔变异系数(Coefficient of Variation)的求解方法。基于该方法设计了“基于排队网络的包随机发送算法”,并应用到河南省杰出人才创新基金项目“基于网络处理器的网络测试平台”中,实现了高速随机测试流量的生成。
本文在网络处理器软硬件结构抽象描述及其映射、设计空间压缩、具有多级并行机制的网络处理器系统性能分析方法、基于排队网络的性能分析模型等方向做了较为深入细致的研究,但仍存在有待进一步研究的问题,包括：在不同体系结构的网络处理器平台上验证本文提出的“基于分层架构的网络处理器系统性能分析方法”的普适性；研究网络处理器的指令级并行和程序/数据的相关性对网络处理器系统性能的影响；基于本文提出的性能分析方法研发自动化性能分析工具。
From the birth of network processors (NP), they gain lots of attentions from many companies and researchers, because of their high performance, programmable, extendable and fast to markets characteristics. More than 30 companies have brought out more than 500 products or designs. Cisco, ALCATE, Deceng, HuaWei 3Com etc. have built routers, switches and security devices using these processors.
But now, the development of network processors technology doesn't match people's wish. Especially when building a system with NPs, we have to face the fact that the absence of a performance analysis methodology, which can help us evaluate the various designs among different hardware and software architectures, design and optimize NP-based systems.
The main purpose of this dissertation is to solve above problems by the study of performance analysis of NP-based systems. And the dissertation makes the following contributions:
1. The dissertation presents the extended general network processors topology (EGNPT) and level based NP software depiction, which solve the problem of how to depict the different NPs'software and hardware architectures in universal form. The dissertation also realizes the mapping of the NPs'software architecture to multilevel parallelism. This work builds the base for the performance analysis of the NP-based applications with different software and hardware architectures.
2. The dissertation brings out "compute budget" and "times of memory accessing" restrictions when the software being mapped to hardware. These restrictions reduce the number of mapping set's (design space) elements and the complexity of the searching working. The constricting test of IPv4 Forward design space shows the original size is 8947848 times of the reduced size. This work makes the propriety objects for NP-based systems performance analyzing.
3. The dissertation presents a hierarchical performance analysis methodology for network processor applications, which overcomes the difficulties brought by NP's multilevel parallelism characteristic. The test results show that the error of this methodology is less than 8% and other performance analysis methods, whose errors are 10%-17%. The practice of the methodology in "IPv4 Forward", "NP-based Network Testing Platform" and "NP-based Network Inspecting System" shows that it can provide technology supports and references for the NP-based system's performance evaluating, designing and optimizing.
4. On the application/function level, the dissertation presents a line based analysis methodology to solve the multithreads program performance evaluation. The test results of IPv4 Forward show that the error of this methodology is 0.47%. This work provides highly accurate parameters for the performance model on system/platform level.
5. On the system/platform level, the dissertation models the system using a GI/G/m/∞/FCFS queueing network, which solves the performance analysis of multiclass inputs and multiserver node open queueing network. The model depicts the system more closely to the real world than other models, which use one class customer, Poisson arrival process and Exponential serve time distribution queueing network to model the system.
6. The dissertation uses decomposition to solve the GI/G/m/∞/FCFS muliclass open queueing network, and gives a new formula for the coefficient of variation of the interdeparture times. Based on this method, the dissertation designs a queueing network based packet random sending algorithm and implements it in the "NP-based Network Test Platform".
The dissertation make efforts in NP software and hardware depictions and mapping relations, NP's multilevel parallel program performance analysis and queueing networks based performance model. Further researches will be needed, including:
a. more testing and evaluating of difference applications on various hardware platforms to validate the universality of the dissertation's methodology.
b. further studies of NP's instructions parallelism and more analysis of program/data relativity.
c. building performance analyzing software tools with the methodology of this dissertation.
引文
[1]Peter Brink, Manohar Castelino, David Meng, Chetan Rawal, Hari Tadepalli, Uday Naik. Network Processing Performance Metrics for IA-and IXP-Based Systems [J]. Intel Technology Journal,2003,14(07):77-91.
[2]任续烨.英特尔发布IXP23XX\IXP46X NP[N].中国计算机报,2004,11(22).
[3]谭章熹,林闯,任丰源,周文江.网络处理器的分析与研究[J].软件学报,2003,14(2)：255-265.
[4]Shan Zheng, Zhao Rong-cai, Xie Kang-min. A Model for NP-based Application Design[A]. In:Proceedings of the Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005)[C]. Dalian:IEEE Computer Society Press,2005:880-883.
[5]Intel Com. Intel(?) IXP2XXX Product Line of Network Processors Development Tools User' s Guide [EB/OL].:www.intel.com/design/network/products/npfamily/ixp2xxx.htm,2007:
[6]R. Allen, B. M. Bass, C. Basso. IBM PowerNP Network Processor:Hardware, software, and applications[J]. IBM Journal of Research and Development,2003,47(3):111-124.
[7]Wolf T, Franklin MA. CommBench—A Telecommunications Benchmark for Network Processors[A]. In:Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software[C]. Austin USA:IEEE Press,2000:154-162.
[8]Bycong Kil Lee, Lizy Kurian John. NPbench:A Benchark Suite for Control Plane and Data Plane Applications for Network Processors[A]. In:Proceedings of the 21th International Conference on Computer Design[C]. San Jose, CA:IEEE Press,2003:226-233.
[9]Memik G, Mangione-Smith B, Hu W. NetBench:A Benchmarking Suite for Network Processors[A]. In:Proceedings of the International Conference on Computer-Aided Design (ICCAD)[C]. San Jose:IEEE Computer Society Press,2001:39-43.
[10]S. Audenaert, P. Chandra. Network Processors Benchmark Framework, NPF Benchmaring Workgroup[EB/OL].:http://www.npforum.org/.2007:
[11]Mel Tsai, Chidamber Kulkarni. A Benchmarking Methodology for Network Processors [A]. In:Proceedings of the First Workshop on Network Processors & Applications (NP-1) in conjunction with 8th International Symposium on High Performance Computer Architecture (HPCA-8)[C]. San Fransisco USA:Morgan Kaufmann,2002:141-165.
[12]Hao Che, C. Kumar, B. Menasinahal, C. Lam, J. Chao. An Analytical Network Processor Performance Analysis Methodology[R]. Arlington USA:University of Texas at Arlington, 2005.
[13]Wen Xu, Larry Peterson, Support for Software Performance Tuning on Network Processors[J], IEEE Network,2003,17(4):40-45.
[14]Sridhar Lakshmanamurthy, Kin-Yip Liu, Yim Pun, Larry Huston, Uday Naik. Network Processor Performance Analysis Methodology[J]. Intel Technology Journal,2002,06(03): 19-28.
[15]Intel Corp. Intel Internet Exchange Architecture Software Building Blocks Applications Design Guide[DB/OL].:http://www.intel.com/design/network/products/npfamily.htm, 2004:
[16]S. Ramakrishna, H. Jamadagni. Analytical Bounds on the Threads in IXP1200 Network Processor[A]. In:Proceedings of the Euromicro Symposium on Digital System Design (DSD'03)[C]. Antalya, Turkey:IEEE Press,2003:426-429.
[17]Patrick Crowley, Jean-Loup Baer. Worst-Case Performance Estimation for Hardware-assisted Multithreaded Processors [A] In:Proceedings of the HPCA-9 Workshop on Network Processors[C]. Anaheim, California, USA:IEEE Press,2003:36-47.
[18]Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe. Cache Modeling for Real-time Software: Beyond Direct Mapped Instruction Caches[A]. In:Proceedings of the IEEE Real-Time Systems Symposium (RTSS'96)[C]. London:IEEE Press,1996:856-859.
[19]Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Kunzli. Design Space Exploration of Network Processor Architectures[A]. In:Proceedings of the 8th International Symposium on High Performance Computer Architecture [C]. Cambridge, MA:Morgan Kaufmann Publishers,2002.
[20]Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Kunzli. A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures [A]. In:Proceedings of the 39th Design Automation Conference (DAC)[C]. New Orleans, USA:ACM Press,2002: 880-892.
[21]Mark Franklin, Eric Tyson, James Buckley, Patrick Crowley, John Maschmeyer. Auto-Pipe and the X Language:A Pipeline Design Tool and Description Language[A]. In: Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS)[C]. Rhodes Island, Greece:IEEE Press,2006.
[22]Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures [A]. In:Mark A. Franklin, Patrick Crowley, Haldun Hadimioglu, Peter Z. Onufryk, Eds. Network Processor Design: Issues and Practices[M]. NewYork:Morgan Kaufmann,2005:277-306.
[23]Ning Weng, Tilman Wolf. Profiling and Mapping of Parallel Workloads on Network Processors[A]. In:Proceedings of the 20th Annual ACM Symposium on Applied Computing (SAC)[C]. Santa Fe, NM:ACM Press,2005:890-896.
[24]Ning Weng, Tilman Wolf. Analytic Modeling of Network Processors for Parallel Workload Mapping[EB/OL].:www.ecs.umass.edu/ece/wolf/pubs/unpublished/tecs.pdf,2007:(to appear in ACM Transactions on Embedded Computing Systems)
[25]Niraj Shah, William Plishker, Kurt Keutzer. NP-Click:A Programming Model for the Intel IXP1200[A].:In:Proceedings of 9th Intl Symposium on High Performance Computing Architectures (HPCA-9)[C]. Anaheim, California, USA:IEEE Press,2003.
[26]E. Kohler et al. The Click Modular Router[J]. ACM Transactions on Computer Systems, 2000,18(3):263-297.
[27]Gokhan Memik, William H. Mangione-Smith. NEPAL:A Framework for Efficiently Structuring Applications for Network Processors[A]. In:Proceedings of the Workshop on Network Processors (NP-2),9th Intel Symposium on High Performance Computing Architectures (HPCA-9)[C]. Anaheim,California:IEEE Computer Society Press,2003.
[28]Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Kunzli. Design Space Exploration of Network Processor Architectures[A]. In:Proceedings of the Workshop on Network Processors, at the 8th International Symposium on High-Performance Computer Architecture (HPCA8)[C]. Cambridge MA, USA:IEEE Computer Society Press,2002.
[29]Shan zheng, Zhao Rong-cai, Xie Kang-min. Network Performance Evaluation Framework[A]. In:Proceedings of the International Conference of Communication Technologies ICCT2006[C]. GuiLin:IEEE Press,2006:451-454.
[30]Jie Lu, Jie Wang. Analytical Performance Analysis of Network-Processor-Based Application Designs[A]. In:Proceedings of the Computer Communications and Networks ICCCN 2006[C]. Arlington VA USA:IEEE Press,2006:33-39.
[31]A. Seidmann, P. Schweitzer, S. Shalev-Oren. Computerized Closed Queueing Network Models of Flexible Manufacturing Systems[J]. Large Scale Systems,1987:12.
[32]Jing Fu. Queueing Behavior and Packet Delays in Network Processor[EB/OL]. www.ee.kth.se/php/modules/publications/reports/2007/IR-EE-LCN_2007_011.pdf,2007:
[33]Mirza Omer Beg. Performance Analysis of Packet Forwarding on IXP2400 Network Processor[R]. Waterloo, Ontario, Canada:University of Waterloo,2006.
[34]Antonia Bertolino, Alvise Bonivento, Guglielmo De Angelis, Alberto Sangiovanni Vincentelli. Modeling and Early Performance Estimation for Network Processor Applications [J]. Lecture Notes in Computer Science,2006,4199:753-767
[35]林闯.随机Petri网和系统性能评价(第2版)[M].北京：清华大学出版社,2005.
[36]S.Afsharian, A.Bertolino, G.De Angelis, P. Iovanna, R. Mirandola. A Model Based Approach to Design Applications for Network Processor[A], In:Proceedings of the First International Workshop on Rapid Integration of Software Engineering Techniques, RISE2004[C]. Luxembourg-Kirchberg:Springer,2004.
[37]张宏科,苏伟,武勇.网络处理器原理与技术[M].北京：北京邮电大学出版社,2004.
[38]Gunter Bolch, Stefan Greiner, Hermann de Meer, Kishor S. Trivedi. Queueing Networks and Markov Chains Modeling and Performance Evaluation with Computer Science Applications (Second Edition)[M]. New Jersey:John Wiley & Sons,2006.
[39]Erol Gelenbe, Guy Pujolle. Introduction to Queueing Networks (second editon)[M]. Paris: John Wiley & Sons,1998.
[40]R. M. Karp. An Introduction to Randomized Algorithms [J]. Discrete Applied Mathematics, 1991,34(3):165-201.
[41]R. Motwani, P. Raghavan. Randomized Algorithms[M]. New York:Cambridge University Press,1995.
[42]D. Meng, E. Eduri, M. Castelino. IXP2400 Intel Network Processor IPv4 Forwarding Benchmark Full Disclosure Report for Gigabit Ethernet Revision 1.0[EB/OL]. http://www.intel.com/design/network/products/npfamily/IXP 2400_IPv6.pdf,2003-3-5:
[43]盛友招.排队论及其在计算机通信中的应用[M].北京：北京邮电大学出版社,1998.
[44]Ning Weng, Tilman Wolf. Pipelining vs. Multiprocessors-Choosing the Right Network Processor System Topology[A]. In:Proceedings of the Advanced Networking and Communications Hardware Workshop in conjunction with The 31st Annual International Symposium on Computer Architecture[C]. New York NY USA:ACM Press,2004: 890-896.
[45]胡红艳.基于项目管理的软件产品研发管理研究[J].企业技术开发,2006,25(11)：99-102.
[46]A. Bertolino, G. De Angelis, R. Mirandola. UML-based Design of Network Processor Applications [A]. In:Proceedings of the 31st EUROMICRO Conference on Software Engineering and Advanced Applications-Volume 00 EUROMICRO'05 [C]. San Jose: IEEE Computer Society,2005:424-431.
[47]张铮.基于NP构建**专用系统研究[D].郑州：解放军信息工程大学,2007：
[48]MMC Networks. EPIF-200 Packet Processor Product Overview[EB/OL]. http://www.mmcnet.com,2003:
[49]Intel Corporation. IXP1200 Network Processor Family Hardware Reference Manual[EB/OL].:http://developer.intel.com/design/network/ixa.html,2001:
[50]Intel Corporation. Intel IXP2400 Network Processor[EB/OL].:http://www.intel.com/ design/network/products/npfamily/ixp2400.htm,2004:
[51]Intel Corporation. Intel IXP2800 Network Processor[EB/OL].:http://www.intel.com/ design/network/products/npfamily/ixp2800.htm,2004:
[52]Hifn Tech. Hifn,5NP4G Network Processor [EB/OL].:http://www.hifn.com/products /5np4g.html,2007:
[53]Agere Microelectronics Group. PayloadPlus Routing Switch Processor[J]. Preliminary Product Brief, Lucent Technologies,2000, (4).
[54]Motorola Corporation. Motorola C-5 DCP Architecture Guide[EB/OL]. http://www.motorola.com,2002:
[55]EZCHIP Technologies. Network Processor Designs for Next-Generation Networking Equipment[EB/OL].:http://www.ezchip.com/,2002:
[56]赵凤华.网络处理器芯片原型诞生清华[N].科技日报,2005,12(29).
[57]K. Keutzer, S. Malik, AR Newton. From ASIC to ASIP:The Next Design Discontinuity[A]. In:Proceedings of the IEEE International Conference on Computer Design[C]. Washington:IEEE Computer Science Press,2002:84-88.
[58]Shah N, Keutzer Kurt. Network Processors:Origin of Species[A]. In:Proceedings of the the Seventeenth International Symposium on Computer and Information Sciences ISCIS XVII[C], Orlando, Florida, US A:Springer,2002.
[59]E.Comer, D.网络处理器与网络系统设计[M].北京：电子工业出版社,2004.
[60]Cisco Systems. Parallel eXpress Forwarding in the Cisco 10000 Edge Service Router[EB/OL].:www.cisco.com/en/US/products/hw/routers/ps133/products_white_pap er09186a008008902a.shtml, October 2000:
[61]BRECIS Communications. MSP5000 Multi-Service Processor Product Brief[EB/OL]. www.pmc-sierra.com/products/details/msp5000/.2001:
[62]Narendra Sankar. CNP810 Network Services Processor Family[EB/OL].:Network Processor Forum, http://www.npforum.org,2001:
[63]Rupan Roy. A Monolithic Packet Processing Architecture Monolithic Packet Processing Architecture [EB/OL].:Network Processor Forum, http://www. npforum.org,2001:
[64]Panos C. Lekkas. Network Processor Architectures, Protocol, and Platforms[M] New York: McGraw-Hill Companies, Inc,2003.
[65]T. Eklund. The World's First 40Gbps (OC-768) Network Processor. Presentation[EB/OL]. Network Processor Forum, http://www.npforum.org,2001:
[66]Madhu Sudanan Seshadri, John Bent, Tevfik Kosar. Network Processors:Guiding Design Through Analysis [EB/OL]. http://www.cs.wisc.edu/～johnbent/Projects/net_proc.pdf, 2001:
[67]Y.-K. Kwok, I. Ahmad. FASTEST:A Practical Low Complexity Algorithm for Compile-time Assignment of Parallel Programs to Multiprocessors[J]. IEEE Trans. Parallel Distributed Systems,1999,10(2):147-159.
[68]Y.-K. Kwok and I. Ahmad. Static Scheduling Algorithms for Allocating Directed Task Graphs to Multiprocessors[J]. ACM Computing Surveys,1999,31(4):406-471.
[69]D. Burger, T. Austin. The SimpleScalar Tool Set Version 2.0[J]. Computer Architecture News,1997,25(3):13-25.
[70]Shan Zheng, Zhao Rong-cai, Xie Kang-min. Performance Analysis of Different Length Packets Processing by Network Processor Based Application[A]. In:Proceedings of International Symposium on Communications And Information Technologies 2006 (ISCIT 2006)[C]. Bangkok Thailand:IEEE Computer Society Press,2006:21-24.
[71]C. Clark, W. Lee, D. Schimmel, D. Contis, M. Kone, A. Thomas. A Hardware Platform for Network Intrusion Detection and Prevention[A]. In:Proceedings of the 3rd Workshop on Network Processors and Applications (NP3)[C]. San Fransisco USA:Morgan Kaufmann Publishers,2004.
[72]M. Adiletta, D. Hooper, M.Wilde. Packet Over SONET:Achieving 10 Gigabit/sec Packet Processing with IXP2800[J]. Intel Technology Journal,2002,6(3).
[73]J. Hasan,S.Chandra, T. N. Vijaykumar. Efficient Use of Memory Bandwidth to Improve Network Processor Throughput[A]. In:Proceedings of the The 30th International Symposium on Computer Architecture (ISCA)[C]. San Diego, California:ACM Press, 2003:288-299.
[74]V. Krishnan, J. Torrellas. A Chip-Multiprocessor with Speculative Multithreading [J]. IEEE Transactions on Computers,1999,48:866-880.
[75]Jeffrey T. Oplinger, David L. Heine, Monica S. Lam. In Search of Speculative Thread-Level Parallelism[A]. In:Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)[C]. California, USA:IEEE Computer Society,1999: 303-313.
[76]E.Brockmeyer, H.L. Halstrom, A.Jensen. The Life and Works of A.K.Erlang[J]. Journal of the Royal Statistical Society. Series A (General),1951,114(1):103-104.
[77]A. Y. Klintchine. Mathmetical Methods in the Theory of Queueing[M]. London:Kluwer Academic Publishers,1994.
[78]D. G. Kendal. Some Problems in The Theory of Queues[J]. Journal of the Royal Statistical Society Serial B,1951,13(2):151-185.
[79]Cohen. JW. The Single Server Queue[M]. Amsterdara:North-Holland,1982.
[80]Cooper, R.B. Introduction to Queueing Theory[M]. New York:North-Holland,1987.
[81]Gross,D., Harris,C.M. Fundamentals of Queueing Theory[M]. New York:Wiley,1985.
[82]JR.Jackson. Networks of Waiting Lines[J]. Operations Research,1957,5:518-521.
[83]W.J.Gondon, G.F.Newel. Closed Queueing Systems with Exponential Severs[J]. Operations Research,1967,15:254-265.
[84]F.Baskett, K.M.Chandy, R.R.Munty, F.GPaaaciss. Open, Closed and Mixed Networks of Queue Swith Different Classes of Customers[J]. Journal of the ACM,1975,22(2): 248-260.
[85]徐光辉.随机服务系统[M].北京：科学出版社,1980.
[86]董泽清.排队论及其应用[M].西安：西安系统工程学会,1983.
[87]陆凤山.排队论及其应用[M].长沙：湖南科学技术出版社,1984.
[88]孟玉坷.排队论基础及应用[M].上海：同济大学出版社,1989.
[89]P. Chylla. Zur Modellierung und approximativen Leistungsanalyse von Vielteilnehmer-Rechensystemen[D]. Munich Germany:Faculty for Mathematics and Computer Science, Technical University Munich,1986:479,481.
[90]G. Pujolle, W. Ai. A Solution for Multiserver and Multiclass Open Queueing Networks[J]. Information Systems and Operations Research,1986,24(3):221-230,479,481,505,601.
[91]W. Whitt. Performance of the Queueing Network Analyzer[J]. Bell System Technical Journal,1983,62(9):2817-2843,479,481.
[92]W. Whitt. The Queueing Network Analyzer[J]. Bell System Technical Journal,1983,62(9): 2779-2815,479,481,601.
[93]E. Gelenbe, G. Pujolle. Introduction to Queueing Networks[M]. Hoboken New Jersey USA: John Wiley Chichester,1987:479,481.
[94]J. Little. A Proof of t,he Queuing Formula L=λW[J]. Operations Research,1961,9(3): 383-387,88,89,111,245,578.
[95]L. Kleinrock. Queueing Systems, volume 1:Theory[M]. New York:John Wiley,1975:38, 252,255,257,265.
[96]S. C. Borst,O. J. Boxma, R. N. Queija, A. P. Zwart. The Impact of the Service Discipline on Delay Asymptotics[J]. Performance Evaluation,2003,54(2):175-206,257.
[97]M. F. Neuts. Structurcd Stochastic Matrices of M/G/1 Type and Their Applications, volume 5 of Probability:Pure and Applied [M]. New York:Marcel Dekker,1989:259,260,314, 316.
[98]A. Riska, E. Smirni. M/G/1-Type Markov Processes:A Tutorial[J]. Performance Evaluation of Complex Systems:Techniques and Tools, Performance 2002, Lecture Notes in Computer Science,2002(2459):36-63.
[99]W. Marchal. Some Simpler Bounds on the Mean Queueing Time[J]. Operations Research, 1978,26(6):265,266,483.
[100]W. hlarchal. Simple Bounds and Approximations in Queueing Systems[D]. Washington, D.C.:George Washington University,1974:269.
[101]A. Allen. Probability, Statistics and Queueing Theory with Computer Science Applications[M]. New York:Academic Press,1990:15,51,252,265,266,270,483.
[102]S. Brumelle. Some Inequalities for Parallel-Server Queues[J]. Operations Research,1971, 19:402-413,269.
[103]T. Kimura. Heuristic Approximations for the Mean Waiting Time in the GI/G/s Queue. Technical Report B55[R]. Tokyo:Institute of Technology,1985:
[104]J. Kingman. Inequalities in the Theory of Queues[J]. Journal of the Royal Statistical Society,1970,32:102-110,269.
[105]Tammo Spalink, Scott Karlin. Evaluating Network Processors in IP Forwarding[R]. Larry Peterson:Princeton University,2000.
[106]Mahias Gries, Ghidamber Kulkarni, Christian Sauer, Kurt Keutzer. Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors[A]. In:Proceedings of Second Network Processor Workshop (NP-2) in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, CA:IEEE Press,2003:75-87.
[107]Peter Bazan. Winpepsy Guid [EB/OL].:http://www7.informatik.uni-erlangen.de/-prbaz an/pepsy/pepsy.short.manual.pdf,2003:
[108]Patrick Crowley, Jean-Loup Baer. A Modeling Framework for Network Processor Systems[A]. In:Proceedings of the HPCA-8 Workshop on Network Processors[C]. Cambridge, MA:IEEE Press,2002.
[109]Patrick Crowley,Jean-Loup Baer. A Hybrid Framework for Network Processor System Analysis[EB/OL].:http://www.cs.washington.edu/homes/baer/npm_perf.pdf,2003:
[110]Hao Che, Chethan Kumar,Basavaraj Menasinahal. A Fast Latency Bound Estimation Algorithm for a Multithreaded Network Processor [A]. In:Proceedings of the Parallel and Distributed Computing and Systems (PDCS 2006)[C]. Dallas, TX, USA:ACTA Press, 2006:513-137.
[111]Prashant R. Chandra. IPv4 Forwarding Application-Level Benchmark Implementation Agreement[EB/OL].:http://www.oiforum.com/public/documents/IPv4IARev.pdf,2002:
[112]钱颂迪,甘英爱,田丰.运筹学(修订版)[M].北京：清华大学出版社,1990.
[113]邓斌,黄洪钟.多目标模糊优化的数学模型及其求解原理和方法[J].机械设计与研究,1996,(1)：8-13.
[114]傅德友,刘庆怀.广义函数D—赋值意义下的多目标规划模型[J].吉林工业大学学报,1995,25(4)：60-63.
[115]李荣钧.含指数型隶属函数的模糊多目标规划分析[J].系统工程,2002,20(2)：10-14.
[116]Spirent Communications. Spirent SmartBits Trusted Industry Standard for Router and Switch Testing[EB/OL].:http://www.spirentcom.com/analysis/technology.cfm?media=7& ws=325&ss=110&stype=15&a=1,2007:
[117]Agilent Technologies. Solution Provides Real-World Security, Performance and Scalability Testing for Advanced Network Devices[EB/OL].:http://www.agilent.com/about/newsroo m/presrel/2007/18jun-em07103.html,2007:
[118]IXIA Corporation. IXIA Product Catalog[EB/OL].:http://www.internet2.edu/assets/appl ets/DS-IXIAChassis.pdf,2005:
[119]姚雄,秦肖臻,王卓,汪秉文.基于嵌入式系统的网络测试仪[J].微机发展,2005,15(2)：103-105.
[120]连光耀,黄考利,李天刚.基于DCOM技术的分布式网络测试系统设计[J].仪表技术,2004,(03)：17-19.
[121]谢鲲,张大方,文吉刚,谢高岗.基于WinPcap的实时网络监测系统[J].湖南大学学报(自然科学版),2006,33(2)：118-121.
[122]Stephen P. Smith, J. Allen Crider, Henry H. Perritt. Independent Review of the Carnivore System Final Report[R]. Lanham, Maryland:IIT Research Institute,2000-12-8.
[123]Tom Bowman, Scott Shane. Battling High-Tech Warriors[J]. Baltimore Sun,1995, (12).
[124]Patrick S. Poole. ECHELON:America's Secret Global Surveillance Network[EB/OL]. http://hiwaay.net/-pspoole/echelon.html,2000:
[125]Feng Zhang, Lester Lipsky. Modelling Restricted Processor Sharing[A]. In:Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, PDPTA 2006[C]. Las Vegas, Nevada, USA:CSREA Press,2006:353-359.
[126]Hammond L., Willey M., Olukotun K.. Data Speculation Support for a Chip-Multiprocessor [A]. In:Proceedings of ACM Conference on Architectural Support for Programming Languages and Operating Systems[C]. New York, USA:ACM Press,1998: 58-69.
[127]V. Krishnan, J. Torrellas. A Chip-Multiprocessor with Speculative Multithreading[J]. IEEE Transactions on Computers,1999,48:866-880.
[128]J. G. Steffan, T.C. Mowry. The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization[A]. In:Proceedings of Int. Symposium on High Performance Computer Architecture[C]. Washington DC, USA:IEEE Computer Society, 1998:2-13.
[129]Sohi, G. S., Breach, S. E., Vijaykumar, T. N. Multiscalar Processors[A]. In:Proceedings of 25 Years of The International Symposia on Computer Architecture[C]. New York NY USA: ACM Press,1998:111-114.
[130]Alexander Maxiaguine, Samarjit Chakraborty, Simon Kunzli, Lothar Thiele. Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms[J]. IEEE Design & Test of Computers,2004,21(5):368-377.
[131]Samarjit Chakraborty, Lothar Thiele. A New Task Model for Streaming Applications and Its Schedulability Analysis[A]. In:Proceedings of the IEEE Design Automation & Test in Europe[C]. Washington. DC. USA:IEEE Computer Society,2005:486-491.
[132]Mark A. Franklin, Tilman Wolf. A Network Processor Performance and Design Model with Benchmark Parameterization[A]. In:Patrick Crowley, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk. Network Processor Design:Issues and Practices[M]. NewYork:Morgan Kaufmann,2005:117-138.
[133]Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad. Characterizing Processor Architectures for Programmable Network Interfaces[A]. In:Proceedings of the 2000 International Conference on Supercomputing[C], Santa Fe, New Mexico:ACM Press, 2000:54-65.
[134]Ramaswamy Ramaswamy, Tilman Wolf. PacketBench:A Tool for Workload Characterization of Network Processing[A]. In:Proceedings of IEEE 6th Annual Workshop on Workload Characterization (WWC-6)[C]. Austin, TX:IEEE Press,2003: 42-50.
[135]Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf. Analysis of Network Processing Workloads[A]. In:Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)[C]. Austin, TX:IEEE Press,2005: 226-235.
[136]F. Baker. Requirements for IP Version 4 Routers (RFC 1812)[EB/OL].:http://www.ietf.org /rfc/rfc1812.txt,1995:
[137]D. Senie. Changing the Default for Directed Broadcasts in Routers (RFC 2644)[EB/OL].: http://www.ietf.org/rfc/rfc2644.txt,1999:
[138]S. Bradner. Benchmarking Terminology for Network Interconnection Devices (RFC 1242) [EB/OL].:http://www. ietf.org/rfc/rfc1242.txt,1991:
[139]S. Bradner, J. McQuaid. Benchmarking Methodology for Network Interconnect Devices (RFC 2544)[EB/OL].:http://www.ietf.org/rfc/rfc2544.txt,1999:
[140]R. Mandeville, J. Perser. Benchmarking Methodology for LAN Switching Devices (RFC 2889)[EB/OL].:http://www.ietf.org/rfc/rfc2889.txt,2000:
[141]D. Newman. Benchmarking Terminology for Firewall Performance (RFC 2647)[EB/OL]. http://www.ietf.org/rfc/rfc2647.txt,1999:
[142]B. Hickman, D. Newman, S. Tadjudin, T. Martin. Benchmarking Methodology for Firewall Performance (RFC 3511)[EB/OL].:http://www.ietf.org/rfc/rfc3511.txt,2003:
[143]安克,赵荣彩,单征.基于拟合的IXP 2400包发送速率控制技术[J].小型微型计算机系统,2007,28(9)：1610-1613.
[144]P. KUhn. Approximate Analysis of General Queuing Networks by Decomposition[J]. IEEE Transactions on Communication,1979,27(1):113-126.
[2]任续烨.英特尔发布IXP23XX\IXP46X NP[N].中国计算机报,2004,11(22).
[3]谭章熹,林闯,任丰源,周文江.网络处理器的分析与研究[J].软件学报,2003,14(2)：255-265.
[4]Shan Zheng, Zhao Rong-cai, Xie Kang-min. A Model for NP-based Application Design[A]. In:Proceedings of the Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005)[C]. Dalian:IEEE Computer Society Press,2005:880-883.
[5]Intel Com. Intel(?) IXP2XXX Product Line of Network Processors Development Tools User' s Guide [EB/OL].:www.intel.com/design/network/products/npfamily/ixp2xxx.htm,2007:
[6]R. Allen, B. M. Bass, C. Basso. IBM PowerNP Network Processor:Hardware, software, and applications[J]. IBM Journal of Research and Development,2003,47(3):111-124.
[7]Wolf T, Franklin MA. CommBench—A Telecommunications Benchmark for Network Processors[A]. In:Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software[C]. Austin USA:IEEE Press,2000:154-162.
[8]Bycong Kil Lee, Lizy Kurian John. NPbench:A Benchark Suite for Control Plane and Data Plane Applications for Network Processors[A]. In:Proceedings of the 21th International Conference on Computer Design[C]. San Jose, CA:IEEE Press,2003:226-233.
[9]Memik G, Mangione-Smith B, Hu W. NetBench:A Benchmarking Suite for Network Processors[A]. In:Proceedings of the International Conference on Computer-Aided Design (ICCAD)[C]. San Jose:IEEE Computer Society Press,2001:39-43.
[10]S. Audenaert, P. Chandra. Network Processors Benchmark Framework, NPF Benchmaring Workgroup[EB/OL].:http://www.npforum.org/.2007:
[11]Mel Tsai, Chidamber Kulkarni. A Benchmarking Methodology for Network Processors [A]. In:Proceedings of the First Workshop on Network Processors & Applications (NP-1) in conjunction with 8th International Symposium on High Performance Computer Architecture (HPCA-8)[C]. San Fransisco USA:Morgan Kaufmann,2002:141-165.
[12]Hao Che, C. Kumar, B. Menasinahal, C. Lam, J. Chao. An Analytical Network Processor Performance Analysis Methodology[R]. Arlington USA:University of Texas at Arlington, 2005.
[13]Wen Xu, Larry Peterson, Support for Software Performance Tuning on Network Processors[J], IEEE Network,2003,17(4):40-45.
[14]Sridhar Lakshmanamurthy, Kin-Yip Liu, Yim Pun, Larry Huston, Uday Naik. Network Processor Performance Analysis Methodology[J]. Intel Technology Journal,2002,06(03): 19-28.
[15]Intel Corp. Intel Internet Exchange Architecture Software Building Blocks Applications Design Guide[DB/OL].:http://www.intel.com/design/network/products/npfamily.htm, 2004:
[16]S. Ramakrishna, H. Jamadagni. Analytical Bounds on the Threads in IXP1200 Network Processor[A]. In:Proceedings of the Euromicro Symposium on Digital System Design (DSD'03)[C]. Antalya, Turkey:IEEE Press,2003:426-429.
[17]Patrick Crowley, Jean-Loup Baer. Worst-Case Performance Estimation for Hardware-assisted Multithreaded Processors [A] In:Proceedings of the HPCA-9 Workshop on Network Processors[C]. Anaheim, California, USA:IEEE Press,2003:36-47.
[18]Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe. Cache Modeling for Real-time Software: Beyond Direct Mapped Instruction Caches[A]. In:Proceedings of the IEEE Real-Time Systems Symposium (RTSS'96)[C]. London:IEEE Press,1996:856-859.
[19]Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Kunzli. Design Space Exploration of Network Processor Architectures[A]. In:Proceedings of the 8th International Symposium on High Performance Computer Architecture [C]. Cambridge, MA:Morgan Kaufmann Publishers,2002.
[20]Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Kunzli. A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures [A]. In:Proceedings of the 39th Design Automation Conference (DAC)[C]. New Orleans, USA:ACM Press,2002: 880-892.
[21]Mark Franklin, Eric Tyson, James Buckley, Patrick Crowley, John Maschmeyer. Auto-Pipe and the X Language:A Pipeline Design Tool and Description Language[A]. In: Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS)[C]. Rhodes Island, Greece:IEEE Press,2006.
[22]Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures [A]. In:Mark A. Franklin, Patrick Crowley, Haldun Hadimioglu, Peter Z. Onufryk, Eds. Network Processor Design: Issues and Practices[M]. NewYork:Morgan Kaufmann,2005:277-306.
[23]Ning Weng, Tilman Wolf. Profiling and Mapping of Parallel Workloads on Network Processors[A]. In:Proceedings of the 20th Annual ACM Symposium on Applied Computing (SAC)[C]. Santa Fe, NM:ACM Press,2005:890-896.
[24]Ning Weng, Tilman Wolf. Analytic Modeling of Network Processors for Parallel Workload Mapping[EB/OL].:www.ecs.umass.edu/ece/wolf/pubs/unpublished/tecs.pdf,2007:(to appear in ACM Transactions on Embedded Computing Systems)
[25]Niraj Shah, William Plishker, Kurt Keutzer. NP-Click:A Programming Model for the Intel IXP1200[A].:In:Proceedings of 9th Intl Symposium on High Performance Computing Architectures (HPCA-9)[C]. Anaheim, California, USA:IEEE Press,2003.
[26]E. Kohler et al. The Click Modular Router[J]. ACM Transactions on Computer Systems, 2000,18(3):263-297.
[27]Gokhan Memik, William H. Mangione-Smith. NEPAL:A Framework for Efficiently Structuring Applications for Network Processors[A]. In:Proceedings of the Workshop on Network Processors (NP-2),9th Intel Symposium on High Performance Computing Architectures (HPCA-9)[C]. Anaheim,California:IEEE Computer Society Press,2003.
[28]Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon Kunzli. Design Space Exploration of Network Processor Architectures[A]. In:Proceedings of the Workshop on Network Processors, at the 8th International Symposium on High-Performance Computer Architecture (HPCA8)[C]. Cambridge MA, USA:IEEE Computer Society Press,2002.
[29]Shan zheng, Zhao Rong-cai, Xie Kang-min. Network Performance Evaluation Framework[A]. In:Proceedings of the International Conference of Communication Technologies ICCT2006[C]. GuiLin:IEEE Press,2006:451-454.
[30]Jie Lu, Jie Wang. Analytical Performance Analysis of Network-Processor-Based Application Designs[A]. In:Proceedings of the Computer Communications and Networks ICCCN 2006[C]. Arlington VA USA:IEEE Press,2006:33-39.
[31]A. Seidmann, P. Schweitzer, S. Shalev-Oren. Computerized Closed Queueing Network Models of Flexible Manufacturing Systems[J]. Large Scale Systems,1987:12.
[32]Jing Fu. Queueing Behavior and Packet Delays in Network Processor[EB/OL]. www.ee.kth.se/php/modules/publications/reports/2007/IR-EE-LCN_2007_011.pdf,2007:
[33]Mirza Omer Beg. Performance Analysis of Packet Forwarding on IXP2400 Network Processor[R]. Waterloo, Ontario, Canada:University of Waterloo,2006.
[34]Antonia Bertolino, Alvise Bonivento, Guglielmo De Angelis, Alberto Sangiovanni Vincentelli. Modeling and Early Performance Estimation for Network Processor Applications [J]. Lecture Notes in Computer Science,2006,4199:753-767
[35]林闯.随机Petri网和系统性能评价(第2版)[M].北京：清华大学出版社,2005.
[36]S.Afsharian, A.Bertolino, G.De Angelis, P. Iovanna, R. Mirandola. A Model Based Approach to Design Applications for Network Processor[A], In:Proceedings of the First International Workshop on Rapid Integration of Software Engineering Techniques, RISE2004[C]. Luxembourg-Kirchberg:Springer,2004.
[37]张宏科,苏伟,武勇.网络处理器原理与技术[M].北京：北京邮电大学出版社,2004.
[38]Gunter Bolch, Stefan Greiner, Hermann de Meer, Kishor S. Trivedi. Queueing Networks and Markov Chains Modeling and Performance Evaluation with Computer Science Applications (Second Edition)[M]. New Jersey:John Wiley & Sons,2006.
[39]Erol Gelenbe, Guy Pujolle. Introduction to Queueing Networks (second editon)[M]. Paris: John Wiley & Sons,1998.
[40]R. M. Karp. An Introduction to Randomized Algorithms [J]. Discrete Applied Mathematics, 1991,34(3):165-201.
[41]R. Motwani, P. Raghavan. Randomized Algorithms[M]. New York:Cambridge University Press,1995.
[42]D. Meng, E. Eduri, M. Castelino. IXP2400 Intel Network Processor IPv4 Forwarding Benchmark Full Disclosure Report for Gigabit Ethernet Revision 1.0[EB/OL]. http://www.intel.com/design/network/products/npfamily/IXP 2400_IPv6.pdf,2003-3-5:
[43]盛友招.排队论及其在计算机通信中的应用[M].北京：北京邮电大学出版社,1998.
[44]Ning Weng, Tilman Wolf. Pipelining vs. Multiprocessors-Choosing the Right Network Processor System Topology[A]. In:Proceedings of the Advanced Networking and Communications Hardware Workshop in conjunction with The 31st Annual International Symposium on Computer Architecture[C]. New York NY USA:ACM Press,2004: 890-896.
[45]胡红艳.基于项目管理的软件产品研发管理研究[J].企业技术开发,2006,25(11)：99-102.
[46]A. Bertolino, G. De Angelis, R. Mirandola. UML-based Design of Network Processor Applications [A]. In:Proceedings of the 31st EUROMICRO Conference on Software Engineering and Advanced Applications-Volume 00 EUROMICRO'05 [C]. San Jose: IEEE Computer Society,2005:424-431.
[47]张铮.基于NP构建**专用系统研究[D].郑州：解放军信息工程大学,2007：
[48]MMC Networks. EPIF-200 Packet Processor Product Overview[EB/OL]. http://www.mmcnet.com,2003:
[49]Intel Corporation. IXP1200 Network Processor Family Hardware Reference Manual[EB/OL].:http://developer.intel.com/design/network/ixa.html,2001:
[50]Intel Corporation. Intel IXP2400 Network Processor[EB/OL].:http://www.intel.com/ design/network/products/npfamily/ixp2400.htm,2004:
[51]Intel Corporation. Intel IXP2800 Network Processor[EB/OL].:http://www.intel.com/ design/network/products/npfamily/ixp2800.htm,2004:
[52]Hifn Tech. Hifn,5NP4G Network Processor [EB/OL].:http://www.hifn.com/products /5np4g.html,2007:
[53]Agere Microelectronics Group. PayloadPlus Routing Switch Processor[J]. Preliminary Product Brief, Lucent Technologies,2000, (4).
[54]Motorola Corporation. Motorola C-5 DCP Architecture Guide[EB/OL]. http://www.motorola.com,2002:
[55]EZCHIP Technologies. Network Processor Designs for Next-Generation Networking Equipment[EB/OL].:http://www.ezchip.com/,2002:
[56]赵凤华.网络处理器芯片原型诞生清华[N].科技日报,2005,12(29).
[57]K. Keutzer, S. Malik, AR Newton. From ASIC to ASIP:The Next Design Discontinuity[A]. In:Proceedings of the IEEE International Conference on Computer Design[C]. Washington:IEEE Computer Science Press,2002:84-88.
[58]Shah N, Keutzer Kurt. Network Processors:Origin of Species[A]. In:Proceedings of the the Seventeenth International Symposium on Computer and Information Sciences ISCIS XVII[C], Orlando, Florida, US A:Springer,2002.
[59]E.Comer, D.网络处理器与网络系统设计[M].北京：电子工业出版社,2004.
[60]Cisco Systems. Parallel eXpress Forwarding in the Cisco 10000 Edge Service Router[EB/OL].:www.cisco.com/en/US/products/hw/routers/ps133/products_white_pap er09186a008008902a.shtml, October 2000:
[61]BRECIS Communications. MSP5000 Multi-Service Processor Product Brief[EB/OL]. www.pmc-sierra.com/products/details/msp5000/.2001:
[62]Narendra Sankar. CNP810 Network Services Processor Family[EB/OL].:Network Processor Forum, http://www.npforum.org,2001:
[63]Rupan Roy. A Monolithic Packet Processing Architecture Monolithic Packet Processing Architecture [EB/OL].:Network Processor Forum, http://www. npforum.org,2001:
[64]Panos C. Lekkas. Network Processor Architectures, Protocol, and Platforms[M] New York: McGraw-Hill Companies, Inc,2003.
[65]T. Eklund. The World's First 40Gbps (OC-768) Network Processor. Presentation[EB/OL]. Network Processor Forum, http://www.npforum.org,2001:
[66]Madhu Sudanan Seshadri, John Bent, Tevfik Kosar. Network Processors:Guiding Design Through Analysis [EB/OL]. http://www.cs.wisc.edu/～johnbent/Projects/net_proc.pdf, 2001:
[67]Y.-K. Kwok, I. Ahmad. FASTEST:A Practical Low Complexity Algorithm for Compile-time Assignment of Parallel Programs to Multiprocessors[J]. IEEE Trans. Parallel Distributed Systems,1999,10(2):147-159.
[68]Y.-K. Kwok and I. Ahmad. Static Scheduling Algorithms for Allocating Directed Task Graphs to Multiprocessors[J]. ACM Computing Surveys,1999,31(4):406-471.
[69]D. Burger, T. Austin. The SimpleScalar Tool Set Version 2.0[J]. Computer Architecture News,1997,25(3):13-25.
[70]Shan Zheng, Zhao Rong-cai, Xie Kang-min. Performance Analysis of Different Length Packets Processing by Network Processor Based Application[A]. In:Proceedings of International Symposium on Communications And Information Technologies 2006 (ISCIT 2006)[C]. Bangkok Thailand:IEEE Computer Society Press,2006:21-24.
[71]C. Clark, W. Lee, D. Schimmel, D. Contis, M. Kone, A. Thomas. A Hardware Platform for Network Intrusion Detection and Prevention[A]. In:Proceedings of the 3rd Workshop on Network Processors and Applications (NP3)[C]. San Fransisco USA:Morgan Kaufmann Publishers,2004.
[72]M. Adiletta, D. Hooper, M.Wilde. Packet Over SONET:Achieving 10 Gigabit/sec Packet Processing with IXP2800[J]. Intel Technology Journal,2002,6(3).
[73]J. Hasan,S.Chandra, T. N. Vijaykumar. Efficient Use of Memory Bandwidth to Improve Network Processor Throughput[A]. In:Proceedings of the The 30th International Symposium on Computer Architecture (ISCA)[C]. San Diego, California:ACM Press, 2003:288-299.
[74]V. Krishnan, J. Torrellas. A Chip-Multiprocessor with Speculative Multithreading [J]. IEEE Transactions on Computers,1999,48:866-880.
[75]Jeffrey T. Oplinger, David L. Heine, Monica S. Lam. In Search of Speculative Thread-Level Parallelism[A]. In:Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)[C]. California, USA:IEEE Computer Society,1999: 303-313.
[76]E.Brockmeyer, H.L. Halstrom, A.Jensen. The Life and Works of A.K.Erlang[J]. Journal of the Royal Statistical Society. Series A (General),1951,114(1):103-104.
[77]A. Y. Klintchine. Mathmetical Methods in the Theory of Queueing[M]. London:Kluwer Academic Publishers,1994.
[78]D. G. Kendal. Some Problems in The Theory of Queues[J]. Journal of the Royal Statistical Society Serial B,1951,13(2):151-185.
[79]Cohen. JW. The Single Server Queue[M]. Amsterdara:North-Holland,1982.
[80]Cooper, R.B. Introduction to Queueing Theory[M]. New York:North-Holland,1987.
[81]Gross,D., Harris,C.M. Fundamentals of Queueing Theory[M]. New York:Wiley,1985.
[82]JR.Jackson. Networks of Waiting Lines[J]. Operations Research,1957,5:518-521.
[83]W.J.Gondon, G.F.Newel. Closed Queueing Systems with Exponential Severs[J]. Operations Research,1967,15:254-265.
[84]F.Baskett, K.M.Chandy, R.R.Munty, F.GPaaaciss. Open, Closed and Mixed Networks of Queue Swith Different Classes of Customers[J]. Journal of the ACM,1975,22(2): 248-260.
[85]徐光辉.随机服务系统[M].北京：科学出版社,1980.
[86]董泽清.排队论及其应用[M].西安：西安系统工程学会,1983.
[87]陆凤山.排队论及其应用[M].长沙：湖南科学技术出版社,1984.
[88]孟玉坷.排队论基础及应用[M].上海：同济大学出版社,1989.
[89]P. Chylla. Zur Modellierung und approximativen Leistungsanalyse von Vielteilnehmer-Rechensystemen[D]. Munich Germany:Faculty for Mathematics and Computer Science, Technical University Munich,1986:479,481.
[90]G. Pujolle, W. Ai. A Solution for Multiserver and Multiclass Open Queueing Networks[J]. Information Systems and Operations Research,1986,24(3):221-230,479,481,505,601.
[91]W. Whitt. Performance of the Queueing Network Analyzer[J]. Bell System Technical Journal,1983,62(9):2817-2843,479,481.
[92]W. Whitt. The Queueing Network Analyzer[J]. Bell System Technical Journal,1983,62(9): 2779-2815,479,481,601.
[93]E. Gelenbe, G. Pujolle. Introduction to Queueing Networks[M]. Hoboken New Jersey USA: John Wiley Chichester,1987:479,481.
[94]J. Little. A Proof of t,he Queuing Formula L=λW[J]. Operations Research,1961,9(3): 383-387,88,89,111,245,578.
[95]L. Kleinrock. Queueing Systems, volume 1:Theory[M]. New York:John Wiley,1975:38, 252,255,257,265.
[96]S. C. Borst,O. J. Boxma, R. N. Queija, A. P. Zwart. The Impact of the Service Discipline on Delay Asymptotics[J]. Performance Evaluation,2003,54(2):175-206,257.
[97]M. F. Neuts. Structurcd Stochastic Matrices of M/G/1 Type and Their Applications, volume 5 of Probability:Pure and Applied [M]. New York:Marcel Dekker,1989:259,260,314, 316.
[98]A. Riska, E. Smirni. M/G/1-Type Markov Processes:A Tutorial[J]. Performance Evaluation of Complex Systems:Techniques and Tools, Performance 2002, Lecture Notes in Computer Science,2002(2459):36-63.
[99]W. Marchal. Some Simpler Bounds on the Mean Queueing Time[J]. Operations Research, 1978,26(6):265,266,483.
[100]W. hlarchal. Simple Bounds and Approximations in Queueing Systems[D]. Washington, D.C.:George Washington University,1974:269.
[101]A. Allen. Probability, Statistics and Queueing Theory with Computer Science Applications[M]. New York:Academic Press,1990:15,51,252,265,266,270,483.
[102]S. Brumelle. Some Inequalities for Parallel-Server Queues[J]. Operations Research,1971, 19:402-413,269.
[103]T. Kimura. Heuristic Approximations for the Mean Waiting Time in the GI/G/s Queue. Technical Report B55[R]. Tokyo:Institute of Technology,1985:
[104]J. Kingman. Inequalities in the Theory of Queues[J]. Journal of the Royal Statistical Society,1970,32:102-110,269.
[105]Tammo Spalink, Scott Karlin. Evaluating Network Processors in IP Forwarding[R]. Larry Peterson:Princeton University,2000.
[106]Mahias Gries, Ghidamber Kulkarni, Christian Sauer, Kurt Keutzer. Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors[A]. In:Proceedings of Second Network Processor Workshop (NP-2) in conjunction with Ninth International Symposium on High Performance Computer Architecture (HPCA-9), Anaheim, CA:IEEE Press,2003:75-87.
[107]Peter Bazan. Winpepsy Guid [EB/OL].:http://www7.informatik.uni-erlangen.de/-prbaz an/pepsy/pepsy.short.manual.pdf,2003:
[108]Patrick Crowley, Jean-Loup Baer. A Modeling Framework for Network Processor Systems[A]. In:Proceedings of the HPCA-8 Workshop on Network Processors[C]. Cambridge, MA:IEEE Press,2002.
[109]Patrick Crowley,Jean-Loup Baer. A Hybrid Framework for Network Processor System Analysis[EB/OL].:http://www.cs.washington.edu/homes/baer/npm_perf.pdf,2003:
[110]Hao Che, Chethan Kumar,Basavaraj Menasinahal. A Fast Latency Bound Estimation Algorithm for a Multithreaded Network Processor [A]. In:Proceedings of the Parallel and Distributed Computing and Systems (PDCS 2006)[C]. Dallas, TX, USA:ACTA Press, 2006:513-137.
[111]Prashant R. Chandra. IPv4 Forwarding Application-Level Benchmark Implementation Agreement[EB/OL].:http://www.oiforum.com/public/documents/IPv4IARev.pdf,2002:
[112]钱颂迪,甘英爱,田丰.运筹学(修订版)[M].北京：清华大学出版社,1990.
[113]邓斌,黄洪钟.多目标模糊优化的数学模型及其求解原理和方法[J].机械设计与研究,1996,(1)：8-13.
[114]傅德友,刘庆怀.广义函数D—赋值意义下的多目标规划模型[J].吉林工业大学学报,1995,25(4)：60-63.
[115]李荣钧.含指数型隶属函数的模糊多目标规划分析[J].系统工程,2002,20(2)：10-14.
[116]Spirent Communications. Spirent SmartBits Trusted Industry Standard for Router and Switch Testing[EB/OL].:http://www.spirentcom.com/analysis/technology.cfm?media=7& ws=325&ss=110&stype=15&a=1,2007:
[117]Agilent Technologies. Solution Provides Real-World Security, Performance and Scalability Testing for Advanced Network Devices[EB/OL].:http://www.agilent.com/about/newsroo m/presrel/2007/18jun-em07103.html,2007:
[118]IXIA Corporation. IXIA Product Catalog[EB/OL].:http://www.internet2.edu/assets/appl ets/DS-IXIAChassis.pdf,2005:
[119]姚雄,秦肖臻,王卓,汪秉文.基于嵌入式系统的网络测试仪[J].微机发展,2005,15(2)：103-105.
[120]连光耀,黄考利,李天刚.基于DCOM技术的分布式网络测试系统设计[J].仪表技术,2004,(03)：17-19.
[121]谢鲲,张大方,文吉刚,谢高岗.基于WinPcap的实时网络监测系统[J].湖南大学学报(自然科学版),2006,33(2)：118-121.
[122]Stephen P. Smith, J. Allen Crider, Henry H. Perritt. Independent Review of the Carnivore System Final Report[R]. Lanham, Maryland:IIT Research Institute,2000-12-8.
[123]Tom Bowman, Scott Shane. Battling High-Tech Warriors[J]. Baltimore Sun,1995, (12).
[124]Patrick S. Poole. ECHELON:America's Secret Global Surveillance Network[EB/OL]. http://hiwaay.net/-pspoole/echelon.html,2000:
[125]Feng Zhang, Lester Lipsky. Modelling Restricted Processor Sharing[A]. In:Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, PDPTA 2006[C]. Las Vegas, Nevada, USA:CSREA Press,2006:353-359.
[126]Hammond L., Willey M., Olukotun K.. Data Speculation Support for a Chip-Multiprocessor [A]. In:Proceedings of ACM Conference on Architectural Support for Programming Languages and Operating Systems[C]. New York, USA:ACM Press,1998: 58-69.
[127]V. Krishnan, J. Torrellas. A Chip-Multiprocessor with Speculative Multithreading[J]. IEEE Transactions on Computers,1999,48:866-880.
[128]J. G. Steffan, T.C. Mowry. The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization[A]. In:Proceedings of Int. Symposium on High Performance Computer Architecture[C]. Washington DC, USA:IEEE Computer Society, 1998:2-13.
[129]Sohi, G. S., Breach, S. E., Vijaykumar, T. N. Multiscalar Processors[A]. In:Proceedings of 25 Years of The International Symposia on Computer Architecture[C]. New York NY USA: ACM Press,1998:111-114.
[130]Alexander Maxiaguine, Samarjit Chakraborty, Simon Kunzli, Lothar Thiele. Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms[J]. IEEE Design & Test of Computers,2004,21(5):368-377.
[131]Samarjit Chakraborty, Lothar Thiele. A New Task Model for Streaming Applications and Its Schedulability Analysis[A]. In:Proceedings of the IEEE Design Automation & Test in Europe[C]. Washington. DC. USA:IEEE Computer Society,2005:486-491.
[132]Mark A. Franklin, Tilman Wolf. A Network Processor Performance and Design Model with Benchmark Parameterization[A]. In:Patrick Crowley, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk. Network Processor Design:Issues and Practices[M]. NewYork:Morgan Kaufmann,2005:117-138.
[133]Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad. Characterizing Processor Architectures for Programmable Network Interfaces[A]. In:Proceedings of the 2000 International Conference on Supercomputing[C], Santa Fe, New Mexico:ACM Press, 2000:54-65.
[134]Ramaswamy Ramaswamy, Tilman Wolf. PacketBench:A Tool for Workload Characterization of Network Processing[A]. In:Proceedings of IEEE 6th Annual Workshop on Workload Characterization (WWC-6)[C]. Austin, TX:IEEE Press,2003: 42-50.
[135]Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf. Analysis of Network Processing Workloads[A]. In:Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)[C]. Austin, TX:IEEE Press,2005: 226-235.
[136]F. Baker. Requirements for IP Version 4 Routers (RFC 1812)[EB/OL].:http://www.ietf.org /rfc/rfc1812.txt,1995:
[137]D. Senie. Changing the Default for Directed Broadcasts in Routers (RFC 2644)[EB/OL].: http://www.ietf.org/rfc/rfc2644.txt,1999:
[138]S. Bradner. Benchmarking Terminology for Network Interconnection Devices (RFC 1242) [EB/OL].:http://www. ietf.org/rfc/rfc1242.txt,1991:
[139]S. Bradner, J. McQuaid. Benchmarking Methodology for Network Interconnect Devices (RFC 2544)[EB/OL].:http://www.ietf.org/rfc/rfc2544.txt,1999:
[140]R. Mandeville, J. Perser. Benchmarking Methodology for LAN Switching Devices (RFC 2889)[EB/OL].:http://www.ietf.org/rfc/rfc2889.txt,2000:
[141]D. Newman. Benchmarking Terminology for Firewall Performance (RFC 2647)[EB/OL]. http://www.ietf.org/rfc/rfc2647.txt,1999:
[142]B. Hickman, D. Newman, S. Tadjudin, T. Martin. Benchmarking Methodology for Firewall Performance (RFC 3511)[EB/OL].:http://www.ietf.org/rfc/rfc3511.txt,2003:
[143]安克,赵荣彩,单征.基于拟合的IXP 2400包发送速率控制技术[J].小型微型计算机系统,2007,28(9)：1610-1613.
[144]P. KUhn. Approximate Analysis of General Queuing Networks by Decomposition[J]. IEEE Transactions on Communication,1979,27(1):113-126.
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