WLAN射频接收机集成电路设计与研究
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摘要
无线本地局域网(Wireless Local Area Networks, WLAN)是计算机网络与无线通信技术相结合的产物,通过利用射频(Radio Frequency, RF)技术构成局域网络,不仅能够提供传统有线局域网的所有功能,而且可以使用无线信道来接入网络,为通信的移动化,个人化和多媒体应用提供了方便快捷的渠道,并成为宽带接入的有效手段之一。WLAN技术可以在空中传输数据、语音和视频信号,使得原先的有线网络所遇到的难题迎刃而解。现今,无线局域网室内数据传输可以达到数十米到几百米范围,而在室外也可以传输几十公里的距离。从WLAN的应用价值和前景来看,应用于无线局域网物理层中的射频接收集成电路也具有巨大的应用前景。如何实现低成本、高性能的无线射频接收机终端是一项具有挑战意义的工作。现今的无线通信射频接收机系统要求在保证极高灵敏度的前提下,尽可能提高接收机的线性度,以使系统的输出信号失真最小,误码率(Bit Error Rate, BER)最低。另外,接收机系统还要求尽可能的展宽射频输入、输出动态范围,使接收机的适应性更强,抗干扰能力更出色。以往,通常使用GaAs工艺制作射频接收集成电路,主要原因是这种工艺具有工作频率高、噪声低等优点。随着近年来CMOS工艺的不断进步,CMOS的频率特性和噪声特性逐步得到改善,采用CMOS工艺设计射频前端接收电路已成为可能。CMOS工艺还具有成本低、面积小、性能高等优势。CMOS工艺制作的射频电路易于和数字信号处理基带电路相兼容,符合片上系统(System on Chip, SOC)的发展的趋势。
本文基于TSMC0.18μm CMOS工艺设计了符合IEEE802.11a标准的射频前端接收机电路,并设计了版图。论文从系统级设计出发,首先讨论了零中频(直接变频)结构、超外差式结构和两次变频结构的工作原理以及各种结构对于结构中各电路模块性能要求的高低。在以上结构中,存在着各种各样的非理想特性,例如噪声,镜像频率(直接变频不存在镜像频率),非线性,失真,阻抗失配等,文章都进行了系统地分析。同时,列出了系统架构的重要参数指标,诸如噪声系数、镜频抑制比、增益、增益压缩点、3阶交调点以及输入输出阻抗匹配等。文章针对IEEE802.11a标准,对系统参数进行了认真分析后,确定了射频接收机的整体框架。随后,论文进行了各个电路模块的设计,包括低噪声放大器(Low Noise Amplifier, LNA),混频器(Mixer),自动增益控制(Automatic Gain Controller, AGC),跨导—电容中频滤波器(Gm-C filter)和sigma-delta ADC。有源CMOS LNA作为第一级,其噪声性能、增益和线性度是整个链路中影响最大的。因此,合理的设计LNA是至关重要的。文章还对LNA中的螺旋电感进行了优化设计,采用低电阻系数的Si衬底、Cu/SiO2互连工艺技术,并设计了适于WLAN的电感版图结构。混频器作为第二级电路,线性度、增益和噪声对整体电路的影响也是研究的重点。采用吉尔伯特单元为核心的混频器,前级增加输入缓冲级对本振信号进行放大,使得工作在开关状态的晶体管具有更好的开关特性,优化了混频器的线性度。中频滤波器采用跨导—电容滤波器,以满足系统大带宽的需求。自动增益控制模块AGC又称为可变增益放大器(Variable Gain Amplifier, VGA),实现整体链路总增益的调节功能,调节的主要依据是数字信号处理基带反馈的数字信号。VGA的主要参数是增益变化动态范围和增益步长。本文采用级联差分放大对的方式,根据数字基带的反馈信号实现各级增益的组合,从而达到54dB的动态范围和1.7dB的增益步长。最后一级模数转换器采用MASH21b-24b级联结构sigma-delta ADC。对于WLAN要求,ADC需要有10MHz的信号带宽。对于如此大的带宽要求,如果采用传统ADC,如流水线ADC,也可以实现模/数转换,但是功耗、面积都非常大。Sigma-delta模数转换器以其独特的工作机理放松了对模拟电路设计的要求,通过过采样,噪声整型及多位量化器技术降低带宽内的噪声,提高信噪比,从而提高ADC的精度。对多位DAC引入的非线性采用DWA数字校正方法。
采用Cadence Virtuoso layout Editor进行了整体电路的版图设计,并使用Diva/Dracula验证工具完成了各单元和整体链路的DRC(Design Rule Check)和LVS(Layout Versus Schematic)验证。整体电路输入信号为5.7GHz,噪声系数为9.284dB,输入阻抗匹配S11为-16dB,匹配阻抗50Ω,VGA输入控制位为默认值10011时,链路增益达到了45.95dB, IIP3为-16.7dBm,最大输入信号幅值-30dBm,达到了WLAN的性能指标要求。整个接收机(除频率合成器外)电流功耗为38mA,版图面积3mm×3mm。
WLAN(Wireless Local Area Networks) is a combinative product of computer networking and wireless communication technology. This new type network can not only realize all the functions which conditional wired networks can provide, but also access networks by wireless information channels. WLAN is a convenient and high speed network employed in mobility, individual communications and multimedia applications, and is an effective means of accessing broadband. Problems met in wired network can be easily solved in WLAN which transmits data, sounds and videos in air. Nowadays, WLAN can transmit data in the range of decade meters to several hundred meters indoor and several decade miles outdoor. In the respect of application and prospect of WLAN, the integrated radio frequency(RF) receiver used for WLAN physical levels has a great valuable prospect. How to realize a low cost but high performance RF receiver is a challenge. The system of RF receiver requires high linearity as far as possible while high sensitivity performance has been already achieved. Therefore, the harmonic distortion can be suppressed and low BER can be met. In addition, RF receiver requires large dynamic range of radio frequency input and output, which results in good adaptability and ability of anti-interference. In early times, the integrated RF receiver circuits were fabricated in GaAs technology which can work at a high frequency and has low noise. As the developing of CMOS technology, the frequency and noise characteristics of CMOS have been improved greatly nowadays and, therefore, fabricating the RF receiver circuits in CMOS technology can be realized very well. The CMOS technology has the advantages of low cost, small area and high performance, and can be easily integrated with digital baseband circuits according with the development of SOC(System on Chip).
This dissertation has deigned the integrated circuits of RF receiver for IEEE 802.11a standard and the layout based on TSMC 0.18um CMOS technology. Firstly, systematic design is introduced and mechanisms of homodyne receiver, heterodyne receiver and two-step do wn-convertor structure are analysed, then, requirements of each sub-modules are defined. There are many non-idealities in the structures mentioned above, such as noise, image frequency, nonlinearities, impedance mis-matchingwhich have been analysed in this paper. The important parameters such as noise figure(NF), image rejection ration(IRR), gain, 1dB compression(P1dB), input third-order intercept point(IIP3) are spread out. Then the architecture used for IEEE802.11a standard is decided after carefully analyzing the required characteristics. Sub-blocks including LNA, Mixer, AGC, Gm-C filter, AGC and sigma-delta ADC are therefore designed. As the first stage, passive CMOS LNA plays an important role that its noise performance, gain and linearity have a great influence to the whole chain. The second stage is mixer and its linearity, gain and noise are also key points of this paper. Gilbert unit is used as the core circuit of mixer and output signal of the locate oscillator is amplified by adding an input buffer, which makes the MOSFET work on a better switching state, then the linearity performance of mixer can be improved. Gm-C filter is used for the large bandwidth requirement. AGC, the so called Variable Gain Amplifier is used to change the gain of the chain by digital signal feedback from digital signal processing module. The main characteristics of AGC are dynamic range and gain step. Cascade differential amplifiers are used and the gain is decided by the feedback digital signal from digital base-band. The dynamic range and gain step are respectively 54dB and 1.7dB. The final stage is MASH21b-24b sigma-delta ADC. The WLAN system requires a bandwidth of 10MHz and the traditional ADC, such as pipelined ADC has a greater dissipation and occupied a larger area than sigma-delta ADC which can relax the requirements of system by its mechanism. The sigma-delta ADC reduces the noise in the interested band by noise shaping and multi-bit quantization and therefore improves the SNR and the precision of ADC. DWA is used for the non-linearity induced by multi-bit DAC。
The whole layout of the circuits is designed by using Cadence Virtuoso layout Edition. DRC(Design Rule Check) and LVS (Layout Versus Schematic) have been achieved by using Diva/Dracula. When the frequency of the input signal is 5.7GHz, the whole system has a NF of 9.284dB, S11-16dB, matched impedance 50Ω, gain of the whole link 45.95dB when input bits of VGA is 10011, IIP3-16.7dB, the maxim amplitude of input-30dBm. The simulation results meet the requirements of the WLAN. The whole receiver circuits (except for PLL) have a current dissipation of 38mA and the layout occupies an area of 3 mm×3mm.
本文基于TSMC0.18μm CMOS工艺设计了符合IEEE802.11a标准的射频前端接收机电路,并设计了版图。论文从系统级设计出发,首先讨论了零中频(直接变频)结构、超外差式结构和两次变频结构的工作原理以及各种结构对于结构中各电路模块性能要求的高低。在以上结构中,存在着各种各样的非理想特性,例如噪声,镜像频率(直接变频不存在镜像频率),非线性,失真,阻抗失配等,文章都进行了系统地分析。同时,列出了系统架构的重要参数指标,诸如噪声系数、镜频抑制比、增益、增益压缩点、3阶交调点以及输入输出阻抗匹配等。文章针对IEEE802.11a标准,对系统参数进行了认真分析后,确定了射频接收机的整体框架。随后,论文进行了各个电路模块的设计,包括低噪声放大器(Low Noise Amplifier, LNA),混频器(Mixer),自动增益控制(Automatic Gain Controller, AGC),跨导—电容中频滤波器(Gm-C filter)和sigma-delta ADC。有源CMOS LNA作为第一级,其噪声性能、增益和线性度是整个链路中影响最大的。因此,合理的设计LNA是至关重要的。文章还对LNA中的螺旋电感进行了优化设计,采用低电阻系数的Si衬底、Cu/SiO2互连工艺技术,并设计了适于WLAN的电感版图结构。混频器作为第二级电路,线性度、增益和噪声对整体电路的影响也是研究的重点。采用吉尔伯特单元为核心的混频器,前级增加输入缓冲级对本振信号进行放大,使得工作在开关状态的晶体管具有更好的开关特性,优化了混频器的线性度。中频滤波器采用跨导—电容滤波器,以满足系统大带宽的需求。自动增益控制模块AGC又称为可变增益放大器(Variable Gain Amplifier, VGA),实现整体链路总增益的调节功能,调节的主要依据是数字信号处理基带反馈的数字信号。VGA的主要参数是增益变化动态范围和增益步长。本文采用级联差分放大对的方式,根据数字基带的反馈信号实现各级增益的组合,从而达到54dB的动态范围和1.7dB的增益步长。最后一级模数转换器采用MASH21b-24b级联结构sigma-delta ADC。对于WLAN要求,ADC需要有10MHz的信号带宽。对于如此大的带宽要求,如果采用传统ADC,如流水线ADC,也可以实现模/数转换,但是功耗、面积都非常大。Sigma-delta模数转换器以其独特的工作机理放松了对模拟电路设计的要求,通过过采样,噪声整型及多位量化器技术降低带宽内的噪声,提高信噪比,从而提高ADC的精度。对多位DAC引入的非线性采用DWA数字校正方法。
采用Cadence Virtuoso layout Editor进行了整体电路的版图设计,并使用Diva/Dracula验证工具完成了各单元和整体链路的DRC(Design Rule Check)和LVS(Layout Versus Schematic)验证。整体电路输入信号为5.7GHz,噪声系数为9.284dB,输入阻抗匹配S11为-16dB,匹配阻抗50Ω,VGA输入控制位为默认值10011时,链路增益达到了45.95dB, IIP3为-16.7dBm,最大输入信号幅值-30dBm,达到了WLAN的性能指标要求。整个接收机(除频率合成器外)电流功耗为38mA,版图面积3mm×3mm。
WLAN(Wireless Local Area Networks) is a combinative product of computer networking and wireless communication technology. This new type network can not only realize all the functions which conditional wired networks can provide, but also access networks by wireless information channels. WLAN is a convenient and high speed network employed in mobility, individual communications and multimedia applications, and is an effective means of accessing broadband. Problems met in wired network can be easily solved in WLAN which transmits data, sounds and videos in air. Nowadays, WLAN can transmit data in the range of decade meters to several hundred meters indoor and several decade miles outdoor. In the respect of application and prospect of WLAN, the integrated radio frequency(RF) receiver used for WLAN physical levels has a great valuable prospect. How to realize a low cost but high performance RF receiver is a challenge. The system of RF receiver requires high linearity as far as possible while high sensitivity performance has been already achieved. Therefore, the harmonic distortion can be suppressed and low BER can be met. In addition, RF receiver requires large dynamic range of radio frequency input and output, which results in good adaptability and ability of anti-interference. In early times, the integrated RF receiver circuits were fabricated in GaAs technology which can work at a high frequency and has low noise. As the developing of CMOS technology, the frequency and noise characteristics of CMOS have been improved greatly nowadays and, therefore, fabricating the RF receiver circuits in CMOS technology can be realized very well. The CMOS technology has the advantages of low cost, small area and high performance, and can be easily integrated with digital baseband circuits according with the development of SOC(System on Chip).
This dissertation has deigned the integrated circuits of RF receiver for IEEE 802.11a standard and the layout based on TSMC 0.18um CMOS technology. Firstly, systematic design is introduced and mechanisms of homodyne receiver, heterodyne receiver and two-step do wn-convertor structure are analysed, then, requirements of each sub-modules are defined. There are many non-idealities in the structures mentioned above, such as noise, image frequency, nonlinearities, impedance mis-matchingwhich have been analysed in this paper. The important parameters such as noise figure(NF), image rejection ration(IRR), gain, 1dB compression(P1dB), input third-order intercept point(IIP3) are spread out. Then the architecture used for IEEE802.11a standard is decided after carefully analyzing the required characteristics. Sub-blocks including LNA, Mixer, AGC, Gm-C filter, AGC and sigma-delta ADC are therefore designed. As the first stage, passive CMOS LNA plays an important role that its noise performance, gain and linearity have a great influence to the whole chain. The second stage is mixer and its linearity, gain and noise are also key points of this paper. Gilbert unit is used as the core circuit of mixer and output signal of the locate oscillator is amplified by adding an input buffer, which makes the MOSFET work on a better switching state, then the linearity performance of mixer can be improved. Gm-C filter is used for the large bandwidth requirement. AGC, the so called Variable Gain Amplifier is used to change the gain of the chain by digital signal feedback from digital signal processing module. The main characteristics of AGC are dynamic range and gain step. Cascade differential amplifiers are used and the gain is decided by the feedback digital signal from digital base-band. The dynamic range and gain step are respectively 54dB and 1.7dB. The final stage is MASH21b-24b sigma-delta ADC. The WLAN system requires a bandwidth of 10MHz and the traditional ADC, such as pipelined ADC has a greater dissipation and occupied a larger area than sigma-delta ADC which can relax the requirements of system by its mechanism. The sigma-delta ADC reduces the noise in the interested band by noise shaping and multi-bit quantization and therefore improves the SNR and the precision of ADC. DWA is used for the non-linearity induced by multi-bit DAC。
The whole layout of the circuits is designed by using Cadence Virtuoso layout Edition. DRC(Design Rule Check) and LVS (Layout Versus Schematic) have been achieved by using Diva/Dracula. When the frequency of the input signal is 5.7GHz, the whole system has a NF of 9.284dB, S11-16dB, matched impedance 50Ω, gain of the whole link 45.95dB when input bits of VGA is 10011, IIP3-16.7dB, the maxim amplitude of input-30dBm. The simulation results meet the requirements of the WLAN. The whole receiver circuits (except for PLL) have a current dissipation of 38mA and the layout occupies an area of 3 mm×3mm.
引文
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