高性能计算机若干关键问题研究
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摘要
高速缓存一致性问题不仅关系着系统的正确性,还对系统的性能有着重要影响。多核处理器的高速缓存一致性协议设计更为复杂和验证更加困难。使用多核处理器构建大规模并行计算系统已经成为主流。在此环境下,高速缓存一致性协议需要处理的一致性事务更多,涉及到处理器芯片内多个高速缓存之间、处理器芯片内高速缓存与片外高速缓存之间、处理器芯片之间的一致性问题等。所以研究多核处理器的高速缓存一致性问题具有重要的学术意义和应用背景。首先,本文对多核处理器中的高速缓存一致性协议进行了研究,重点研究了扩放性较好、能适应多核处理器本身特点的MOESI协议及其实现,并对该协议做出了优化;其次,本文研究了在由多核处理器构建的并行计算系统环境下的高速缓存一致性协议,实验证明本文工作能够有效减少片内高速缓存失效次数(13%到30%)和提高系统性能(运行时间最多能减少30%左右);最后,本文研究了片上高速缓存的包含与非包含策略,提出了一个基于不包含策略的片上高速缓存系统设计,从而提高了片上高速缓存容量的利用率和提升了多核处理器的性能。
高性能计算机是一个国家的重要战略资源,其国产化水平是一个国家综合国力的集中体现。目前采用我国具有完全自主知识产权的龙芯多核处理器构建高性能计算机已经被一些研究单位或机构纳入日程。首先,本文特别针对科学计算领域应用,对龙芯体系结构的多核处理器的片上缓存系统的性能进行了评测,指出了龙芯多核处理器在科学计算领域中的一些性能特点。其次,依此进行了一些设计空间上的探索。实验证明,在某些情况下可以使片上二级高速缓存命中率提高50%以上,等。
高性能计算机的网络,对于机器的整体性能具有至关重要的作用。首先,本文研究了一种先进的新型网络拓朴结构:MPU,研究内容包括其数学模型、网络拓扑、路由算法等。其次,本文从理论上对MPU与当前其他先进高性能计算机网络进行了对比分析。最后,本文还介绍了为MPU所开发的一个大型并行模拟器MPUS的原理、架构、工作流程,等。实验证明,MPU的设计正确,且具有良好的可扩放性。
KD-50-Ⅰ万亿次计算机是首台基于龙芯通用高性能处理器的国产万亿次计算机。首先,本文围绕KD-50-Ⅰ的体系结构设计,研究实现了KD-50-Ⅰ的无盘启动技术、构建了KD-50-Ⅰ的高效操作系统和文件系统、优化了KD-50-Ⅰ通信库,从而提高了系统的性能和可用性,有利于KD-50-Ⅰ的推广应用。其次,本文研究了实际物理学研究中常用到的扫描电子显微成像模拟程序在KD-50-Ⅰ上的应用,并对其进行了优化。本项工作提高了应用程序运行效率,为KD-50-Ⅰ在不同领域的应用提供了示例。
The Cache Coherence Protocol is a key component towards the correctness and effciency of the computer system. It is more difficult to design and verify the cache coherence protocol for Chip Multiprocessor(CMP), as the protocol should deal with the interaction between CMPs, inter- and intra-CMPs, etc. High performance computers are important resources to our country. We have studied the cache coherence techniques for CMP. Taking into account the scalarbility and performance, our work focuses on the MOESI protocol and its implementation. We have studied the cache coherence protocol in multi-CMP (M-CMP) systems. Experiments show that our work can improve system performance up to 1. 5X, and reduce the times of on-chip cache misses (13% up to 30%). To utilize on-chip cache efficiently is key to CMP' s performance. We have studied the performance of inclusive and non-inclusive on-chip cache and proposed an on-chip cache architecture that is based on exclusive policy.
Some companies and research institution have dicided to comstruct high performance computers that based on LoongSon multi-core CPU. To comprehend the feature of LoongSon CPU under scientific applications more precisely, we profiled its performance. Based on the research, we proposed some idea to optimise its architecture. Experiments showed that our work can reduce the L2 Cache miss rate up to 50%.
The network of high performance computer is key to HPC' s performance. We have studied a new network—MPU, including its mathematic model, topology, routing algorithm, etc. We proved that MPU has better performance that some other modern networks theoretically. After that, we have studied a large scale parallel simulator for MPU—MPUS, including its architecture, working procedures, etc. Experiments thowed that the design of MPU is right, and is good at scalability.
KD-50-I is the first totally made-in-China Tera-Flops high performance computer that based on LoongSon CPU. We have studied its architecture and optimization to it. Our wrok contributes to the development and use of totally made-in-China high performance computer.
高性能计算机是一个国家的重要战略资源,其国产化水平是一个国家综合国力的集中体现。目前采用我国具有完全自主知识产权的龙芯多核处理器构建高性能计算机已经被一些研究单位或机构纳入日程。首先,本文特别针对科学计算领域应用,对龙芯体系结构的多核处理器的片上缓存系统的性能进行了评测,指出了龙芯多核处理器在科学计算领域中的一些性能特点。其次,依此进行了一些设计空间上的探索。实验证明,在某些情况下可以使片上二级高速缓存命中率提高50%以上,等。
高性能计算机的网络,对于机器的整体性能具有至关重要的作用。首先,本文研究了一种先进的新型网络拓朴结构:MPU,研究内容包括其数学模型、网络拓扑、路由算法等。其次,本文从理论上对MPU与当前其他先进高性能计算机网络进行了对比分析。最后,本文还介绍了为MPU所开发的一个大型并行模拟器MPUS的原理、架构、工作流程,等。实验证明,MPU的设计正确,且具有良好的可扩放性。
KD-50-Ⅰ万亿次计算机是首台基于龙芯通用高性能处理器的国产万亿次计算机。首先,本文围绕KD-50-Ⅰ的体系结构设计,研究实现了KD-50-Ⅰ的无盘启动技术、构建了KD-50-Ⅰ的高效操作系统和文件系统、优化了KD-50-Ⅰ通信库,从而提高了系统的性能和可用性,有利于KD-50-Ⅰ的推广应用。其次,本文研究了实际物理学研究中常用到的扫描电子显微成像模拟程序在KD-50-Ⅰ上的应用,并对其进行了优化。本项工作提高了应用程序运行效率,为KD-50-Ⅰ在不同领域的应用提供了示例。
The Cache Coherence Protocol is a key component towards the correctness and effciency of the computer system. It is more difficult to design and verify the cache coherence protocol for Chip Multiprocessor(CMP), as the protocol should deal with the interaction between CMPs, inter- and intra-CMPs, etc. High performance computers are important resources to our country. We have studied the cache coherence techniques for CMP. Taking into account the scalarbility and performance, our work focuses on the MOESI protocol and its implementation. We have studied the cache coherence protocol in multi-CMP (M-CMP) systems. Experiments show that our work can improve system performance up to 1. 5X, and reduce the times of on-chip cache misses (13% up to 30%). To utilize on-chip cache efficiently is key to CMP' s performance. We have studied the performance of inclusive and non-inclusive on-chip cache and proposed an on-chip cache architecture that is based on exclusive policy.
Some companies and research institution have dicided to comstruct high performance computers that based on LoongSon multi-core CPU. To comprehend the feature of LoongSon CPU under scientific applications more precisely, we profiled its performance. Based on the research, we proposed some idea to optimise its architecture. Experiments showed that our work can reduce the L2 Cache miss rate up to 50%.
The network of high performance computer is key to HPC' s performance. We have studied a new network—MPU, including its mathematic model, topology, routing algorithm, etc. We proved that MPU has better performance that some other modern networks theoretically. After that, we have studied a large scale parallel simulator for MPU—MPUS, including its architecture, working procedures, etc. Experiments thowed that the design of MPU is right, and is good at scalability.
KD-50-I is the first totally made-in-China Tera-Flops high performance computer that based on LoongSon CPU. We have studied its architecture and optimization to it. Our wrok contributes to the development and use of totally made-in-China high performance computer.
引文
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