片上多核处理器缓存子系统优化的研究
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摘要
当前的片上多核处理器需要大容量的缓存系统来降低快速的处理器和慢速的片下主存之间的性能差距。本文认为可以利用和挖掘片上多核处理器的特性来优化其缓存子系统的性能和功耗。本文的工作研究了几个优化片上多核处理器缓存子系统性能的机制。具体来说,本文的研究主题包含三个方面：1)研究和设计高效的多播路由算法来提升片上网络的性能；2)利用当前的新型的非易失性存储器来为片上多核处理器设计低功耗的缓存系统；3)挖掘利用线程的进度信息来设计更加高效的缓存一致性协议。
针对第一个研究主题,我们提出了一种高效的片上网络多播路由机制。对于集成越来越多核的片上多核处理器来说,片上网络为其提供了一个高效的、可扩展的通信基础架构。对于多核架构下的片上网络来说,一对多的通信模式是很普遍的。没有有效的多播路由机制的支持,传统的基于单播的片上网络在处理这些多播通信时是很低效的。本文提出了一个基于网络划分的多播路由机制,简称DPM。DPM可以高效地减低片上网络中网络包的平均传输延迟以及降低片上网络的功耗。具体来说,DPM可以根据当前网络中负载均衡级别以及多播通信的链路共享特征来动态地进行路由选择。
本文的第二个研究课题是利用一种新型的非易失性存储器(自旋转移矩随机访问存储器,STT-RAM)来为片上多核处理器设计低功耗的缓存。STT-RAM具有快速的访问速度、高存储密度以及可以忽略不计的泄露功率。然而,大规模地应用STT-RAM作为多核处理器的缓存受到STT-RAM的较长的写延迟以及较高的写功耗的约束。最近研究表明过降低STT-RAM的存储单元(磁性隧道结MTJ)的数据保持时间可以有效地提升其写性能。但是保持时间降低的STT-RAM是易失性的,需要通过周期性地刷新其存储单元来避免数据丢失。当这样的STT-RAM用于多核的最后一级缓存(LLC)时,频繁的刷新操作在加剧能量消耗的同时也会给系统的性能带来负面影响。文本提出了一种高效的刷新方案(简称CCear)可以最小化这类STT-RAM上的刷新操作。CCear主要通过与缓存一致性协议以及缓存管理算法进行交互来消除不必要的刷新操作。
最后我们提出了一个高效的一致性协议的调整机制来优化运行在片上多核处理器上的并行程序的性能。片上多核处理器的一个主要目标就是通过挖掘线程级别的并行性来继续提升应用程序的性能。但是对于运行在这类系统上的多线程程序来说,由于不均匀的任务分配以及共享资源的冲突,不同的线程通常呈现出不同的执行进度。这种进度的不均匀性是多线程程序性能的最大的瓶颈之一。由于多线程程序内在的同步机制,如内存屏障和锁,运行具有较快进度的线程的核必须停下来等待进度较慢的核。这样的空等不仅会降低系统性能,也会导致功耗的浪费。本文提出了一种线程进度感知的一致性调整机制,简称TEACA。TEACA利用线程的进度信息来动态地调整每个线程的一致性策略,目的是提升片上网络带宽资源的使用效率以及降低功耗。具体来说,TEACA动态地将线程划分为二类：领导者线程与落后者线程。随后,TEACA会根据线程来类别信息为其一致性请求提供特定的一致性策略。
Modern chip multiprocessors (CMPs) employ large cache memories to reduce the performance gap between processors and off-chip memory. This thesis states that the particular characteristics of CMP system can be exploited to improve energy and performance in the memory hierarchy. The research presented in this thesis investigates several mechanisms to optimize the performance of CMP memory system. Specifically, we target three problems as our research topic:1) design efficient multicasting algorithm to improve the performance of on-chip network,2) exploit emerging non-volatile memories to design low power cache memory for CMP systems,3) exploit thread progress information to design high performance cache coherence protocols.
For the first research topic, we propose an efficient multicast routing mech-anism for on-chip network. For CMP system with increasing core count, on-chip network provides an efficient and scalable interconnection paradigm, wherein one-to-many (multicast) communication is universal for such platforms. Without ef-ficient multicasting support, traditional unicasting on-chip networks will be low efficiency in tackling such multicast communication. In this thesis, we propose dual partitioning multicasting (DPM) which significantly reduces packet laten-cy and on-chip network power dissipation. Specifically, DPM scheme adaptively makes routing decision based on the network load-balance level as well as the link sharing patterns characterized by the distribution of the multicasting destinations.
For our second research topic, we propose to exploit emerging non-volatile memory, such as spin-torque transfer RAM (STT-RAM), to design low power cache memories. STT-RAM has fast read access, high storage density and negli-gible leakage power. However, the wide adoption of STT-RAM as cache memories is impeded by its long write latency and high write power. The write performance of STT-RAM can be improved through relaxing the retention time of its cell, magnetic tunnel junction (MTJ). The resultant volatile STT-RAM needs to be periodically refreshed to prevent data loss. When applied as the large last-level cache in CMP systems, the frequent refresh operations could dissipate significant extra energy. In addition, the refreshes could severely conflict with the normal read/write operations to degrade the overall system performance. In this thesis, we propose cache coherence enabled adaptive refresh (CCear) to minimize the number of refresh operations for volatile STT-RAM. CCear can effectively mini-mize the number of refresh operations on volatile STT-RAM through interacting with cache coherence protocols and cache management policy.
Finally, we propose an efficient coherence adaption mechanism to improve the performance of cache coherence protocol in CMP systems. One primary ob-jective of CMP system is to boost application execution by exploiting thread-level parallelism. In such systems, threads typically exhibit unbalanced progress stem-ming from unequal cache misses or task assignment. Load imbalance is one of the biggest roadblocks for parallel application performance. Because of the inherent synchronization primitives, such as barriers and locks, cores running fast thread have to waste pervious cycles waiting for slow cores. In this thesis, we propose thread progress aware coherence adaption (TEACA) which utilizes the thread progress information as the hints to adapt hybrid coherence protocols. Specifical-1y, TEACA fuses the memory system statistics to estimate the progress of threads. Based on the estimated thread progress information, TEACA dynamically catego-rizes threads into leader threads and laggard threads. The thread categorization decisions are then leveraged for efficient coherence adaption in hybrid coherence protocols.
针对第一个研究主题,我们提出了一种高效的片上网络多播路由机制。对于集成越来越多核的片上多核处理器来说,片上网络为其提供了一个高效的、可扩展的通信基础架构。对于多核架构下的片上网络来说,一对多的通信模式是很普遍的。没有有效的多播路由机制的支持,传统的基于单播的片上网络在处理这些多播通信时是很低效的。本文提出了一个基于网络划分的多播路由机制,简称DPM。DPM可以高效地减低片上网络中网络包的平均传输延迟以及降低片上网络的功耗。具体来说,DPM可以根据当前网络中负载均衡级别以及多播通信的链路共享特征来动态地进行路由选择。
本文的第二个研究课题是利用一种新型的非易失性存储器(自旋转移矩随机访问存储器,STT-RAM)来为片上多核处理器设计低功耗的缓存。STT-RAM具有快速的访问速度、高存储密度以及可以忽略不计的泄露功率。然而,大规模地应用STT-RAM作为多核处理器的缓存受到STT-RAM的较长的写延迟以及较高的写功耗的约束。最近研究表明过降低STT-RAM的存储单元(磁性隧道结MTJ)的数据保持时间可以有效地提升其写性能。但是保持时间降低的STT-RAM是易失性的,需要通过周期性地刷新其存储单元来避免数据丢失。当这样的STT-RAM用于多核的最后一级缓存(LLC)时,频繁的刷新操作在加剧能量消耗的同时也会给系统的性能带来负面影响。文本提出了一种高效的刷新方案(简称CCear)可以最小化这类STT-RAM上的刷新操作。CCear主要通过与缓存一致性协议以及缓存管理算法进行交互来消除不必要的刷新操作。
最后我们提出了一个高效的一致性协议的调整机制来优化运行在片上多核处理器上的并行程序的性能。片上多核处理器的一个主要目标就是通过挖掘线程级别的并行性来继续提升应用程序的性能。但是对于运行在这类系统上的多线程程序来说,由于不均匀的任务分配以及共享资源的冲突,不同的线程通常呈现出不同的执行进度。这种进度的不均匀性是多线程程序性能的最大的瓶颈之一。由于多线程程序内在的同步机制,如内存屏障和锁,运行具有较快进度的线程的核必须停下来等待进度较慢的核。这样的空等不仅会降低系统性能,也会导致功耗的浪费。本文提出了一种线程进度感知的一致性调整机制,简称TEACA。TEACA利用线程的进度信息来动态地调整每个线程的一致性策略,目的是提升片上网络带宽资源的使用效率以及降低功耗。具体来说,TEACA动态地将线程划分为二类：领导者线程与落后者线程。随后,TEACA会根据线程来类别信息为其一致性请求提供特定的一致性策略。
Modern chip multiprocessors (CMPs) employ large cache memories to reduce the performance gap between processors and off-chip memory. This thesis states that the particular characteristics of CMP system can be exploited to improve energy and performance in the memory hierarchy. The research presented in this thesis investigates several mechanisms to optimize the performance of CMP memory system. Specifically, we target three problems as our research topic:1) design efficient multicasting algorithm to improve the performance of on-chip network,2) exploit emerging non-volatile memories to design low power cache memory for CMP systems,3) exploit thread progress information to design high performance cache coherence protocols.
For the first research topic, we propose an efficient multicast routing mech-anism for on-chip network. For CMP system with increasing core count, on-chip network provides an efficient and scalable interconnection paradigm, wherein one-to-many (multicast) communication is universal for such platforms. Without ef-ficient multicasting support, traditional unicasting on-chip networks will be low efficiency in tackling such multicast communication. In this thesis, we propose dual partitioning multicasting (DPM) which significantly reduces packet laten-cy and on-chip network power dissipation. Specifically, DPM scheme adaptively makes routing decision based on the network load-balance level as well as the link sharing patterns characterized by the distribution of the multicasting destinations.
For our second research topic, we propose to exploit emerging non-volatile memory, such as spin-torque transfer RAM (STT-RAM), to design low power cache memories. STT-RAM has fast read access, high storage density and negli-gible leakage power. However, the wide adoption of STT-RAM as cache memories is impeded by its long write latency and high write power. The write performance of STT-RAM can be improved through relaxing the retention time of its cell, magnetic tunnel junction (MTJ). The resultant volatile STT-RAM needs to be periodically refreshed to prevent data loss. When applied as the large last-level cache in CMP systems, the frequent refresh operations could dissipate significant extra energy. In addition, the refreshes could severely conflict with the normal read/write operations to degrade the overall system performance. In this thesis, we propose cache coherence enabled adaptive refresh (CCear) to minimize the number of refresh operations for volatile STT-RAM. CCear can effectively mini-mize the number of refresh operations on volatile STT-RAM through interacting with cache coherence protocols and cache management policy.
Finally, we propose an efficient coherence adaption mechanism to improve the performance of cache coherence protocol in CMP systems. One primary ob-jective of CMP system is to boost application execution by exploiting thread-level parallelism. In such systems, threads typically exhibit unbalanced progress stem-ming from unequal cache misses or task assignment. Load imbalance is one of the biggest roadblocks for parallel application performance. Because of the inherent synchronization primitives, such as barriers and locks, cores running fast thread have to waste pervious cycles waiting for slow cores. In this thesis, we propose thread progress aware coherence adaption (TEACA) which utilizes the thread progress information as the hints to adapt hybrid coherence protocols. Specifical-1y, TEACA fuses the memory system statistics to estimate the progress of threads. Based on the estimated thread progress information, TEACA dynamically catego-rizes threads into leader threads and laggard threads. The thread categorization decisions are then leveraged for efficient coherence adaption in hybrid coherence protocols.
引文
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