基于CCSDS IDC星载图像压缩算法的FPGA实现技术
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摘要
随着航天技术的发展,不论是深空探索还是对地观测,卫星图像获取设备分辨率日益提高,获得的遥感图像数据越来越多,数据下传压力越来越大,因而星载图像压缩技术在深空、遥感领域中起着越来越重要的作用。
目前,按照去相关技术,在星载图像压缩系统中主要采用了基于预测的差分脉冲编码调制(DPCM)算法、基于离散余弦变换(DCT)的算法以及基于离散小波变换(DWT)的算法,具体采用的静止图像压缩标准有CCSDS LDC、JPEG、JPEG2000、SPIHT等标准,但它们存在计算复杂度高甚至分块效应的缺点,不太适合星载应用。因而,空间数据系统咨询委员会(CCSDS)着手建立一种新的适合于空间应用的星载图像压缩算法,并于2005年11月正式推出了IDC(Image Data Compression)图像数据压缩推荐标准。IDC采用了9/7离散小波变换,支持无损压缩和有损压缩,支持码流渐进传输。该算法计算复杂度低,支持快速、低功耗硬件实现,获得了与JPEG2000相近的性能,是专门为空间应用而设计的压缩标准,满足星载应用的要求。
为对卫星获取的海量图像数据进行实时压缩,解决数据存储和传输的压力,本文对CCSDS推出的IDC星载图像压缩算法及其硬件实现展开研究,利用先进的FPGA技术,研究并设计了IDC算法的IP软核,将该IP核集成于CoreConnect的PLB总线上,构建一个较完整的单芯片星载图像压缩系统。
论文的主要内容如下：
(1)研究了CCSDS IDC图像数据压缩标准,对算法进行了分析和仿真。经与JPEG2000压缩算法对比,IDC压缩算法的计算复杂度和硬件实现复杂度较低,非常适合星载环境图像数据压缩的应用。
(2)研究了IDC所采用的9/7离散小波变换算法,并将其转换为有利于快速计算和VLSI实现的提升格式。
提出了9/7整数离散小波变换提升格式的VLSI实现结构,简化了计算过程,便于数据的有序处理。改进设计了9/7浮点离散小波变换卷积算法的VLSI实现结构,设计了9/7浮点离散小波变换提升格式VLSI实现结构。在9/7浮点离散小波变换的卷积算法和提升格式实现结构中,采用基于CSD编码的移位加运算代替了常系数乘法,实现了无乘法计算,缩短了延时路径,提高了计算频率,节约了硬件资源。
在研究设计的二维离散小波变换的VLSI结构中,采用行、列并行变换结构,加快了变换速度,提高了小波变换效率；且行变换模块和列变换模块均采用内嵌边界延拓处理方法,减少了所需的内存容量。
(3)研究了IDC标准中位平面编码器算法,与离散小波变换的计算密集型不同,它的数据运算并不复杂,而是以大量的比较、移位和逻辑判断操作为主的处理过程,而且数据的有序流动是一个比较复杂的过程,要频繁访问存储单元。
基于并行技术提出了位平面编码器VLSI实现架构,提高了位平面数据的处理能力。该架构主要包括直流系数初始编码模块、交流系数位深编码模块和位平面编码模块。
为减少块内扫描时间,按系数集合分类的方法进行块内并行扫描,大幅减少每个块的扫描时间。为减少一个段的扫描时间,采取了块分组并行扫描的方法。为加快位平面最优编码选项计算速度,采取了块分组并行统计的方法。
(4)基于Xilinx公司Virtex-ⅡPro FPGA芯片内嵌的PowerPC处理器硬核、IBM CoreConnect,总线结构和基于单芯片设计星载压缩系统的思想,提出一种基于PowerPC+CoreConnect PLB+IDC IP软核的星载图像压缩系统SoPC架构,提供了通过片上总线集成外围IP软核的方法,降低了小卫星图像压缩有效载荷的体积、复杂度和成本,缩短了研制周期。设计了基于CoreConnect PLB,总线的IDC图像压缩IP软核,开发了符合PLB总线的IP核IPIF接口,将设计的软核集成于PLB总线上,构建了在单一芯片FPGA内将各种不同的IP核连接到一起构成一个较完整应用的星载图像压缩系统。
本文在研究设计了1DC算法IP软核的基础上,进行了功能验证和系统设计,整个系统在Xilinx公司的Virtex-ⅡPro FPGA开发系统上进行验证和实现。
With the development of the aerospace technology, more and more remote sense image data are produced and the data transmission to ground becomes more and more difficult both in deep space probes and in the near earth observations, owing to the increasing resolution of the satellite imaging instruments. Therefore, the onboard image data compression plays an important role in the fields of deep space exploration and remote sense.
At present, according to different techniques used for decorrelation, the image compression algorithms can be separated into DPCM, DCT and DWT-based in the onboard image compression systems. The main standards of still image compression include CCSDS LDC based on DPCM, JPEG based on DCT, and JPEG2000 and SPIHT based on DWT. But some of them have the disadvantages of high computational complexity, even block effect, which are not suitable for onboard satellite use. So the CCSDS starts to establish a new image data compression algorithm suitable for spaceborne applications, and the new image data compression recommendation standard called CCSDS Image Data Compression (IDC) Blue Book is finally published in November 2005. The IDC algorithm,9/7 DWT-based, supports both lossy and lossless compression and allows progressive transmission. The algorithm reduces computational complexity and the hardware implementation is fast and low power. CCSDS IDC achieves performance similar to JPEG2000. It is designed specially for space application, meeting the requirements of satellites.
In order to compress the extensive amount of satellite image data in real time and solve the problem of data storage and transmission, the CCSDS IDC algorithm and its hardware implementation is researched in this paper. With the advanced FPGA technology and the new IDC algorithm, an IP soft core of IDC algorithm is designed and integrated into the PLB bus of the CoreConnect, aiming at building a single-chip satellite image compression system.
The paper is summarized as follows:
(1) Study on CCSDS IDC image data compression recommanded standard. The algorithm is analyzed and simulated in detail. The computational complexity and hardware implementation for IDC compression algorithm is lower than that of JPEG2000's. It is very suitable for the image data compression in satellite environment.
(2) The 9/7 discrete wavelet transform algorithm is studied and it is converted into a lifting scheme, easy to calculate quickly and be implemented by VLSI.
VLSI implementation architecture of 9/7 integer DWT lifting-based is proposed, which can simplify the computational procedure. VLSI implementation architecture of 9/7 float DWT convolution algorithm is also improved, and VLSI architecture of 9/7 float DWT lifting scheme is also designed. In the wavelet transform modules of convolution algorithm and lifting scheme, replacing constant coefficient multiplication operations, the shift-adder multipliers CSD-based get no multiplier computation, shorten the delay path, increase the computing frequency and save hardware resources.
In the VLSI structure of two dimensional discrete wavelet transform, the parallel transformation of row and column structure speeds up the transformation and raises the efficiency of the wavelet transform. Row and column transformation modules use the embedded symmetric extension to reduce the required memory capacity.
(3) The IDC's bit plane encoder is researched. Different from the DWT's intensive computation, its data operation is not complicated. It is a procedure mainly including a lot of comparison, shift and logical judgement operations. As a complex process, the data flow needs frequent access to the memory.
VLSI implementation architecture of bit plane encoder based on parallel technique is proposed. The modules of initial coding of DC coefficient, AC coefficient bit depth coding and bit plane coding are designed.
The parallel scan method based on set-type is used to reduce the scan time in a block. The parallel scan method based on block-group is used to shorten the scan time of a segment. And the parallel statistical method based on block-group is taken to speed up the optimal code option calculation for a bit plane.
(4) A SoPC architecture of satellite image compression system is proposed, which is based on PowerPC processor. CoreConnect PLB bus and IDC IP soft core. The implementation of the single-chip image compression system aims to decrease the size, complexity and cost of the small satellite and shorten the development cycle. An IDC IP soft core based on CoreConnect PLB bus is designed and the IPIF interface in accordance to PLB bus is developed. An onboard image compression system composed of various IP core in a Xilinx Virtex-ⅡPro FPGA is built.
In this paper, on the basis of researching and designing the IDC's IP software core, the functional verification and system design are done. Finally, the system is verified and implemented in the Xilinx Virtex-ⅡPro FPGA development system.
目前,按照去相关技术,在星载图像压缩系统中主要采用了基于预测的差分脉冲编码调制(DPCM)算法、基于离散余弦变换(DCT)的算法以及基于离散小波变换(DWT)的算法,具体采用的静止图像压缩标准有CCSDS LDC、JPEG、JPEG2000、SPIHT等标准,但它们存在计算复杂度高甚至分块效应的缺点,不太适合星载应用。因而,空间数据系统咨询委员会(CCSDS)着手建立一种新的适合于空间应用的星载图像压缩算法,并于2005年11月正式推出了IDC(Image Data Compression)图像数据压缩推荐标准。IDC采用了9/7离散小波变换,支持无损压缩和有损压缩,支持码流渐进传输。该算法计算复杂度低,支持快速、低功耗硬件实现,获得了与JPEG2000相近的性能,是专门为空间应用而设计的压缩标准,满足星载应用的要求。
为对卫星获取的海量图像数据进行实时压缩,解决数据存储和传输的压力,本文对CCSDS推出的IDC星载图像压缩算法及其硬件实现展开研究,利用先进的FPGA技术,研究并设计了IDC算法的IP软核,将该IP核集成于CoreConnect的PLB总线上,构建一个较完整的单芯片星载图像压缩系统。
论文的主要内容如下：
(1)研究了CCSDS IDC图像数据压缩标准,对算法进行了分析和仿真。经与JPEG2000压缩算法对比,IDC压缩算法的计算复杂度和硬件实现复杂度较低,非常适合星载环境图像数据压缩的应用。
(2)研究了IDC所采用的9/7离散小波变换算法,并将其转换为有利于快速计算和VLSI实现的提升格式。
提出了9/7整数离散小波变换提升格式的VLSI实现结构,简化了计算过程,便于数据的有序处理。改进设计了9/7浮点离散小波变换卷积算法的VLSI实现结构,设计了9/7浮点离散小波变换提升格式VLSI实现结构。在9/7浮点离散小波变换的卷积算法和提升格式实现结构中,采用基于CSD编码的移位加运算代替了常系数乘法,实现了无乘法计算,缩短了延时路径,提高了计算频率,节约了硬件资源。
在研究设计的二维离散小波变换的VLSI结构中,采用行、列并行变换结构,加快了变换速度,提高了小波变换效率；且行变换模块和列变换模块均采用内嵌边界延拓处理方法,减少了所需的内存容量。
(3)研究了IDC标准中位平面编码器算法,与离散小波变换的计算密集型不同,它的数据运算并不复杂,而是以大量的比较、移位和逻辑判断操作为主的处理过程,而且数据的有序流动是一个比较复杂的过程,要频繁访问存储单元。
基于并行技术提出了位平面编码器VLSI实现架构,提高了位平面数据的处理能力。该架构主要包括直流系数初始编码模块、交流系数位深编码模块和位平面编码模块。
为减少块内扫描时间,按系数集合分类的方法进行块内并行扫描,大幅减少每个块的扫描时间。为减少一个段的扫描时间,采取了块分组并行扫描的方法。为加快位平面最优编码选项计算速度,采取了块分组并行统计的方法。
(4)基于Xilinx公司Virtex-ⅡPro FPGA芯片内嵌的PowerPC处理器硬核、IBM CoreConnect,总线结构和基于单芯片设计星载压缩系统的思想,提出一种基于PowerPC+CoreConnect PLB+IDC IP软核的星载图像压缩系统SoPC架构,提供了通过片上总线集成外围IP软核的方法,降低了小卫星图像压缩有效载荷的体积、复杂度和成本,缩短了研制周期。设计了基于CoreConnect PLB,总线的IDC图像压缩IP软核,开发了符合PLB总线的IP核IPIF接口,将设计的软核集成于PLB总线上,构建了在单一芯片FPGA内将各种不同的IP核连接到一起构成一个较完整应用的星载图像压缩系统。
本文在研究设计了1DC算法IP软核的基础上,进行了功能验证和系统设计,整个系统在Xilinx公司的Virtex-ⅡPro FPGA开发系统上进行验证和实现。
With the development of the aerospace technology, more and more remote sense image data are produced and the data transmission to ground becomes more and more difficult both in deep space probes and in the near earth observations, owing to the increasing resolution of the satellite imaging instruments. Therefore, the onboard image data compression plays an important role in the fields of deep space exploration and remote sense.
At present, according to different techniques used for decorrelation, the image compression algorithms can be separated into DPCM, DCT and DWT-based in the onboard image compression systems. The main standards of still image compression include CCSDS LDC based on DPCM, JPEG based on DCT, and JPEG2000 and SPIHT based on DWT. But some of them have the disadvantages of high computational complexity, even block effect, which are not suitable for onboard satellite use. So the CCSDS starts to establish a new image data compression algorithm suitable for spaceborne applications, and the new image data compression recommendation standard called CCSDS Image Data Compression (IDC) Blue Book is finally published in November 2005. The IDC algorithm,9/7 DWT-based, supports both lossy and lossless compression and allows progressive transmission. The algorithm reduces computational complexity and the hardware implementation is fast and low power. CCSDS IDC achieves performance similar to JPEG2000. It is designed specially for space application, meeting the requirements of satellites.
In order to compress the extensive amount of satellite image data in real time and solve the problem of data storage and transmission, the CCSDS IDC algorithm and its hardware implementation is researched in this paper. With the advanced FPGA technology and the new IDC algorithm, an IP soft core of IDC algorithm is designed and integrated into the PLB bus of the CoreConnect, aiming at building a single-chip satellite image compression system.
The paper is summarized as follows:
(1) Study on CCSDS IDC image data compression recommanded standard. The algorithm is analyzed and simulated in detail. The computational complexity and hardware implementation for IDC compression algorithm is lower than that of JPEG2000's. It is very suitable for the image data compression in satellite environment.
(2) The 9/7 discrete wavelet transform algorithm is studied and it is converted into a lifting scheme, easy to calculate quickly and be implemented by VLSI.
VLSI implementation architecture of 9/7 integer DWT lifting-based is proposed, which can simplify the computational procedure. VLSI implementation architecture of 9/7 float DWT convolution algorithm is also improved, and VLSI architecture of 9/7 float DWT lifting scheme is also designed. In the wavelet transform modules of convolution algorithm and lifting scheme, replacing constant coefficient multiplication operations, the shift-adder multipliers CSD-based get no multiplier computation, shorten the delay path, increase the computing frequency and save hardware resources.
In the VLSI structure of two dimensional discrete wavelet transform, the parallel transformation of row and column structure speeds up the transformation and raises the efficiency of the wavelet transform. Row and column transformation modules use the embedded symmetric extension to reduce the required memory capacity.
(3) The IDC's bit plane encoder is researched. Different from the DWT's intensive computation, its data operation is not complicated. It is a procedure mainly including a lot of comparison, shift and logical judgement operations. As a complex process, the data flow needs frequent access to the memory.
VLSI implementation architecture of bit plane encoder based on parallel technique is proposed. The modules of initial coding of DC coefficient, AC coefficient bit depth coding and bit plane coding are designed.
The parallel scan method based on set-type is used to reduce the scan time in a block. The parallel scan method based on block-group is used to shorten the scan time of a segment. And the parallel statistical method based on block-group is taken to speed up the optimal code option calculation for a bit plane.
(4) A SoPC architecture of satellite image compression system is proposed, which is based on PowerPC processor. CoreConnect PLB bus and IDC IP soft core. The implementation of the single-chip image compression system aims to decrease the size, complexity and cost of the small satellite and shorten the development cycle. An IDC IP soft core based on CoreConnect PLB bus is designed and the IPIF interface in accordance to PLB bus is developed. An onboard image compression system composed of various IP core in a Xilinx Virtex-ⅡPro FPGA is built.
In this paper, on the basis of researching and designing the IDC's IP software core, the functional verification and system design are done. Finally, the system is verified and implemented in the Xilinx Virtex-ⅡPro FPGA development system.
引文
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