DVB-S信道接收芯片字节处理环节的研究与实现
摘要
我们正处于一个知识经济的时代，知识和发明对国计民生的影响力居于空前重要的地位。卫星广播电视网以其频带宽、覆盖面广的优点，为信息的传播提供了非常良好的媒介。与此同时，伴随着知识经济浪潮而来的数字化革命带动了集成电路技术、信息处理技术、通信技术等等一系列现代化技术的全面发展，并在数字电视的迅速成长中得到体现。数字电视DVB-S信道接收芯片，正是各种先进技术的结晶，本文完成了DVB-S接收芯片中字节处理环节的研究和实现。
完成字节处理功能的电路包括从卷积解码输出后到传输流解复用的所有部分，由解交织、RS解码、解扰码和格式转换等模块组成。
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。由于单片系统级芯片设计在速度、功耗、成本上与多芯片系统相比占有较大的优势，因此发展SOC设计在未来的集成电路设计业中将有举足轻重的地位。而随着规模的扩大，SOC设计中，一些普通ASIC中较为次要的因素成为举足轻重的环节，甚至直接影响到设计的成败。为了让功能模块在SOC中也可以应用，需要在电路设计阶段就增加对这些“次要”因素的考虑。
本文共分八章。第一章概述了数字电视和DVB标准的特点，并介绍了ASIC和SOC设计的有关概念。
第二章对数字卫星电视接收系统的整体框架做一简单说明。
第三章介绍DVB-S信道接收芯片的系统结构以及DVB-S发送端的组成部分。
从第四章起，开始分模块说明对字节处理部分的研究和ASIC实现策略。第四章给出了数据解交织的原理和实现方法。
第五章详细讨论RS码的编解码算法，并给出用于ASIC实现的ME解码算法。
第六章讨论了伪随机序列和数据扰码的特点，并给出了其ASIC实现方案。
第七章实现了调整数据速率的功能，讨论了多时钟设计的问题，并给出面向DVB-S数据速率调整应用的多时钟解决方案。
第八章研究了SOC设计的特点和方法，并讨论了面向SOC设计而实现DVB-S信道接收芯片字节处理部分的策略。
本文比较了实现RS解码的几种算法，并在ME算法基础上进行改进，创造性的去掉了缩短码解码中的校正环节，纠正了有关论文中的不当论述，并将RS解码模块进行了参数化设计，同时也将RS解码的规模缩小了20％；克服了多时钟设计中的信号完整性难题，在没有增加模块面积的条件下，大幅降低数据的相位
摘要
抖动，首次引入锁相环来调整速率。最后结合SOC设计的趋势，分析了面向SOC
设计的IP复用方案，为今后提高性能、降低成本指明方向。
We are in an era economy is based on the knowledge that impacts people's livelihood with unprecedented importance. Broadcasting network by satellite, with its wide frequency band and vast overlay, acts as an excellent medium for the widespread of information. Concurrently, accompanied by this economic torrent with knowledge, a digital revolution breaks out, leading to the full development of a series of modern technologies like IC technology, Information-Processing technology, Communication technology, etc., and emphasizes itself in the process of digital TV's rapid progress. The IC chip for digit TV receiver through DVB-S channel, is precisely the combination of these advanced technologies. The main work of the paper implements the byte processing part in this chip.
The circuit to fulfill the byte processing function includes all parts between the modules on convolutional decoding and transfer stream de-multiplexing, consisting of the modules on data de- interleaving, RS decoding, data de-scrambling and format transforming.
The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design. Since the SOC design excels multi-chip in speed, power consuming and cost, it is of extreme importance to develop SOC design in future IC industry. Moreover, as the scale expands, some minor factors in traditional ASIC design become crucial in SOC design, even decide its success. In order to use those functional modules in SOC also, it is necessary to take these 'minor' factors into account.
The paper consists of eight chapters. The first chapter summarizes the characteristics of digital TV and DVB specifications, and introduces the relating concepts of ASIC and SOC design.
Chapter two gives a simple explanation on the framework of digital TV receiver system.
Chapter three sketches the structure of the chip as DVB-S channel receiver, and introduces the main parts of DVB-S channel sender.
From the fourth chapter on, the paper explains the study and implementation on the byte processing part module by module. The fourth chapter shows the principle and
the ASIC implementation of data de-interleaving.
Chapter five thoroughly discusses the algorithms on encoding and decoding RS code, and implements the ME algorithm with ASIC.
Chapter six studies characteristics and implementations of pseudo-random sequence generator and data scrambling, and fulfills the de-scrambling function with ASIC.
Chapter seven puts forward the scheme to adjust data rate, discusses the design in multi-clock circumstances, and implements the multi-clock application on adjusting data rate for DVB-S.
The last chapter studies the characteristics and methods of SOC design, and advances the scheme of byte processing part in DVB-S channel receiver for SOC design.
The paper compares some algorithms on RS decoding, makes improvements based on the ME algorithm, removes the modifying step in decoding truncate RS code, corrects unsuitable statements in the related papers, and parameterizes the RS decoding module, reducing its area by 20%. The paper overcomes the signal integration problem in multi-clock design, greatly lowers the phase jitter without area increase, introduces PLL to adjust rate for the first time, and parameterizes the module. Finally, relating to the trend of SOC design, the paper analyzes the IP reuse method, pointing the direction to improve the performance and reduce the cost.
完成字节处理功能的电路包括从卷积解码输出后到传输流解复用的所有部分，由解交织、RS解码、解扰码和格式转换等模块组成。
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。由于单片系统级芯片设计在速度、功耗、成本上与多芯片系统相比占有较大的优势，因此发展SOC设计在未来的集成电路设计业中将有举足轻重的地位。而随着规模的扩大，SOC设计中，一些普通ASIC中较为次要的因素成为举足轻重的环节，甚至直接影响到设计的成败。为了让功能模块在SOC中也可以应用，需要在电路设计阶段就增加对这些“次要”因素的考虑。
本文共分八章。第一章概述了数字电视和DVB标准的特点，并介绍了ASIC和SOC设计的有关概念。
第二章对数字卫星电视接收系统的整体框架做一简单说明。
第三章介绍DVB-S信道接收芯片的系统结构以及DVB-S发送端的组成部分。
从第四章起，开始分模块说明对字节处理部分的研究和ASIC实现策略。第四章给出了数据解交织的原理和实现方法。
第五章详细讨论RS码的编解码算法，并给出用于ASIC实现的ME解码算法。
第六章讨论了伪随机序列和数据扰码的特点，并给出了其ASIC实现方案。
第七章实现了调整数据速率的功能，讨论了多时钟设计的问题，并给出面向DVB-S数据速率调整应用的多时钟解决方案。
第八章研究了SOC设计的特点和方法，并讨论了面向SOC设计而实现DVB-S信道接收芯片字节处理部分的策略。
本文比较了实现RS解码的几种算法，并在ME算法基础上进行改进，创造性的去掉了缩短码解码中的校正环节，纠正了有关论文中的不当论述，并将RS解码模块进行了参数化设计，同时也将RS解码的规模缩小了20％；克服了多时钟设计中的信号完整性难题，在没有增加模块面积的条件下，大幅降低数据的相位
摘要
抖动，首次引入锁相环来调整速率。最后结合SOC设计的趋势，分析了面向SOC
设计的IP复用方案，为今后提高性能、降低成本指明方向。
We are in an era economy is based on the knowledge that impacts people's livelihood with unprecedented importance. Broadcasting network by satellite, with its wide frequency band and vast overlay, acts as an excellent medium for the widespread of information. Concurrently, accompanied by this economic torrent with knowledge, a digital revolution breaks out, leading to the full development of a series of modern technologies like IC technology, Information-Processing technology, Communication technology, etc., and emphasizes itself in the process of digital TV's rapid progress. The IC chip for digit TV receiver through DVB-S channel, is precisely the combination of these advanced technologies. The main work of the paper implements the byte processing part in this chip.
The circuit to fulfill the byte processing function includes all parts between the modules on convolutional decoding and transfer stream de-multiplexing, consisting of the modules on data de- interleaving, RS decoding, data de-scrambling and format transforming.
The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design. Since the SOC design excels multi-chip in speed, power consuming and cost, it is of extreme importance to develop SOC design in future IC industry. Moreover, as the scale expands, some minor factors in traditional ASIC design become crucial in SOC design, even decide its success. In order to use those functional modules in SOC also, it is necessary to take these 'minor' factors into account.
The paper consists of eight chapters. The first chapter summarizes the characteristics of digital TV and DVB specifications, and introduces the relating concepts of ASIC and SOC design.
Chapter two gives a simple explanation on the framework of digital TV receiver system.
Chapter three sketches the structure of the chip as DVB-S channel receiver, and introduces the main parts of DVB-S channel sender.
From the fourth chapter on, the paper explains the study and implementation on the byte processing part module by module. The fourth chapter shows the principle and
the ASIC implementation of data de-interleaving.
Chapter five thoroughly discusses the algorithms on encoding and decoding RS code, and implements the ME algorithm with ASIC.
Chapter six studies characteristics and implementations of pseudo-random sequence generator and data scrambling, and fulfills the de-scrambling function with ASIC.
Chapter seven puts forward the scheme to adjust data rate, discusses the design in multi-clock circumstances, and implements the multi-clock application on adjusting data rate for DVB-S.
The last chapter studies the characteristics and methods of SOC design, and advances the scheme of byte processing part in DVB-S channel receiver for SOC design.
The paper compares some algorithms on RS decoding, makes improvements based on the ME algorithm, removes the modifying step in decoding truncate RS code, corrects unsuitable statements in the related papers, and parameterizes the RS decoding module, reducing its area by 20%. The paper overcomes the signal integration problem in multi-clock design, greatly lowers the phase jitter without area increase, introduces PLL to adjust rate for the first time, and parameterizes the module. Finally, relating to the trend of SOC design, the paper analyzes the IP reuse method, pointing the direction to improve the performance and reduce the cost.
引文
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