超高频射频识别阅读器关键模块与单芯片收发机设计
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摘要
随着超高频射频识别技术的广泛应用，单芯片阅读器已经成为超高频射频识别技术研究的关键和热点。本文根据超高频射频识别技术相关协议规范和要求，以阅读器关键模块和阅读器单芯片收发机为研究对象完成了以下工作：
分析了超高频射频识别系统的基本理论，研究了阅读器和标签之间的能量传输原理。总结了不同射频收发机结构的优缺点。通过分析ISO/IEC18000-6C空中接口协议，确定了阅读器收发机的各个模块和收发机整体的性能参数。
提出一种省略了低噪声放大器以获得较高的接收机线性度的阅读器收发机结构。根据协议中发射频谱掩膜版的要求设计了阅读器的发射机通路。在发射机的设计中，使用占用芯片面积较小的有源三阶切比雪夫低通滤波器，作为对基带信号滤波整形的脉冲整形滤波器。在功率放大器的设计中，采用两级线性AB类结构的同时，在功放输出级使用线性化提升技术，保证了功率放大器的线性度。
设计了一种使用3.5/4预分频器的ΔΣ Fractional-N频率综合器。频率综合器使用正交压控振荡器，不需要使用在版图绘制时需要精心设计的多相滤波器就可以输出四路高精度匹配的正交信号。提出的3.5/4预分频器可以把ΔΣ调制器的量化阶梯降低到整数分频的一半，从而降低频率综合器的带外相位噪声。
在接收机通路中设计了一种有源正交下变频混频器，对正交下变频混频器使用电流注入技术有效的降低了跨导管的闪烁噪声，降低了噪声系数。设计了两种不同环路的自动增益控制电路：一种使用传统的峰值检波器检测输出峰值作为反馈环路的控制信号；在另外一种自动增益控制电路的设计中，把输出信号和参考电压进行比较产生占空比和输出信号幅值变化的方波信号，方波信号控制电荷泵对电容充放电输出环路增益控制信号。
在收发机版图设计中提出了两种有效隔离技术，使用CMOS工艺实现了单芯片阅读器收发机的设计。分别对接收机和发射机通路进行了测试，总结单芯片阅读器收发机的性能参数。
With the wide application of radio frequency identification (UHF RFID)technology, single-chip reader has become a key and hot spots in the study of UHFRFID technology. According to the UHF RFID-related protocol specifications andrequirements, taking key modules and single-chip transceiver as the study target, thefollowing work has been complete:
The basic theory of UHF RFID system is analyzed and makes a study on thetheory of energy transfer between the reader and tag. The advantage anddisadvantage of different structures of the RF transceiver is summarized. The readertransceiver modules and overall performance is determined by analyzing theISO/IEC18000-6C air interface protocol.
A missing low noise amplifier with high linearity reader transceiver structure isproposed. The transmitter path is designed according to the emission spectrum maskrequirements in the protocol. For the transmitter design using a third-orderChebyshev low-pass active filter as a baseband signal pulse shaping filter for itoccupies a small chip area. In the design of power amplifier, use a two-level linearstructure AB class amplifier and the output stage uses linear upgrade technologicalat the same time which guarantee the linearity of power amplifier.
A3.5/4prescaler is used in the design of the ΔΣ Fractional-N frequencysynthesizer. A quadrature voltage controlled oscillator is applied in the frequencysynthesizer, for it can output four channels of high-precision-matching of orthogonalsignals without design a layout matching multiphase filter. A3.5/4prescaler canmake theΔΣ modulator quantitative step down to half compare to integerfrequency divider, reducing the frequency synthesizer band phase noise.
A quadrature downconversion mixer is designed in the receiver path; currentinjection technology is used in the downconversion mixer design to reduce theflicker noise effectively and so reduce the noise figure. Two different automatic gaincontrol circuit loops were designed: In the first automatic gain control circuit atraditional peak detector is used to detect the output amplitude as a control signal forthe feedback loop. In the design of another automatic gain control circuit, comparingthe output signal with a reference signal to generate a square wave signal which dutycycle changes with the amplitude of the output signal. A charge-pump controlled bythe above square wave to charge and discharge a capacitor for generating the control signal of the automatic gain control ciecuit loop.
In the layout design of the transceiver tow effective isolation technology ispresented and a single-chip reader transceiver is realized by CMOS process. Thereceiver and transmitter path has been tested individually and the performance ofsingle-chip reader transceiver is summarized at last.
分析了超高频射频识别系统的基本理论，研究了阅读器和标签之间的能量传输原理。总结了不同射频收发机结构的优缺点。通过分析ISO/IEC18000-6C空中接口协议，确定了阅读器收发机的各个模块和收发机整体的性能参数。
提出一种省略了低噪声放大器以获得较高的接收机线性度的阅读器收发机结构。根据协议中发射频谱掩膜版的要求设计了阅读器的发射机通路。在发射机的设计中，使用占用芯片面积较小的有源三阶切比雪夫低通滤波器，作为对基带信号滤波整形的脉冲整形滤波器。在功率放大器的设计中，采用两级线性AB类结构的同时，在功放输出级使用线性化提升技术，保证了功率放大器的线性度。
设计了一种使用3.5/4预分频器的ΔΣ Fractional-N频率综合器。频率综合器使用正交压控振荡器，不需要使用在版图绘制时需要精心设计的多相滤波器就可以输出四路高精度匹配的正交信号。提出的3.5/4预分频器可以把ΔΣ调制器的量化阶梯降低到整数分频的一半，从而降低频率综合器的带外相位噪声。
在接收机通路中设计了一种有源正交下变频混频器，对正交下变频混频器使用电流注入技术有效的降低了跨导管的闪烁噪声，降低了噪声系数。设计了两种不同环路的自动增益控制电路：一种使用传统的峰值检波器检测输出峰值作为反馈环路的控制信号；在另外一种自动增益控制电路的设计中，把输出信号和参考电压进行比较产生占空比和输出信号幅值变化的方波信号，方波信号控制电荷泵对电容充放电输出环路增益控制信号。
在收发机版图设计中提出了两种有效隔离技术，使用CMOS工艺实现了单芯片阅读器收发机的设计。分别对接收机和发射机通路进行了测试，总结单芯片阅读器收发机的性能参数。
With the wide application of radio frequency identification (UHF RFID)technology, single-chip reader has become a key and hot spots in the study of UHFRFID technology. According to the UHF RFID-related protocol specifications andrequirements, taking key modules and single-chip transceiver as the study target, thefollowing work has been complete:
The basic theory of UHF RFID system is analyzed and makes a study on thetheory of energy transfer between the reader and tag. The advantage anddisadvantage of different structures of the RF transceiver is summarized. The readertransceiver modules and overall performance is determined by analyzing theISO/IEC18000-6C air interface protocol.
A missing low noise amplifier with high linearity reader transceiver structure isproposed. The transmitter path is designed according to the emission spectrum maskrequirements in the protocol. For the transmitter design using a third-orderChebyshev low-pass active filter as a baseband signal pulse shaping filter for itoccupies a small chip area. In the design of power amplifier, use a two-level linearstructure AB class amplifier and the output stage uses linear upgrade technologicalat the same time which guarantee the linearity of power amplifier.
A3.5/4prescaler is used in the design of the ΔΣ Fractional-N frequencysynthesizer. A quadrature voltage controlled oscillator is applied in the frequencysynthesizer, for it can output four channels of high-precision-matching of orthogonalsignals without design a layout matching multiphase filter. A3.5/4prescaler canmake theΔΣ modulator quantitative step down to half compare to integerfrequency divider, reducing the frequency synthesizer band phase noise.
A quadrature downconversion mixer is designed in the receiver path; currentinjection technology is used in the downconversion mixer design to reduce theflicker noise effectively and so reduce the noise figure. Two different automatic gaincontrol circuit loops were designed: In the first automatic gain control circuit atraditional peak detector is used to detect the output amplitude as a control signal forthe feedback loop. In the design of another automatic gain control circuit, comparingthe output signal with a reference signal to generate a square wave signal which dutycycle changes with the amplitude of the output signal. A charge-pump controlled bythe above square wave to charge and discharge a capacitor for generating the control signal of the automatic gain control ciecuit loop.
In the layout design of the transceiver tow effective isolation technology ispresented and a single-chip reader transceiver is realized by CMOS process. Thereceiver and transmitter path has been tested individually and the performance ofsingle-chip reader transceiver is summarized at last.
引文
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