电荷俘获型存储器阻挡层的研究
|
摘要
闪存是当前非易失性半导体存储器市场上的主流存储器件。随着闪存进入20纳米工艺节点,基于传统浮栅结构的闪存技术正面临严重的技术挑战,如浮栅耦合、电荷泄漏、相邻单元之间的串扰问题等。因而,提出了能够解决以上问题的电荷分立俘获型存储器。这种电荷俘获存储器件的基本结构是由隧穿层、存储层和阻挡层等功能层构成。本论文主要针对当前电荷俘获存储器可持续性缩小过程中的低压和高可靠性的需求,对阻挡层的材料、结构、后处理方式进行了优化,以及提出了光照的方法更准确的测试电容结构中少子参与的速度特性。
本论文首先介绍了如何优化阻挡层材料。由于采用传统的SiO2做阻挡层材料,不能满足器件持续按比例缩小的要求,因而,提出了引入高k阻挡层。首先阐明了引入高k材料做阻挡层的原因。这就是阻挡层采用高k材料,能使电场更多的叠加在遂穿层上,从而增大器件的编程擦写速度。同时,高k阻挡层和大功函数的金属电极一起能够有效的抑制擦除饱和现象。接着,介绍了各种高k阻挡层及其相应的存储器件的性能。接着介绍了如何优化阻挡层结构。一种是采用堆叠的高k阻挡层。这样可以兼具多种高k材料的优点。另一种是在阻挡层和俘获层之间插入siO2层。由于SiO2带隙宽,那么器件可以在不损失速度的前提下,极大的改善器件的保持特性。然后提出了对阻挡层中常用的Al2O3材料进行后处理优化。我们实验中发现英高温退火能有效降低Al2O3材料的缺陷密度,从而,改善电荷俘获型存储器件的性能。同研究发现退火气氛对MANOS器件也有明显的影响。最后,研究中发现在电容结构中少子参与的速度特性测试中引入光照。并基于弛豫时间模型,提取了光照和非光照下的时间常数,光照可以有效的减小时问常数。并且,光照能够增大器件的编擦速度,使器件的速度和晶体管的速度相一致。
Currently, flash are the dominant memory devices in the non-volatile semiconductor memory market. As the flash involves in the20nm nodes, the flash technology based on the conventional floating gate faces the big challenge. There are issues such as the floating gate coupling, charge leakage, the disturbing between the adjacent cells and so on. Thus, the discrete charge trapping memory is proposed to replace the floating gate memory. The charge trapping memory is composed of the tunneling layer, the charge trapping layer and the blocking layer. In order to meet the requirements of low operation voltage and high reliability, the optimization of the blocking layer is investigated in terms of materials, structure and post processing. Also, illumination is introduced in the speed measurement that minority carriers take part in the capacitor structure.
This paper first introduces how to optimize the blocking layer in terms of materials. Since the conventional SiO2material as the blocking layer cannot meet the scaling down requirement, the high k material is introduced. Firstly, why to introduce the high k materials in the blocking layer is introduced. The reason is that the use of high k material in the blocking layer leads to more electric field is applied to the tunneling layer, which results in faster program/erase speed. Meanwhile, the high k blocking layer along with the high work function metal electrode can effectively suppress the erase saturation. Then blocking layers with various high k materials are introduced. Second, how to optimize the blocking layer in terms of structure is introduced. One method is to use the stacked high k blocking layer, which could combines advantages of different high k materials. Another is to insert SiO2between the charge trapping layer and the blocking layer. Since the band gap of SiO2is large, the retention of the memory device can be greatly improved without degrading the speed. Third, how to optimize the Al2O3material in term of post processing technology is introduced. Our experimental results show that the high temperature post deposition annealing can reduce the trap density in Al2O3material, which can greatly improve the performance of the MANOS device. Meanwhile, it is also found that the annealing atmosphere has an obvious effect on the MANOS device. Finally, the illumination is introduced in the speed measurement under the condition that minority carriers take part in the program or erase. Based on a relaxation time model, the time constant in the dark and illumination is extracted. Illumination can reduce the time constant. And illumination increases the program or ease speed in the capacitor structure. It is found that the speed in the capacitor under illumination is comparable with that measured in the transistor structure.
本论文首先介绍了如何优化阻挡层材料。由于采用传统的SiO2做阻挡层材料,不能满足器件持续按比例缩小的要求,因而,提出了引入高k阻挡层。首先阐明了引入高k材料做阻挡层的原因。这就是阻挡层采用高k材料,能使电场更多的叠加在遂穿层上,从而增大器件的编程擦写速度。同时,高k阻挡层和大功函数的金属电极一起能够有效的抑制擦除饱和现象。接着,介绍了各种高k阻挡层及其相应的存储器件的性能。接着介绍了如何优化阻挡层结构。一种是采用堆叠的高k阻挡层。这样可以兼具多种高k材料的优点。另一种是在阻挡层和俘获层之间插入siO2层。由于SiO2带隙宽,那么器件可以在不损失速度的前提下,极大的改善器件的保持特性。然后提出了对阻挡层中常用的Al2O3材料进行后处理优化。我们实验中发现英高温退火能有效降低Al2O3材料的缺陷密度,从而,改善电荷俘获型存储器件的性能。同研究发现退火气氛对MANOS器件也有明显的影响。最后,研究中发现在电容结构中少子参与的速度特性测试中引入光照。并基于弛豫时间模型,提取了光照和非光照下的时间常数,光照可以有效的减小时问常数。并且,光照能够增大器件的编擦速度,使器件的速度和晶体管的速度相一致。
Currently, flash are the dominant memory devices in the non-volatile semiconductor memory market. As the flash involves in the20nm nodes, the flash technology based on the conventional floating gate faces the big challenge. There are issues such as the floating gate coupling, charge leakage, the disturbing between the adjacent cells and so on. Thus, the discrete charge trapping memory is proposed to replace the floating gate memory. The charge trapping memory is composed of the tunneling layer, the charge trapping layer and the blocking layer. In order to meet the requirements of low operation voltage and high reliability, the optimization of the blocking layer is investigated in terms of materials, structure and post processing. Also, illumination is introduced in the speed measurement that minority carriers take part in the capacitor structure.
This paper first introduces how to optimize the blocking layer in terms of materials. Since the conventional SiO2material as the blocking layer cannot meet the scaling down requirement, the high k material is introduced. Firstly, why to introduce the high k materials in the blocking layer is introduced. The reason is that the use of high k material in the blocking layer leads to more electric field is applied to the tunneling layer, which results in faster program/erase speed. Meanwhile, the high k blocking layer along with the high work function metal electrode can effectively suppress the erase saturation. Then blocking layers with various high k materials are introduced. Second, how to optimize the blocking layer in terms of structure is introduced. One method is to use the stacked high k blocking layer, which could combines advantages of different high k materials. Another is to insert SiO2between the charge trapping layer and the blocking layer. Since the band gap of SiO2is large, the retention of the memory device can be greatly improved without degrading the speed. Third, how to optimize the Al2O3material in term of post processing technology is introduced. Our experimental results show that the high temperature post deposition annealing can reduce the trap density in Al2O3material, which can greatly improve the performance of the MANOS device. Meanwhile, it is also found that the annealing atmosphere has an obvious effect on the MANOS device. Finally, the illumination is introduced in the speed measurement under the condition that minority carriers take part in the program or erase. Based on a relaxation time model, the time constant in the dark and illumination is extracted. Illumination can reduce the time constant. And illumination increases the program or ease speed in the capacitor structure. It is found that the speed in the capacitor under illumination is comparable with that measured in the transistor structure.
引文
[I]D. Kahng and S. M. Sze, A floating gate and its application to memory devices [J]. Bell Systems Technical Journal,1967,46:1288
[2]F. Masuoka, M. Asano, H. Iwahashi, T. Komuro and S. Tanaka, A new flash E2PROM cell using triple polysilicon technology [C]. IEDM Tech. Dig.,1984: 464-467
[3]International Technology Roadmap for Semiconductors, http://www.itrs.net/,2010
[4]K. Kim, Technology for sub-50nm DRAM and NAND flash manufacturing [C]. IEDM Tech. Dig.,2005:323-326
[5]C. Y. Lu, K. Y. Hsieh and R. Liu, Future challenges of flash memory technologies [J]. Microelectron. Eng.,2009,86:283-286
[6]A. Sikora, F. P. Pesl, W. Unger, et al., Technologies and reliability of modern embedded flash cells [J]. Microelectron. Reliab.,2006,46:1980-2005
[7]K. Kim and G. Jeong, Memory technologies for sub-40nm node [C]. IEDM Tech. Dig.,2009:27-30
[8]G. Molas, M. Bocquet, E. Vianello, et al., Reliability of charge trapping memories with high-k control dielectrics [J]. Microelectron. Eng.,2009,86:1796-1803
[9]L. Larcher and A. Padovani, A high-k related reliability issues in advanced non-volatile memories [J]. Microelectron. Reliab.,2010,50:1251-1258
[10]B. Govoreanu, P. Blomme, J. Van Houdt, et al., Enhanced tunneling current effect for nonvolatile memory applications [J]. Jpn. J. Appl. Phys.,2003, 42:2020-2024
[11]J. D. Casperson, L. D. Bell and H. A. Atwater, Materials issues for layered tunnel barrier structures [J]. J. Appl. Phys.,2008,92:261-267
[12]M. H. White, D. A. Adams and J. Bu, On the go with SONOS [J]. IEEE Circuits and Devices,2000,16:22-31.
[13]B. Eitan, P. Pavan, I. Bloom, et al., NROM:a novel localized trapping 2-bit nonvolatile memory cell [J]. IEEE Electron Device Lett.,2000,21:543-545.
[14]C. H. Lee, K. I. Choi, M. K. Cho, et al., A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories [C]. IEDM Tech. Dig.,2003:613-616
[1]Mori S, et al. ONO inter-poly dielectric scaling for nonvolatile memory Applications [J]. IEEE Trans Electron Dev,1991,38(2):386-391
[2]Mori S, et al. Thickness scaling limitation factors for ONO interpoly dielectric for nonvolatile memory devices [J]. IEEE Trans Electron Dev,1996,43(1):47-53
[3]Jiankang Bu, Marvin H. White. Design considerations in scaled SONOS nonvolatile memory devices [J]. Solid State Electron,2001,45:113-120
[4]Yang Yang, Marvin H. White. Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures [J]. Solid State Electronic,2000,44: 949-958
[5]Marvin H.White. On the go with SONOS [J]. IEEE Circuits and Devices,2000, 16(4):22-31
[6]Chang-Hyun Lee, et al. Charge-trapping device structure of SiO2/SiN/high-k dielectric A12O3 for high-density flash memory [J]. Appl Phys Lett,2005,86:152908
[7]G. Molas, et al. Reliability of charge trapping memories with high-k control dielectrics [J]. Microelectron Eng,2009,86:1796-1803
[8]M. Bocquet, G. Molas, et al. [C]. Proceedings of ESSDERC,2008, pp.110-122.
[9]Chang Yong Kang. Barrier engineering in metal-aluminum oxide nitride-oxide-silicon (MANOS) flash memory [J]. Curr Appl Phys,2010,10:e27-e31
[10]Chang Hyun Lee, Kyung Choi, et al. A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit Hash memeries [C]. IEDM Tech. Dig,2003,613-616
[11]Wei Chen, Wen-Jun Liu, et al. Multistacked Al2O3/HfO2/SiO2 tunnel layer for high-density nonvolatile memory application [J]. Appl Phys Lett,2007,91:022908
[12]Sheng-Chih Lai, Hang-Ting Lue et al. Study of the Erase Mechanism of MANOS (Metal/Al2O3/SiN/SiO2/Si) Device [J]. IEEE Electron Dev Lett,2007,28(7): 643-645
[13]SMaikap, H Y Lee, et al. Charge trapping characteristics of atomic-layer-deposited HfO2 films with AI2O3 as a blocking oxide for high-density non-volatile memory device applications [J]. Semicond. Sci. Technol.,2007,22: 884-889
[14]Almudena H M, Rob V S, Michiel V D, et.al. Reliability comparison of Al2O3 and HfSiON for use as interpoly dielectric in flash arrays. [C]. Proceedings of 36th European solid-state research conference,2006,234-237.
[15]B. Govoreanu, R. Degraeve, et al. Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate Flash memory [J]. Microelectron Eng,2009,86:1807-1811
[16]He W, Pu J, Chan D, et.al. Performance improvement in charge-trap flash memory using Lanthanum-based high-κ blocking oxide [J]. IEEE Trans Electron Dev,2009,56:2746-2751
[17]Chih-Hao C, Joseph Y-M L. Metal-high-k-high-k-oxide-semiconductor capacitors and field effect transistors using Al/La2O3/Ta2O5/SiO2/Si structure for nonvolatile memory applications [J]. Appl Phys Lett,2007,91:192903
[18]Jing P, Daniel S H C, Sun-Jung K, et.al. Aluminum-Doped Gadolinium Oxides as bl。Cking layer for improved charge retention in Charge-Trap-Type nonvolatile memory devices [J]. IEEE Trans Electr Dev,2009,56(11):2739-2745
[19]Wang X, Liu J, Bai W, et.al. A novel MONOS-type nonvolatile memory using high-k dielectrics for improved data retention and programming speed [J]. IEEE Trans Electr Dev,2004,51(5):597-602
[20]Sheng-Chih L, Hang-Ting L, Ming-Jui Y, et.al. MA BE-SONOS:a bandgap engineered SONOS using metal gate and Al2O3 blocking layer to overcome erase saturation [C]. IEEE Non-Volatile Semiconductor Memory Workshop,2007,88-89
[21]Ping-Hung T, Kuei-Shu Chang-Liao, Dong-Wei Y, et.al. Crucial integration of high work-function metal gate and high-k blocking oxide on charge-trapping type flash memory device [J]. Appl Phys Lett,2008,93:252902
[22]Chi-Pei L, Cheng-Kei L, Bing-Yue T, et al. Nanoscale multigate TiN metal nanocrystal memory using high-k blocking dielectric and high-work-function gate electrode integrated on Silcon-on-Insulator substrate [J]. Japanese Journal of Applied Physics,2009,48:04C059
[23]J. Robertson. Band offsets of wide-band-gap oxides and implications for future electronic devices [J]. Journal of Vacuum Science Technology-Part B,2000,18: 1785-1791
[24]G Molas, M. Bocquet, et al. Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories [J]. Microelectron Eng,2008,85: 2393-2399
[25]W. He, D. S. H. Chan, et al. Process and material properties of LaHfOx prepared by atomic layer deposition [J]. J. Electrochem. Soc.,2008,155(10):189-193
[26]E. A. Kraut, R. W. Grant, et al. Precise determination of the valence-band edge in X-ray photoemission spectra:Application to measurement of semiconductor interface potentials [J]. Phys.Rev. Lett.,1980,44(24):1620-1623
[1]Sangmoo Choi, et al. Improved metal-oxide-nitride-oxide-silicon-type flash device with high-k dielectrics for blocking layer [J]. J. Appl. Phys.,2003,94(8): 5408-5410
[2]M Bocquet, et al. Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories [J]. Solid State Electron,2009,53:786-791
[3]Arnaud F et.al. Physical understanding and modeling of SANOS retention in programmed state [J]. Solid State Electronics,2008,52:577-583
[4]L Larcher, A Padovani, et al. Investigation of trapping/detrapping mechanisms in Al2O3 electron/hole traps and their influence on TANOS memory operations [C]. VLSI Technology Systems and Applications (VLSI-TSA),2010,52-53
[5]Lai S C, et al. A Study of barrier engineered Al2O3 and HfO2 High-κ Charge Trapping Devices (BE-MAONOS and BE-MHONOS) with optimal High-κ thickness [C]. IEEE international memory workshop,2010
[1]Gan Wang, Marvin H. White. Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices [J]. Solid-State Electronics,2008,52: 1491-1497
[2]Chang Yong Kang. Barrier engineering in metal-aluminum oxide-nitride-pxide-silicon (MANOS) flash memory [J]. Current Applied Physics, 2010,10:e27-e31
[3]Dirk Wellekens, Pieter Blomme, Bogdan Govoreanu, et al. Al2O3 based flash interpoly dielectrics:a comparative retention study [C]. Proceedings of the European Solid-State Device Research Conference,2006. p.238-241
[4]M. Florian Beug, et al. Analysis of TANOS memory cells with sealing oxide containing blocking dielectric [J]. IEEE Transactions on Electron Devices,2010, 57(7):1590-1596
[5]Salvatore M. Amoroso et al. Reliability Constraints for TANOS Memories due to Alumina Trapping and Leakage [C]. IEEE Reliability Physics Symposium IRPS, 2010,966-969
[6]L Larcher, A Padovani, et al. Investigation of trapping/detrapping mechanisms in AI2O3 electron/hole traps and their influence on TANOS memory operations [C]. VLSI Technology Systems and Applications (VLSI-TSA),2010,52-53
[7]Dirk Wellekens, Joeri De Vos, et al. Optimization of Al2O3 interpoly dielectric for embedded flash memory applications [C]. Proceedings of Joint Non Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design,2008,12-15
[8]V. V. Afanas'ev, et al. Impact of annealing-induced compaction on electronic properties of atomic-layer-deposited Al2O3 [J]. Applied Physics Letter,2002,81(9): 1678-1680
[9]M. Lisiansky, et al. SiO2/Si3N4/Al2O3 stacks for scaled-down memory devices: effects of interfaces and thermal annealing [J]. Applied Physics Letter,2006,89: 153506
[10]Mario Lanza, Marc Porti, et al. Conductivity and Charge Trapping After Electrical Stress in Amorphous and Polycrystalline Al2O3-Based Devices Studied With AFM-Related Techniques [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY,2011,10(2):344-351
[11]W.Weinreich, L.Wilde, P. Kucher, et al. Correlation of microscopic and macroscopic electrical characteristics of high-k ZrSixO2 thin films using tunneling atomic force microscopy [J]. J. Vac. Sci. Technol. B,2009,27(1):364-368,.
[12]Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, et al. Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode [C]. IEEE IEDM,2001, pp. 20.2-1-20.2-4
[13]X. Yu, et al. Effect of gate dopant diffusion on leakage current in n+ Poly-Si/HfO2 and examination of leakage paths by conducting atomic force microscopy [J]. IEEE Electron Device Lett.,2007,28(5):373-375
[14]Andreas Kerber, et al. Charge Trapping and Dielectric Reliability of SiO2-Al2O3 Gate Stacks With TiN Electrodes [J]. IEEE Trans. Electr. Dev.,2003,50(5): 1261-1269
[15]J. R. Hauser and K. Ahmed. Characterization of ultra-thin oxides using electrical C-V and 1-V measurements [C]. Proc. AIP Conf.,1998,235-239
[16]G. S. Lujan, T. Schram, L. Pantisano, et al. Impact of ALCVD and PVD titanium nitride deposition on metal gate capacitors [C]. Proc.32nd ESSDERC,2002,583-586
[17]Jeonz S h, Kim C W. The effect of fixed oxide charge in Al2O3 blocking dielectric on memory properties of Charge Trap Flash Memory devices [J]. EL SOLID ST,2006,9 (8):G265-G267
[18]Lai S C, Chen C P, Du P Y, et al. A Study of barrier engineered A12O3 and HfO2 High-κ Charge Trapping Devices (BE-MAONOS and BE-MHONOS) with optimal High-κ thickness [C]. IEEE international memory workshop,2010
[19]J. K. Park et al, Improvement of memory performance by high temperature annealing of the Al2O3 blocking layer in a charge-trap type flash memory device [J]. App. Phys. Lett.,2010,96:222902
[20]J. Hauser, CVC, Version 3.0, Department of E&CE, North Carolina State University, USA,1996
[21]Suhane A, Arreghini A, et al. Experimental assessment of electrons and holes in erase transient of TANOS and TANVaS memories [J]. IEEE Electron Device Letter, 2010,31(9):936-938
[22]Gildenblat G Compact Modeling:Principles, Techniques and Applications: Springer,2010, pp.332-335
[23]V A Gritsenko, et al. Electronic structure of memory traps in silicon nitride [J]. Microelectron Eng,2009,86:786-791
[24]Ielmini D, et al. Modeling of SILC based on electron and hole tunneling—Part Ⅰ: transient effects [J]. IEEE Trans Electron Devices,2000,47(6):1258-1265
[25]Padovani A, et al. Modeling TANOS memory program transients to investigate charge-trapping dynamics [J]. IEEE Electron Device Letter,2009,30(8):882-884
[26]Rahman M S, et al. SILC decay in La2O3 gate dielectrics grown on Ge substrates subjected to constant voltage stress [J]. Solid State Electron,2010,54:979-984
[27]Campabadal F, et al. Electrical characteristics of metal-insulator-semiconductor structures with atomic layer deposited AI2O3, HfO2, and nanolaminates on different silicon substrates [J]. J Vac Sci Technol B,2011,29(1):01AA07
[28]A. Rothschild, et al. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory [C]. Solid State Device Research Conference,2009,272-275
[29]M. Lisiansky, et al. SiO2/Si3N4/Al2O3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing [J]. Appl. Phys. Lett.,2006,89:153506
[30]Sanghun Jeon et al. The Effect of Fixed Oxide Charge in Al2O3 Blocking Dielectric on Memory Properties of Charge Trap Flash Memory Devices [J]. Electrochemical and Solid-State Letters,2006,9 (8):G265-G267
[31]Man Chang et al. Improvement of memory properties for MANOS-type nonvolatile memory devices with high-pressure wet vapor annealing [J]. Microelectronic Engineering,2007,84:2002-2005
[32]Srikant Jayanti, et al. Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures [J]. Appl. Phys. Lett.2010,96:092905
[I]Kim K, Jeong G. Memory Technologies for sub-40nm Node [C]. IEDM Tech. Dig.,2007,27-30
[2]J. Jang H-S. Kim W. Cho H. Cho J. Kim et al. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra highdensity NAND flash memory [C]. VLSI symposia,2009,192-193
[3]A. Suhane et al. High Performance THANVaS Memories for MLC Charge Trap NAND Flash [C]. IEEE Int. Memory Workshop (IMW),2011
[4]D. Gilmer, N. Goel, et al. Engineering the complete MANOS-type NVM stack for best in class retention performance [C]. IEDM Tech. Dig.,2009,439-442
[5]Wu J Y et al. Ultrathin HfON Trapping Layer for Charge-Trap Memory Made by Atomic Layer Deposition [J]. IEEE Electron. Device. Lett.,2010,31(9):993-995
[6]FRANK A. SEWELL et al. The Light-Sensitive MNOS Memory Transistor [J]. IEEE Tran Electr Dev,1973, ED-20(6):563-572
[7]V. Mikhelashvili, et al. Optical properties of nonvolatile memory capacitors based on gold nanoparticles and SiO2-HfO2 sublayers [J]. Appl Phys Lett,2011,98: 022905
[8]V. Mikhelashvili, et al. The effect of light irradiation on electrons and holes trapping in nonvolatile memory capacitors employing sub 10 nm SiO2-HfO2 stacks and Au nanocrystals [J]. Microelectron Eng,2011,88:964-968
[9]D. K. Schroder et al. Bulk and Optical Generation Parameters Measured with the Pulsed MOS Capacitor [J]. IEEE Trans. Electron Devices,1972, ED-19(9):1018-1023
[10]D.K. Schroder et al. Recombination Lifetime Using the Pulsed MOS Capacitor [J]. IEEE Trans. Electron Devices,1984, ED-31(4):462-467
[11]Takaaki Baba, Takayuki Sagishima, et al. Transient Analysis of Electrical and Linear Charge Preset on the Input Stage of Surface CCD's [J]. IEEE Trans. Electron Devices,1978, ED-25(9):1101-1109
[12]T. Ando, et al. Analysis of optical writing mode in solid-state imaging devices with inherent MNOS memory [C]. IEE PROCEEDINGS,1986, (133) Pt. I No. I:6-12
[13]Hiroyuki Yamasmi, et al. Novel Solid-state Imaging Devices with Inherent MNOS Memory Gate [J]. IEEE Trans. Electron Devices,1985, ED-32(4):738-743
[14]M. H. White and J. R. Cricchi, "Characterization of thin-oxide MNOS memory transistors," IEEE Trans. Electron Devices,1972, ED-19(12):1280-1288
[15]S. M. Sze, in "Physics of Semiconductor Devices" 2nd edition,1981, p 366.
[16]James Victory, et al. A Time-Dependent, Surface Potential Based Compact Model for MOS Capacitors [J]. IEEE Electron. Device. Lett.,2001,22(5):245-247
[17]Z. Zhu, in "Compact Modeling:Principles, Techniques and Applications", edited by G. Gildenblat, (2010, Springer, Dordrecht), p.334.
[18]Padovani A, et al, A Comprehensive Understanding of the Erase of TAN OS Memories Through Charge Separation Experiments and Simulations [J]. IEEE Trans. Electr. Dev.,2011,58(9):3147-3155
[19]A. Mauri et al. A new physics-based model for MANOS memories program/erase [C].2008, IEDM Tech. Dig.,555-558
[20]T. H. Ning, H. N. Yu. Optically induced injection of hot electrons into SiO2 [J]. J. Appl. Phys.,1974,45(12):5373-5378
[2]F. Masuoka, M. Asano, H. Iwahashi, T. Komuro and S. Tanaka, A new flash E2PROM cell using triple polysilicon technology [C]. IEDM Tech. Dig.,1984: 464-467
[3]International Technology Roadmap for Semiconductors, http://www.itrs.net/,2010
[4]K. Kim, Technology for sub-50nm DRAM and NAND flash manufacturing [C]. IEDM Tech. Dig.,2005:323-326
[5]C. Y. Lu, K. Y. Hsieh and R. Liu, Future challenges of flash memory technologies [J]. Microelectron. Eng.,2009,86:283-286
[6]A. Sikora, F. P. Pesl, W. Unger, et al., Technologies and reliability of modern embedded flash cells [J]. Microelectron. Reliab.,2006,46:1980-2005
[7]K. Kim and G. Jeong, Memory technologies for sub-40nm node [C]. IEDM Tech. Dig.,2009:27-30
[8]G. Molas, M. Bocquet, E. Vianello, et al., Reliability of charge trapping memories with high-k control dielectrics [J]. Microelectron. Eng.,2009,86:1796-1803
[9]L. Larcher and A. Padovani, A high-k related reliability issues in advanced non-volatile memories [J]. Microelectron. Reliab.,2010,50:1251-1258
[10]B. Govoreanu, P. Blomme, J. Van Houdt, et al., Enhanced tunneling current effect for nonvolatile memory applications [J]. Jpn. J. Appl. Phys.,2003, 42:2020-2024
[11]J. D. Casperson, L. D. Bell and H. A. Atwater, Materials issues for layered tunnel barrier structures [J]. J. Appl. Phys.,2008,92:261-267
[12]M. H. White, D. A. Adams and J. Bu, On the go with SONOS [J]. IEEE Circuits and Devices,2000,16:22-31.
[13]B. Eitan, P. Pavan, I. Bloom, et al., NROM:a novel localized trapping 2-bit nonvolatile memory cell [J]. IEEE Electron Device Lett.,2000,21:543-545.
[14]C. H. Lee, K. I. Choi, M. K. Cho, et al., A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories [C]. IEDM Tech. Dig.,2003:613-616
[1]Mori S, et al. ONO inter-poly dielectric scaling for nonvolatile memory Applications [J]. IEEE Trans Electron Dev,1991,38(2):386-391
[2]Mori S, et al. Thickness scaling limitation factors for ONO interpoly dielectric for nonvolatile memory devices [J]. IEEE Trans Electron Dev,1996,43(1):47-53
[3]Jiankang Bu, Marvin H. White. Design considerations in scaled SONOS nonvolatile memory devices [J]. Solid State Electron,2001,45:113-120
[4]Yang Yang, Marvin H. White. Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures [J]. Solid State Electronic,2000,44: 949-958
[5]Marvin H.White. On the go with SONOS [J]. IEEE Circuits and Devices,2000, 16(4):22-31
[6]Chang-Hyun Lee, et al. Charge-trapping device structure of SiO2/SiN/high-k dielectric A12O3 for high-density flash memory [J]. Appl Phys Lett,2005,86:152908
[7]G. Molas, et al. Reliability of charge trapping memories with high-k control dielectrics [J]. Microelectron Eng,2009,86:1796-1803
[8]M. Bocquet, G. Molas, et al. [C]. Proceedings of ESSDERC,2008, pp.110-122.
[9]Chang Yong Kang. Barrier engineering in metal-aluminum oxide nitride-oxide-silicon (MANOS) flash memory [J]. Curr Appl Phys,2010,10:e27-e31
[10]Chang Hyun Lee, Kyung Choi, et al. A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit Hash memeries [C]. IEDM Tech. Dig,2003,613-616
[11]Wei Chen, Wen-Jun Liu, et al. Multistacked Al2O3/HfO2/SiO2 tunnel layer for high-density nonvolatile memory application [J]. Appl Phys Lett,2007,91:022908
[12]Sheng-Chih Lai, Hang-Ting Lue et al. Study of the Erase Mechanism of MANOS (Metal/Al2O3/SiN/SiO2/Si) Device [J]. IEEE Electron Dev Lett,2007,28(7): 643-645
[13]SMaikap, H Y Lee, et al. Charge trapping characteristics of atomic-layer-deposited HfO2 films with AI2O3 as a blocking oxide for high-density non-volatile memory device applications [J]. Semicond. Sci. Technol.,2007,22: 884-889
[14]Almudena H M, Rob V S, Michiel V D, et.al. Reliability comparison of Al2O3 and HfSiON for use as interpoly dielectric in flash arrays. [C]. Proceedings of 36th European solid-state research conference,2006,234-237.
[15]B. Govoreanu, R. Degraeve, et al. Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate Flash memory [J]. Microelectron Eng,2009,86:1807-1811
[16]He W, Pu J, Chan D, et.al. Performance improvement in charge-trap flash memory using Lanthanum-based high-κ blocking oxide [J]. IEEE Trans Electron Dev,2009,56:2746-2751
[17]Chih-Hao C, Joseph Y-M L. Metal-high-k-high-k-oxide-semiconductor capacitors and field effect transistors using Al/La2O3/Ta2O5/SiO2/Si structure for nonvolatile memory applications [J]. Appl Phys Lett,2007,91:192903
[18]Jing P, Daniel S H C, Sun-Jung K, et.al. Aluminum-Doped Gadolinium Oxides as bl。Cking layer for improved charge retention in Charge-Trap-Type nonvolatile memory devices [J]. IEEE Trans Electr Dev,2009,56(11):2739-2745
[19]Wang X, Liu J, Bai W, et.al. A novel MONOS-type nonvolatile memory using high-k dielectrics for improved data retention and programming speed [J]. IEEE Trans Electr Dev,2004,51(5):597-602
[20]Sheng-Chih L, Hang-Ting L, Ming-Jui Y, et.al. MA BE-SONOS:a bandgap engineered SONOS using metal gate and Al2O3 blocking layer to overcome erase saturation [C]. IEEE Non-Volatile Semiconductor Memory Workshop,2007,88-89
[21]Ping-Hung T, Kuei-Shu Chang-Liao, Dong-Wei Y, et.al. Crucial integration of high work-function metal gate and high-k blocking oxide on charge-trapping type flash memory device [J]. Appl Phys Lett,2008,93:252902
[22]Chi-Pei L, Cheng-Kei L, Bing-Yue T, et al. Nanoscale multigate TiN metal nanocrystal memory using high-k blocking dielectric and high-work-function gate electrode integrated on Silcon-on-Insulator substrate [J]. Japanese Journal of Applied Physics,2009,48:04C059
[23]J. Robertson. Band offsets of wide-band-gap oxides and implications for future electronic devices [J]. Journal of Vacuum Science Technology-Part B,2000,18: 1785-1791
[24]G Molas, M. Bocquet, et al. Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories [J]. Microelectron Eng,2008,85: 2393-2399
[25]W. He, D. S. H. Chan, et al. Process and material properties of LaHfOx prepared by atomic layer deposition [J]. J. Electrochem. Soc.,2008,155(10):189-193
[26]E. A. Kraut, R. W. Grant, et al. Precise determination of the valence-band edge in X-ray photoemission spectra:Application to measurement of semiconductor interface potentials [J]. Phys.Rev. Lett.,1980,44(24):1620-1623
[1]Sangmoo Choi, et al. Improved metal-oxide-nitride-oxide-silicon-type flash device with high-k dielectrics for blocking layer [J]. J. Appl. Phys.,2003,94(8): 5408-5410
[2]M Bocquet, et al. Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories [J]. Solid State Electron,2009,53:786-791
[3]Arnaud F et.al. Physical understanding and modeling of SANOS retention in programmed state [J]. Solid State Electronics,2008,52:577-583
[4]L Larcher, A Padovani, et al. Investigation of trapping/detrapping mechanisms in Al2O3 electron/hole traps and their influence on TANOS memory operations [C]. VLSI Technology Systems and Applications (VLSI-TSA),2010,52-53
[5]Lai S C, et al. A Study of barrier engineered Al2O3 and HfO2 High-κ Charge Trapping Devices (BE-MAONOS and BE-MHONOS) with optimal High-κ thickness [C]. IEEE international memory workshop,2010
[1]Gan Wang, Marvin H. White. Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices [J]. Solid-State Electronics,2008,52: 1491-1497
[2]Chang Yong Kang. Barrier engineering in metal-aluminum oxide-nitride-pxide-silicon (MANOS) flash memory [J]. Current Applied Physics, 2010,10:e27-e31
[3]Dirk Wellekens, Pieter Blomme, Bogdan Govoreanu, et al. Al2O3 based flash interpoly dielectrics:a comparative retention study [C]. Proceedings of the European Solid-State Device Research Conference,2006. p.238-241
[4]M. Florian Beug, et al. Analysis of TANOS memory cells with sealing oxide containing blocking dielectric [J]. IEEE Transactions on Electron Devices,2010, 57(7):1590-1596
[5]Salvatore M. Amoroso et al. Reliability Constraints for TANOS Memories due to Alumina Trapping and Leakage [C]. IEEE Reliability Physics Symposium IRPS, 2010,966-969
[6]L Larcher, A Padovani, et al. Investigation of trapping/detrapping mechanisms in AI2O3 electron/hole traps and their influence on TANOS memory operations [C]. VLSI Technology Systems and Applications (VLSI-TSA),2010,52-53
[7]Dirk Wellekens, Joeri De Vos, et al. Optimization of Al2O3 interpoly dielectric for embedded flash memory applications [C]. Proceedings of Joint Non Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design,2008,12-15
[8]V. V. Afanas'ev, et al. Impact of annealing-induced compaction on electronic properties of atomic-layer-deposited Al2O3 [J]. Applied Physics Letter,2002,81(9): 1678-1680
[9]M. Lisiansky, et al. SiO2/Si3N4/Al2O3 stacks for scaled-down memory devices: effects of interfaces and thermal annealing [J]. Applied Physics Letter,2006,89: 153506
[10]Mario Lanza, Marc Porti, et al. Conductivity and Charge Trapping After Electrical Stress in Amorphous and Polycrystalline Al2O3-Based Devices Studied With AFM-Related Techniques [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY,2011,10(2):344-351
[11]W.Weinreich, L.Wilde, P. Kucher, et al. Correlation of microscopic and macroscopic electrical characteristics of high-k ZrSixO2 thin films using tunneling atomic force microscopy [J]. J. Vac. Sci. Technol. B,2009,27(1):364-368,.
[12]Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, et al. Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode [C]. IEEE IEDM,2001, pp. 20.2-1-20.2-4
[13]X. Yu, et al. Effect of gate dopant diffusion on leakage current in n+ Poly-Si/HfO2 and examination of leakage paths by conducting atomic force microscopy [J]. IEEE Electron Device Lett.,2007,28(5):373-375
[14]Andreas Kerber, et al. Charge Trapping and Dielectric Reliability of SiO2-Al2O3 Gate Stacks With TiN Electrodes [J]. IEEE Trans. Electr. Dev.,2003,50(5): 1261-1269
[15]J. R. Hauser and K. Ahmed. Characterization of ultra-thin oxides using electrical C-V and 1-V measurements [C]. Proc. AIP Conf.,1998,235-239
[16]G. S. Lujan, T. Schram, L. Pantisano, et al. Impact of ALCVD and PVD titanium nitride deposition on metal gate capacitors [C]. Proc.32nd ESSDERC,2002,583-586
[17]Jeonz S h, Kim C W. The effect of fixed oxide charge in Al2O3 blocking dielectric on memory properties of Charge Trap Flash Memory devices [J]. EL SOLID ST,2006,9 (8):G265-G267
[18]Lai S C, Chen C P, Du P Y, et al. A Study of barrier engineered A12O3 and HfO2 High-κ Charge Trapping Devices (BE-MAONOS and BE-MHONOS) with optimal High-κ thickness [C]. IEEE international memory workshop,2010
[19]J. K. Park et al, Improvement of memory performance by high temperature annealing of the Al2O3 blocking layer in a charge-trap type flash memory device [J]. App. Phys. Lett.,2010,96:222902
[20]J. Hauser, CVC, Version 3.0, Department of E&CE, North Carolina State University, USA,1996
[21]Suhane A, Arreghini A, et al. Experimental assessment of electrons and holes in erase transient of TANOS and TANVaS memories [J]. IEEE Electron Device Letter, 2010,31(9):936-938
[22]Gildenblat G Compact Modeling:Principles, Techniques and Applications: Springer,2010, pp.332-335
[23]V A Gritsenko, et al. Electronic structure of memory traps in silicon nitride [J]. Microelectron Eng,2009,86:786-791
[24]Ielmini D, et al. Modeling of SILC based on electron and hole tunneling—Part Ⅰ: transient effects [J]. IEEE Trans Electron Devices,2000,47(6):1258-1265
[25]Padovani A, et al. Modeling TANOS memory program transients to investigate charge-trapping dynamics [J]. IEEE Electron Device Letter,2009,30(8):882-884
[26]Rahman M S, et al. SILC decay in La2O3 gate dielectrics grown on Ge substrates subjected to constant voltage stress [J]. Solid State Electron,2010,54:979-984
[27]Campabadal F, et al. Electrical characteristics of metal-insulator-semiconductor structures with atomic layer deposited AI2O3, HfO2, and nanolaminates on different silicon substrates [J]. J Vac Sci Technol B,2011,29(1):01AA07
[28]A. Rothschild, et al. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory [C]. Solid State Device Research Conference,2009,272-275
[29]M. Lisiansky, et al. SiO2/Si3N4/Al2O3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing [J]. Appl. Phys. Lett.,2006,89:153506
[30]Sanghun Jeon et al. The Effect of Fixed Oxide Charge in Al2O3 Blocking Dielectric on Memory Properties of Charge Trap Flash Memory Devices [J]. Electrochemical and Solid-State Letters,2006,9 (8):G265-G267
[31]Man Chang et al. Improvement of memory properties for MANOS-type nonvolatile memory devices with high-pressure wet vapor annealing [J]. Microelectronic Engineering,2007,84:2002-2005
[32]Srikant Jayanti, et al. Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures [J]. Appl. Phys. Lett.2010,96:092905
[I]Kim K, Jeong G. Memory Technologies for sub-40nm Node [C]. IEDM Tech. Dig.,2007,27-30
[2]J. Jang H-S. Kim W. Cho H. Cho J. Kim et al. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra highdensity NAND flash memory [C]. VLSI symposia,2009,192-193
[3]A. Suhane et al. High Performance THANVaS Memories for MLC Charge Trap NAND Flash [C]. IEEE Int. Memory Workshop (IMW),2011
[4]D. Gilmer, N. Goel, et al. Engineering the complete MANOS-type NVM stack for best in class retention performance [C]. IEDM Tech. Dig.,2009,439-442
[5]Wu J Y et al. Ultrathin HfON Trapping Layer for Charge-Trap Memory Made by Atomic Layer Deposition [J]. IEEE Electron. Device. Lett.,2010,31(9):993-995
[6]FRANK A. SEWELL et al. The Light-Sensitive MNOS Memory Transistor [J]. IEEE Tran Electr Dev,1973, ED-20(6):563-572
[7]V. Mikhelashvili, et al. Optical properties of nonvolatile memory capacitors based on gold nanoparticles and SiO2-HfO2 sublayers [J]. Appl Phys Lett,2011,98: 022905
[8]V. Mikhelashvili, et al. The effect of light irradiation on electrons and holes trapping in nonvolatile memory capacitors employing sub 10 nm SiO2-HfO2 stacks and Au nanocrystals [J]. Microelectron Eng,2011,88:964-968
[9]D. K. Schroder et al. Bulk and Optical Generation Parameters Measured with the Pulsed MOS Capacitor [J]. IEEE Trans. Electron Devices,1972, ED-19(9):1018-1023
[10]D.K. Schroder et al. Recombination Lifetime Using the Pulsed MOS Capacitor [J]. IEEE Trans. Electron Devices,1984, ED-31(4):462-467
[11]Takaaki Baba, Takayuki Sagishima, et al. Transient Analysis of Electrical and Linear Charge Preset on the Input Stage of Surface CCD's [J]. IEEE Trans. Electron Devices,1978, ED-25(9):1101-1109
[12]T. Ando, et al. Analysis of optical writing mode in solid-state imaging devices with inherent MNOS memory [C]. IEE PROCEEDINGS,1986, (133) Pt. I No. I:6-12
[13]Hiroyuki Yamasmi, et al. Novel Solid-state Imaging Devices with Inherent MNOS Memory Gate [J]. IEEE Trans. Electron Devices,1985, ED-32(4):738-743
[14]M. H. White and J. R. Cricchi, "Characterization of thin-oxide MNOS memory transistors," IEEE Trans. Electron Devices,1972, ED-19(12):1280-1288
[15]S. M. Sze, in "Physics of Semiconductor Devices" 2nd edition,1981, p 366.
[16]James Victory, et al. A Time-Dependent, Surface Potential Based Compact Model for MOS Capacitors [J]. IEEE Electron. Device. Lett.,2001,22(5):245-247
[17]Z. Zhu, in "Compact Modeling:Principles, Techniques and Applications", edited by G. Gildenblat, (2010, Springer, Dordrecht), p.334.
[18]Padovani A, et al, A Comprehensive Understanding of the Erase of TAN OS Memories Through Charge Separation Experiments and Simulations [J]. IEEE Trans. Electr. Dev.,2011,58(9):3147-3155
[19]A. Mauri et al. A new physics-based model for MANOS memories program/erase [C].2008, IEDM Tech. Dig.,555-558
[20]T. H. Ning, H. N. Yu. Optically induced injection of hot electrons into SiO2 [J]. J. Appl. Phys.,1974,45(12):5373-5378
© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号 地址：北京市海淀区学院路29号 邮编：100083 电话：办公室：(+86 10)66554848；文献借阅、咨询服务、科技查新：66554700 |