基于Boole过程的考虑互连效应的EDA方法研究
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摘要
在VDSM工艺下,对IC电路进行逻辑级模拟验证、测试生成、布局和布线等技术处理时,均要考虑互连效应所产生的影响,只有这样才能较真实地反映电路的特性。本文对Boole过程论中的波形计算进行了扩展,运用该理论研究上述四方面技术中的考虑互连效应的新算法。
互连效应,特别是其中的串扰问题对电路的逻辑和时序有着严重的影响,仅凭传统的逻辑级模拟已经不能反映电路的真实情况。目前的模拟验证技术必须考虑互连效应。而准确地考虑这些因素还必须要做模拟布图。耦合电容和动态的信号跳变情况是产生串扰的两个重要因素,其中后者决定了串扰能否发生,因此通过逻辑级模拟产生的波形关系对串扰估计和优化就具有了重要作用。运用考虑互连效应的模拟所获得的信号跳变数可以较为准确地估计电路的功耗。
本文提出了基于Boole过程论的逻辑级模拟验证方法。针对冒险检测、反馈环路的处理、伪路径识别和惯性延迟冲突等波形模拟中的关键问题,采用基于Boole过程的方法进行描述、分析和解决。冒险检测定理给出了通过波形运算检测电路中冒险现象的形式化方法;分时片处理法和波形递增算法解决了Boole过程在处理电路中反馈环问题上的缺陷;伪路径识别算法能够有效地发现电路网表中的冗余部分;而惯性冲突消除法能使信号波形的描述更加准确。本文运用这些概念和结论设计了并行逻辑级模拟基本算法。该算法不需要对初始数据进行划分,而是利用活动元件计算的高度并行性在模拟过程中动态地形成活动元件队列的方法进行并行计算。本算法通过对队列中的元素计算调度优先权的方法提高了并行加速比。
为了模拟互连效应下的逻辑波形,本文将互连线看作一个元件,定义了其上的原始波形、串扰波形和互连传输门。在给定工艺和版图信息的条件下,提出了基于Boole过程中波形表示的互连线上的串扰波形计算方法。定义了逻辑-串扰关系图,将逻辑级模拟基本算法和串扰计算结合起来,并通过该图完成了考虑互连效应的逻辑波形模拟。本文使用VHDL描述了互连线串
The technology treatment with IC in VDSM, for example logic level simulation, ATPG, routing and placement, must consider the interconnect effect. Otherwise the characteristic of circuits can not be reflected more factually, some extensions are done on the waveform computing in Boolean Process in this dissertation, by which some new algoritms considering interconnect effect are discussed in above four technologies.Interconnect effect, especially crosstalk disturbs the logic and time sequence badly, the traditional logic level simulation can not reflect the factual state of circuit. So interconnect effect must be considered in simulation technology. The layout simulation must be done for considering the factors exactly. Coupling capacitance and dynamic switches of signals are two important crosstalk factor. Dynamic switches of signals decide the generation of crosstalk. So the waveforms relation generated by logic level simulation has important effect on the estimation and optimization of crosstalk. The power of circuit can be estimated more exactly by the sum of switches of circuit generated by the simulation considering interconnect effect.A Boolean Process-based logic level simulation method is presented in this dissertation. Some critical problems, for example hazards finding, feedback cycle treatment, false paths finding and inertial delay conflict, are described, analysed and solved. The hazards finding theory is a formal method to find hazards in circuit by computing waveforms. Time piece method and waveform increase algorithm solve the defect of Boolean Process in feedback cycle treatment. False path finding algorithm can the redundant part in netlist. inertial conflict elimination can describe waveforms more exactly. Utilizing above concepts and results, a parallel algorithm for logic level simulation is presented. It need not partition the data, but forms the active components queue to realize parallel computing in simulation. The algorithm improves acceleration ratio by scheduling priority.
For simulating the logic waveforms in interconnect effect, the ' interconnect component' is defined, including its original waveform, crosstalk waveform and interconnect transport gate. A Boolean Process-based computing method for crosstalk waveforms on nets is presented after obtaining layout information. The Logic-Crosstalk Graph is defined. It integrates the basic algorithm of logic level simulation and corsstalk computing, by which the waveforms simulation considering interconnect effect can be performed. The crosstalk delay computing of interconnect are described in VHDL.Aiming at the sensitization concept in Boolean Process, the computing rules of sensitization waveforms sets with time windows are defined, the method generating test waveforms in crosstalk is presented.For minimizing crosstalk in detailed routing, the distance between waveforms in Boolean Process is defined newly. Integrating coupling capacitance, the crosstalk between nets is defined. Based on above work, the object function for minimizing crosstalk in two-layer detailed routing is presented. It can reflect the crosstalk between nets more exactly and afford more space for adjusting routing. Routing generating tree and improved GA are presented, by which the channel routing method with minimizing crosstalk is designed. It can reduce the cost of computing. Variable parameter method is presented to design the routing algorithm with optimizing crosstalk, and the routing resource is utilized fully. Above methods have potential parallelism because of computing of all nets is performed simultaneity.The waveform computing considering interconnect effect can be utilized to estimate the power of circuit more exactly. So a macrocell placement algorithm that both minimizes length of wires and distributes power equably is presented. It considers the position of cell' pins, makes the minimizing of length of wires more flexible. The confirming of power centre makes the picking up of power more convenient. Algorithm decomposes big scale placement optimization by grouping and reduces the sum of wires by integrating.
互连效应,特别是其中的串扰问题对电路的逻辑和时序有着严重的影响,仅凭传统的逻辑级模拟已经不能反映电路的真实情况。目前的模拟验证技术必须考虑互连效应。而准确地考虑这些因素还必须要做模拟布图。耦合电容和动态的信号跳变情况是产生串扰的两个重要因素,其中后者决定了串扰能否发生,因此通过逻辑级模拟产生的波形关系对串扰估计和优化就具有了重要作用。运用考虑互连效应的模拟所获得的信号跳变数可以较为准确地估计电路的功耗。
本文提出了基于Boole过程论的逻辑级模拟验证方法。针对冒险检测、反馈环路的处理、伪路径识别和惯性延迟冲突等波形模拟中的关键问题,采用基于Boole过程的方法进行描述、分析和解决。冒险检测定理给出了通过波形运算检测电路中冒险现象的形式化方法;分时片处理法和波形递增算法解决了Boole过程在处理电路中反馈环问题上的缺陷;伪路径识别算法能够有效地发现电路网表中的冗余部分;而惯性冲突消除法能使信号波形的描述更加准确。本文运用这些概念和结论设计了并行逻辑级模拟基本算法。该算法不需要对初始数据进行划分,而是利用活动元件计算的高度并行性在模拟过程中动态地形成活动元件队列的方法进行并行计算。本算法通过对队列中的元素计算调度优先权的方法提高了并行加速比。
为了模拟互连效应下的逻辑波形,本文将互连线看作一个元件,定义了其上的原始波形、串扰波形和互连传输门。在给定工艺和版图信息的条件下,提出了基于Boole过程中波形表示的互连线上的串扰波形计算方法。定义了逻辑-串扰关系图,将逻辑级模拟基本算法和串扰计算结合起来,并通过该图完成了考虑互连效应的逻辑波形模拟。本文使用VHDL描述了互连线串
The technology treatment with IC in VDSM, for example logic level simulation, ATPG, routing and placement, must consider the interconnect effect. Otherwise the characteristic of circuits can not be reflected more factually, some extensions are done on the waveform computing in Boolean Process in this dissertation, by which some new algoritms considering interconnect effect are discussed in above four technologies.Interconnect effect, especially crosstalk disturbs the logic and time sequence badly, the traditional logic level simulation can not reflect the factual state of circuit. So interconnect effect must be considered in simulation technology. The layout simulation must be done for considering the factors exactly. Coupling capacitance and dynamic switches of signals are two important crosstalk factor. Dynamic switches of signals decide the generation of crosstalk. So the waveforms relation generated by logic level simulation has important effect on the estimation and optimization of crosstalk. The power of circuit can be estimated more exactly by the sum of switches of circuit generated by the simulation considering interconnect effect.A Boolean Process-based logic level simulation method is presented in this dissertation. Some critical problems, for example hazards finding, feedback cycle treatment, false paths finding and inertial delay conflict, are described, analysed and solved. The hazards finding theory is a formal method to find hazards in circuit by computing waveforms. Time piece method and waveform increase algorithm solve the defect of Boolean Process in feedback cycle treatment. False path finding algorithm can the redundant part in netlist. inertial conflict elimination can describe waveforms more exactly. Utilizing above concepts and results, a parallel algorithm for logic level simulation is presented. It need not partition the data, but forms the active components queue to realize parallel computing in simulation. The algorithm improves acceleration ratio by scheduling priority.
For simulating the logic waveforms in interconnect effect, the ' interconnect component' is defined, including its original waveform, crosstalk waveform and interconnect transport gate. A Boolean Process-based computing method for crosstalk waveforms on nets is presented after obtaining layout information. The Logic-Crosstalk Graph is defined. It integrates the basic algorithm of logic level simulation and corsstalk computing, by which the waveforms simulation considering interconnect effect can be performed. The crosstalk delay computing of interconnect are described in VHDL.Aiming at the sensitization concept in Boolean Process, the computing rules of sensitization waveforms sets with time windows are defined, the method generating test waveforms in crosstalk is presented.For minimizing crosstalk in detailed routing, the distance between waveforms in Boolean Process is defined newly. Integrating coupling capacitance, the crosstalk between nets is defined. Based on above work, the object function for minimizing crosstalk in two-layer detailed routing is presented. It can reflect the crosstalk between nets more exactly and afford more space for adjusting routing. Routing generating tree and improved GA are presented, by which the channel routing method with minimizing crosstalk is designed. It can reduce the cost of computing. Variable parameter method is presented to design the routing algorithm with optimizing crosstalk, and the routing resource is utilized fully. Above methods have potential parallelism because of computing of all nets is performed simultaneity.The waveform computing considering interconnect effect can be utilized to estimate the power of circuit more exactly. So a macrocell placement algorithm that both minimizes length of wires and distributes power equably is presented. It considers the position of cell' pins, makes the minimizing of length of wires more flexible. The confirming of power centre makes the picking up of power more convenient. Algorithm decomposes big scale placement optimization by grouping and reduces the sum of wires by integrating.
引文
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