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LDPC码快速及低错误平层译码算法研究
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摘要
LDPC码具有逼近香农限的良好译码性能,故而得到了广泛的研究。为了获取更好的译码性能,LDPC码的各种译码算法得到深入的研究。置信传播具有良好的译码性能,但是在其译码过程中易出现较高的错误平层,因此无法满足一些对数据传输质量要求极高的通信系统数据高可靠传输的需求;改进型比特翻转算法计算复杂度较低可以用于构造大吞吐量LDPC译码器,能够更好地满足高速数据传输系统纠错译码的需求。本文主要研究置信传播算法的低错误平层译码以及改进型比特翻转算法的快速译码等问题,主要研究内容如下。
     首先,为了提高LDPC译码器的译码速度,本文提出了并行比特选择机制来降低加权比特翻转算法硬件实现时挑选翻转比特造成的时延。具体来讲,依据接收向量中错误比特均匀分布的特点,将所有比特划分成若干子块,从每个子块挑选出一个比特作为候选翻转比特,最后根据一定的准则从这些候选比特中选择部分比特进行翻转完成译码迭代。此外,本文还通过引入树形搜索技术降低候选比特查找的计算复杂度,进一步增加算法硬件实现时的译码速度。
     其次,为了提高可靠性权重比特翻转(reliability ratio-based weighted bit-flipping,RRWBF)算法的译码速度,本文提出多比特翻转机制来加快RRWBF算法的收敛速度。具体来讲,在每次译码迭代中,根据伴随向量的重量选择合理数量的比特,然后同时翻转这些比特的硬判结果来完成迭代译码,进而有效的解决RRWBF算法中由单比特翻转造成的收敛速度慢的问题。另外,本文还提出了一种新颖的迭代提前停止机制用于消除算法译码过程中出现的无效迭代,从而进一步提高算法的收敛速度。但是,使用多比特翻转机制的RRWBF算法,译码过程中出现与单比特翻转类似的循环翻转现象,影响其译码性能。为此,本文提出一种循环翻转消除机制来破坏多比特翻转译码过程中产生的循环翻转,进而提高其译码性能。
     本文还提出稳定陷阱集的概念来描述LDPC码译码过程中出现的错误平层现象,并且相应提出一种基于稳定陷阱集破坏的改进置信传播算法用以降低LDPC码的错误平层。具体来讲,稳定陷阱集中比特节点信息值的排名会随着译码迭代进行不断下降。利用这一特性可以更加高效准确地将这些节点挑选出来,之后将其初始对数似然值翻转达到集破坏的目的。最后将修正后的初始似然值序列送入译码器进行翻转译码尝试以降低LDPC码的错误平层。另外,在置信传播算法的译码过程中会出现大量的震荡错误,即一些比特节点的硬判决结果在译码过程中呈现震荡状态从而导致译码失败。本文提出不稳定陷阱集的概念来描述这种错误类型,并且相应提出一种改进型置信传播算法以消除译码过程中出现的震荡错误进而达到提高LDPC码译码性能的目的。
     最后,本文针对欧氏几何LDPC码码字的循环特性以及fast weighted bitflipping (FWBF)算法的结构特点设计高速LDPC译码器。欧氏几何LDPC码具有良好的低错误平层特性,结合FWBF算法的快速译码特性,可以很好满足光通信等高速、高质量传输通信系统的要求。
Because of its near Shannon-limit performance, low-density parity-check (LDPC)codes has obtained considerable study. In order to obtain a good decoding performance,all the decoding algorithms of LDPC codes have been extensively studied. Beliefpropagation (BP) algorithm has good decoding performance but appears a high errorfloor in its decoding process. Hence, BP cannot work well in the communicationssystem requiring an extremely low error rate. The modified weighted bit flipping (WBF)algorithms can be used to design a high-speed decoder because of their lowcomputational complexity, which makes the WBF-based algorithms work well in thehigh-speed data transmission system. In this paper, we study the modified BP algorithmto lower the error floor and the enhanced WBF algorithm to implement the fastdecoding of the LDPC codes.
     Firstly, In order to improve the decoding speed of LDPC codes, a fast weighted bitflipping algorithm with parallel bit-chosen is proposed to lower the delay of choosingthe flipped bit. In this scheme, all the bits are first divided into several blocks accordingto the uniform error distribution in the received vector. And then, one bit is chosen fromeach block to form the candidate set of the flipped bits. Finally, a proper number of bitsare chosen from the candidate set and flipped to implement the flipping decoding.Furthermore, the tree sorting method is adopted to decrease the computationalcomplexity of the key module of the proposed algorithm. The proposed scheme and themethod of hardware implement can achieve significant improvement in the decodingspeed.
     Secondly, in order to improve the decoding speed of the reliability ratio-basedweighted bit-flipping (RRWBF) algorithm, we propose a multiple-bits selectionmechanism to accelerate the decoding convergence of the RRWBF algorithm.Specifically, based on the weight of syndrome vector, reasonable quantities of bits areselected to flip in each iteration. This mechanism can effectively solve the problem oflow convergence speed of single-bit flipping algorithm. In addition, a novel earlystopping criterion is also introduced which can further raise up the convergence speedof the LDPC decoding. However, the RRWBF algorithm with the multiple-bits selection mechanism will appear the bit-repeated flipping, which can impair thedecoding performance of the RRWBF algorithm. Hence, a bit-repeated flippingelimination mechanism is proposed to reduce the bit-repeated flipping in the process ofthe multiple-bits flipping decoding.
     Thirdly, in order to more exactly describe the error-floor phenomenon in the iterativedecoding of LDPC codes, a modified concept of the stable trapping set is introduced.Based on this new concept, an improved belief propagation algorithm with set-breakingmechanism is proposed to lower the error-floors of LDPC codes. Specifically, messageranking of the bit nodes in the stable trapping sets will be greatly lowered than that ofother bit nodes in the iterative decoding process. By using this characteristic to label thebit nodes in the set, their initial log likelihood ratios will be flipped to break the stabletrapping set and then restart to decode. In the decoding process of the BP algorithm, itwill appear much oscillation error, namely, the hard-decision digits of some bit nodesare always changed, which can result in decoding failure. In order to describe this typeof decoding failure, a modified concept of the unstable trapping set is introduced. Basedon this new concept, an improved belief propagation algorithm is proposed to eliminatethe oscillation error to improve the decoding performance of the LDPC codes.
     Finally, a FWBF decoder is designed to implement the high-speed decoding ofEG-LDPC codes according to their cyclic characteristic. EG-LDPC codes have a lowerror floor and FWBF has a fast decoding speed. Hence, the FWBF decoder based onEG-LDPC codes can well applied in the communications systems which require thedata is transmitted with high speed and reliablity.
引文
[1] C.E.Shannon. mathematical theory of communication[J]. Bell Syst. Tech. J,1948,27:379-423,623-656; Reprinted in C. E. Shannon and W. Weaver, TheMathematical Theory of Communication. Urbana, IL: Univ. Illinois Press,1949.
    [2] Shu Lin. Error Control Coding,2rd ed.Prentice Hall,2004.
    [3] A.J.Vterbi.Error Bound for convolutional codes and asymptotically optimumdecoding algorithm [J]. IEEE Trans.Inform.Theory,1967,13:260-269.
    [4] I. S. Reed and G. Solomon. Polynomial codes over certain finite fields[J]. Journalof the Society for Industrial and Applied Mathematics,1960,8(2):300–304.
    [5] L. F. Wei. Rotationally invariant convolutional channel coding with expandedsignal space Part I:180degrees[J]. IEEE J. Select. Areas Commun.,1984,SAC-2:659-672.
    [6] Berrou, A. Glavieux, and P. Thitimajshima. Near Shannon limit error-correctingcoding and decoding: Turbo-codes[C]. in Proc. of the IEEE Int. Conf. onCommun., Geneva, Switzerland,1993,1064–1070.
    [7] C. Berrou and A. Glavieux. Near optimum error correcting and decoding: Turbo-codes[J]. IEEE Trans. Commun.,1996,44(10):1261–1271.
    [8] R. G. Gallager. Low-density parity-check codes[J]. IRE Trans. Inform. Theory,1962,8:21–28.
    [9] D. J. C. MacKay and R. M. Neal. Near Shannon limit performance of low densityparity check codes[J]. Electronics Letters,1996,32(18):1645–1646.
    [10] N. Wiberg, H.-A. Loeliger, and R. K etter. Codes and iterative decoding ongeneral graphs[J]. European Trans. Telecomm,1995,6:513-525.
    [11] S.-Y. Chung, G. D. Forney, T. J. Richardson, and R. Urbanke. On the design oflow density parity-check codes within0.0045dB of the Shannon limit[J]. IEEECommun. Lett.,2001,5(2):58–60.
    [12] J.Campello, D.S.Modha and S.Rajagopalan. Designing LDPC codes using bit-filling[C]. in Proc.IEEE International Conference on communications,2001,55-59.
    [13] J.Campello and D.S.Modha. Extended bit-filling and LDPC code design[C]. inProc. IEEE Global Telecommunications Conference,2001,985-989.
    [14] X.Y.Hu, E.Eleftheriou, and D.-M.Arnold. Progressive edge-growth Tanner graphs[C]. in Proc. IEEE Global Telecommun. Conf., San Antonio, TX, USA,2001,2:995–1001.
    [15] X.Y.Hu, E.Eleftheriou, and D.-M.Arnold. Regular and irregular progressive edge-growth tanner graphs[J]. IEEE Trans.Inform.Theory,2005,51(1):386–398.
    [16] H. Xiao and A. H. Banihashemi. Improved progressive–edge–growth (PEG)construction of irregular LDPC codes[J]. IEEE Commun. Lett.,2004,8(12):715–717.
    [17] C.T. Healy, R.C. de Lamare. Decoder-Optimised Progressive Edge GrowthAlgorithms for the Design of LDPC Codes with Low Error Floors[J].Communications Letters, IEEE,2012,16(6):889-892.
    [18] Y.Kou, S.Lin, and M.P.C.Fossorier. Low-density parity-check codes based onfinite geometries: A rediscovery and new results[C]. IEEE Trans. Inform. Theory,2001,47(7):2711–2736.
    [19] I.Djurdjevic, J.Xu, K.Abdel-Ghaffar,and S.Lin. A class of low-densityparity-check codes constructed based on Reed-Solomon codes with twoinformation symbols[J]. IEEE Commun.Lett.,2003,7(7):317–319.
    [20] B.Ammar, B.Honary, Y.Kou, J.Xu, and S.Lin. Construction of low-density paritycheck codes based on balanced incomplete block designs[J]. IEEE Trans. Inform.Theory,2004,50(6):1257–1269.
    [21] B. Vasic and O. Milenkovic. Combinatorial constructions of low-density parity-check codes for iterative decoding[J]. IEEE Trans. Inform. Theory,2004,50(6):1156–1176.
    [22] Z. W. Li, L. Chen, L. Q. Zeng, S. Lin, and W. H. Fong. Efficient encoding ofquasi-cyclic low-density parity-check codes[J]. IEEE Trans. Commun.,2006,54(1):71–81.
    [23] J. Garcia-Frias, Wei Zhong. Approaching Shannon performance by iterativedecoding of linear codes with low-density generator matrix[J]. CommunicationsLetters, IEEE,2003,7(6):266,268.
    [24] M.J. Wainwright, E. Martinian. Low-Density Graph Codes That Are Optimal forBinning and Coding With Side Information[J]. Information Theory, IEEETransactions on,2009,55(3):1061-1079
    [25] He Zhiyong, P. Fortier, S. Roy. A class of irregular LDPC codes with low errorfloor and low encoding complexity[J]. Communications Letters, IEEE,2006,10(5):372-374.
    [26] W.M.Tam, Lau, F. C M; Tse, C.K., A class of QC-LDPC codes with low encodingcomplexity and good error performance[J]. Communications Letters, IEEE,2010,14(2):169-171.
    [27] M. Fossorier, M. Mihaljevic, and H. Imai. Reduced complexity iterative decodingof low density parity check codes based on belief propagation[J]. IEEE TransCommun,1999,47:673-680.
    [28] Wu Xiaofu, Song Yue, Jiang Ming, Zhao Chunming. Adaptive-Normalized/OffsetMin-Sum Algorithm[J]. Communications Letters, IEEE,2010,14(7):667-669.
    [29] M. Ramezani, R. Yazdani, M. Ardakani. Stability analysis of an improvedmin-sum decoder[J]. Communications Letters, IEEE,2008,12(8):581-583.
    [30] J. Zhang, M. Fossorier, D. Gu, Zhang J. Two-dimensional correction for min-sumdecoding of irregular LDPC codes[J]. Communications Letters, IEEE,2006,10(3):180-182.
    [31] Zhao Jianguang, F. Zarkeshvari, A.H. Banihashemi. On implementation of min-sum algorithm and its modifications for decoding low-density Parity-check (LDPC)codes[J]. Communications, IEEE Transactions on,2005,53(4):549-554.
    [32] V.K.K. Srinivasan, C.K. Singh, P.T. Balsara. A Generic Scalable Architecture forMin-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder[J]. VeryLarge Scale Integration (VLSI) Systems, IEEE Transactions on,2010,18(9):1372-1376.
    [33] Jinghu Chen, Ajay Dholakia, Evangelos Eleftheriou, Marc P. C. Fossorier andXiao-Yu Hu. Reduced-Complexity Decoding of LDPC Codes[J]. IEEE TransCommun,2005,53(8).
    [34] Zhang J and M.P.C. Fossorier. A modified weighted bit-flipping decoding of lowdensity parity-check codes [J]. IEEE Commun. Lett.,2004,8(3):165–167.
    [35] Jiang M, Zhao C, Shi Z and Chen Y. An improvement on the modified weightedbit flipping decoding algorithm for LDPC codes [J], IEEE CommunicationsLetters,2005,9(9):814–816.
    [36] X. Wu, C. Zhao and X. You. Parallel weighted bit-flipping decoding[J]. IEEECommun. Lett.,2007,11:671–673.
    [37] X. Wu, C. Ling, M. Jiang, E. Xu, C. Zhao and X. You. New insights into weightedbit-flipping decoding[J]. IEEE Commun. Lett.,2009,57:2177-2180.
    [38] Liu Z and D.A. Pados. A decoding algorithm for finite-geometry LDPC codes[J],Communications, IEEE Transactions on,2005,53(3):415-421.
    [39] T.M.N. Ngatched, F. Takawira and M. Bossert, An improved decoding algorithmfor finite-geometry LDPC codes[J]. Communications, IEEE Transactions on,2009,57(2):302-306.
    [40] F. Guo, L. Hanzo. Reliability ratio based weighted bit-flipping decoding forlow-density parity-check codes [J]. Electronic Letters,2004,40(21):1356–1358.
    [41] Lee, C. H., and W. Wolf, Implementation-efficient reliability ratio based weightedbit-flipping decoding for LDPC codes [J]. Electronic Letters,2005,41:1356–1358.
    [42] Lan Lan, Lingqi Zeng, Ying Y. Tai. Construction of Quasi-Cyclic LDPC Codes forAWGN and Binary Erasure Channels: A Finite Field Approach[J]. IEEE Trans.Inform. Theory,2007,3(7).
    [43] Richarddson T, Urbranke R. Efficient encoding of low-density parity-checkcodes[J]. IEEE Trans. Inform. Theory,2001,47(2):638-656
    [44] Li Zongwang, Chen Lei, Zeng Lingqi, et al. Efficient Encoding of Quasi-CyclicLow-Density Parity-Check Codes[J]. IEEE Trans. on Communications,2006,54(1):71-81
    [45] C. Yoon, E. Choi, M. Cheong, and S.-K. Lee. Arbitrary bit generation andcorrection technique for encoding QC-LDPC codes with dual diagonal paritystructure[C]. IEEE Wireless Communications and Networking Conference,(WCNC2007),2007,662-666.
    [46] C. Yoon, J.-E. Oh, M. Cheong, and S.-K. Lee. A hardware efficient LDPCencoding scheme for exploiting decoder structure and resources[C]. IEEEVehicular Technology Conference (VTC2007-Spring),2007,2445-2449.
    [47] Chia-Yu Lin, Chih-Chun Wei, and Mong-Kai Ku. Efficient Encoding for Dual-Diagonal Structured LDPC Codes Based on Parity Bit Prediction and Correction[C]. APCCAS2008. IEEE Asia Pacific Conference on Circuits and Systems.
    [48] IEEE Standard for Local and metropolitan area networks Part16: Air Interface forBroadband Wireless Access Systems
    [49] Z Chen, X Zhao, X Peng, D Zhou. An early stopping criterion for decoding LDPCcodes in WiMAX and WiFi standards[C]. Proceedings of2010IEEE InternationalSymposium on Circuits and Systems (ISCAS).
    [50]温娜,张平.一种LDPC码的译码停止准则[J].电子技术应用.2007年3期.
    [51]刘东华.Turbo码原理与应用技术,北京:电子工业出版社,2004.
    [52] Beomkyu Shin; Sang-Hyo Kim; Jong-Seon No; Dong-Joon Shin, New stoppingcriteria for decoding LDPC codes in H-ARQ systems[C]. Information Theory andIts Applications,2008. ISITA2008. International Symposium on,2008,1(5):7-10.
    [53] Chin-Long Wey, Ming-Der Shieh and Shin-Yo Lin. Algorithms of Finding theFirst Two Minimum Values and Their Hardware Implementation[J], Circuits andSystems I: Regular Papers, IEEE Transactions on,2008,55(11):3430-3437.
    [54] B.D. Bingham and M.R. Greenstreet. Modeling Energy-Time Trade-Offs in VLSIComputation[J], Computers, IEEE Transactions on,2012,61(4):530-547.
    [55] A.A. Colavita, A. Cicuttin, F. Fratnik, et al.. SORTCHIP: a VLSI implementationof a hardware algorithm for continuous data sorting[J], Solid-State Circuits, IEEEJournal of,2003,38,(6):1076-1079.
    [56] A. Greb, G. Zachmann. GPU-ABiSort: optimal parallel sorting on streamarchitectures[C]. Parallel and Distributed Processing Symposium,2006. IPDPS2006.20th International,2006,25-29.
    [57] Shengnan Dong; Xiaotao Wang; Xingbo Wang, A Novel High-Speed ParallelScheme for Data Sorting Algorithm Based on FPGA[C]. Image and SignalProcessing,2009. CISP '09.2nd International Congress on,2009,1(4):17-19.
    [58] IEEE P802.11n/D2.00, Draft standard for local and metropolitan area networks,specific requirements Part11:Wireless LAN Medium Access Control(MAC)andPhysical Layer(PHY) specifications: enhancements for higher throughput[S],2007.
    [59] Xie Qian, Chen Zhixiang, Peng Xiao, et al.. A sorting-based architecture of findingthe first two minimum values for LDPC decoding[A], Signal Processing and itsApplications (CSPA),2011IEEE7th International Colloquium on,2011,95-98.
    [60] Wang Zhongfeng, Cui Zhiqiang. A Memory Efficient Partially Parallel DecoderArchitecture for Quasi-Cyclic LDPC Codes[J], Very Large Scale Integration(VLSI) Systems, IEEE Transactions on,2007,15(4):483-488.
    [61] Chien, Y.–H, M.-K Ku, J.-B Liu. Low-complexity iteration control algorithm formulti-rate partially parallel layered LDPC decoders[J]. Electronics Letters,2012,48(22):1406-1407.
    [62] Seok-Min Kim, Chang-Soo Park, Sun-Young Hwang, A novel partially parallelarchitecture for high-throughput LDPC Decoder for DVB-S2[J]. ConsumerElectronics, IEEE Transactions on,2010,56(2):820-825.
    [63] Jie Jin, Chi-Ying Tsui. Improving the hardware utilization efficiency of partiallyparallel LDPC decoder with scheduling and sub-matrix decomposition[C]. Circuitsand Systems,2009. ISCAS2009. IEEE International Symposium on,2009,24(27):2233-2236.
    [64] R. Asvadi, A.H. Banihashemi, M. Ahmadian-Attari. Design of Finite-LengthIrregular Protograph Codes with Low Error Floors over the Binary-Input AWGNChannel Using Cyclic Liftings [J]. Communications, IEEE Transactions on,2012,60(4):902-907.
    [65] Kyung-Joong Kim, Jin-Ho Chung, Kyeongcheol Yang. Design of Length-Compatible Low-Density Parity-Check Codes [J]. Communications Letters, IEEE,2012,16(5):734-737.
    [66] Ivan B.Djordjevic. Spatial-Domain-Based Hybrid Multidimensional Coded-Modulation Schemes Enabling Multi-Tb/s Optical Transport*[J]. LightwaveTechnology, Journal of,2012,30(24):3888-3901.
    [67] Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, et al.. A5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE802.15.3c Applications [J].Solid-State Circuits, IEEE Journal of,2012,47(9):2246-2257.
    [68] Wu, Tsung-Che, Yao-Wen Hu, Lee, Chang-Ming. Optimization of memoryutilization for partially parallel QC-LDPC decoder[C]. Information Theory and itsApplications (ISITA),2010International Symposium on,2010,17(20):496-500.
    [69] Zhu Yuming, C. Chakrabarti. Memory Efficient LDPC Code Design for HighThroughput Software Defined Radio (SDR) systems[C]. Acoustics, Speech andSignal Processing,2007. ICASSP2007. IEEE International Conference on,2007,2:15-20.
    [70] Chen Xiaoheng Kang Jingyu, Lin Shu, V. Akella. Memory System Optimizationfor FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders[J].Circuits and Systems I: Regular Papers, IEEE Transactions on,2011,58(1):98-111.
    [71] Smith B P, Kschischang F R. Future Prospects for FEC in Fiber-OpticCommunications [J].Selected Topics in Quantum Electronics, Journal of IEEE,2010,16(5):1245-1257.
    [72] ITU-T Rec.G.975.1, Forward Error Correction for High Bit-Rate DWDMSubmarine Systems [S].
    [73] Guo, F., Hanzo, L., Reliability ratio based weighted bit-flipping decoding forlow-density parity-check codes [J]. Electronic Letters,2004,40(21):1356–1358,.
    [74] Lee, C. H., and W. Wolf, Implementation-efficient reliability ratio based weightedbit-flipping decoding for LDPC codes [J]. Electronic Letters,2005,41:1356–1358.
    [75] Tiwari, H.D., Huynh Ngoc Bao, Yong Beom Cho, A Parallel IRRWBF LDPCDecoder Based on Stream-Based Processor [J].IEEE Transactions on Parallel andDistributed Systems,2012,23(12):2198-2204.
    [76] Cho Junho, Sung Wonyong. Adaptive Threshold Technique for Bit-FlippingDecoding of Low-Density Parity-Check Codes [J].IEEE Communications Letters,2010,14(9):857-859.
    [77] Tso-Cho Chen. An early stopping criterion for LDPC decoding based on averageweighted reliability measure [C]. Cross Strait Quad-Regional Radio Science andWireless Technology Conference (CSQRWC),2012:123-126.
    [78] D.J. MacKay, Online database of low-density parity check codes [OL].http://www.inference.phy. cam.ac.uk/mackay/codes/data.html,2013-1-28.
    [79] R. Asvadi, A.H. Banihashemi, M. Ahmadian-Attari. Design of Finite-LengthIrregular Protograph Codes with Low Error Floors over the Binary-Input AWGNChannel Using Cyclic Liftings [J]. Communications, IEEE Transactions on,2012,60(4):902-907.
    [80] Kyung-Joong Kim, Jin-Ho Chung, Kyeongcheol Yang. Design of Length-Compatible Low-Density Parity-Check Codes [J]. Communications Letters, IEEE,2012,16(5):734-737.
    [81] H.D. Tiwari, Huynh Ngoc Bao, Yong Beom Cho. Flexible LDPC decoder usingstream data processing for802.11n and802.16e[J]. Consumer Electronics, IEEETransactions on,2011,57(4):1505-1512.
    [82] Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, et al.. A5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE802.15.3c Applications [J].Solid-State Circuits, IEEE Journal of,2012,47(9):2246-2257.
    [83] Hong-Fu Chou, Yeong-Luh Ueng, Mao-Chao Lin, et al. An RLL-ConstrainedLDPC Coded Recording System Using Deliberate Flipping and Flipped-BitDetection[J]. Communications, IEEE Transactions on,2012,60(12):3587-3596.
    [84] Gwang-Hyun Gho, Kahn, J.M. Rate-adaptive modulation and low-densityparity-check coding for optical fiber transmission systems[J]. OpticalCommunications and Networking, IEEE/OSA Journal of,2012,4(10):760-768.
    [85] R. Asvadi, A.H. Banihashemi, M. Ahmadian-Attari. Design of Finite-LengthIrregular Protograph Codes with Low Error Floors over the Binary-Input AWGNChannel Using Cyclic Liftings[J]. Communications, IEEE Transactions on,2012,60(4):902-907.
    [86] S. Laendner, T. Hehn, O. Milenkovic, J.B. Huber. The Trapping Redundancy ofLinear Block Codes [J]. IEEE Transactions on Information Theory,2009,55(1):53-63.
    [87] Wang Chih-Chun, S.R. Kulkarni, H.V. Poor. Finding All Small Error-ProneSubstructures in LDPC Codes [J]. IEEE Transactions on Information Theory,2009,55(5):1976-1999.
    [88] M. Karimi, A.H. Banihashemi. Efficient Algorithm for Finding Dominant TrappingSets of LDPC Codes[J]. Information Theory, IEEE Transactions on,2012,58(11):6942-6958.
    [89] Qin Huang, Qiuju Diao, Shu Lin, K. Abdel-Ghaffar. Cyclic and Quasi-CyclicLDPC Codes on Constrained Parity-Check Matrices and Their Trapping Sets[J].Information Theory, IEEE Transactions on,2012,58(5):2648-2671.
    [90] S.K. Chilappagari, D.V. Nguyen, B. Vasic, M.W. Marcellin. On Trapping Sets andGuaranteed Error Correction Capability of LDPC Codes and GLDPC Codes[J].Information Theory, IEEE Transactions on,2010,56(4):1600-1611.
    [91] Saejoon Kim. Trapping Set Error Correction through Adaptive Informed DynamicScheduling Decoding of LDPC Codes[J]. Communications Letters, IEEE,2012,16(7):1103-1105.
    [92] Zhang Z, L. Dolecek, B. Nikolic, et al. Lowering LDPC Error Floors byPostprocessing [C]. Global Telecommunications Conference,2008:1-6.
    [93] Han Yang, W. Ryan. Low-floor decoders for LDPC codes[J]. IEEE Trans.Commun.,2009,57(6):1663-1673.
    [94] Kang J, Huang Q, Lin S, K. Abdel-Ghaffar. An Iterative Decoding Algorithm withBacktracking to Lower the Error-Floors of LDPC Codes [J]. IEEE Transactions onCommunications,2011,59(1):64-73.
    [95] S. Gounai, T. Ohtsuki. Decoding algorithms based on oscillation for low-densityparity check codes[J]. IEICE Trans. Fundam.,2005, E88-A:2216-2226.
    [96] Han Yang, W.E. Ryan, LDPC decoder strategies for achieving low error floors [C].Information Theory and Applications Workshop,2008:277-286.
    [97] Ma Kexiang, Li Yongzhao, Zhang Hailin. A Fast Weighted Bit Flipping Algorithmfor Higher-Speed Decoding of LDPC Codes[J]. China Communications,2013.
    [98] Lin S, J Daniel. Error Control Coding: Fundamentals and Applications [M].2ndedition. Prentice-Hall: Upper Saddle River, NJ,2004.
    [99] Diao Q, Zhou W,Lin S. A transform approach for constructing quasi-cyclicEuclidean geometry LDPC codes [J]. Information Theory and ApplicationsWorkshop (ITA),2012, vol., no., pp.204-211,5-10Feb.2012.
    [100] D. E. Knuth, The Art of Computer Programming,2nd ed[M]. New York:Addison-Wesley,1998.
    [101] Zhang Z, Anantharam V, M J Wainwright. An Efficient10GBASE-T EthernetLDPC Decoder Design With Low Error Floors [J].Solid-State Circuits, IEEEJournal of,2010,45(4):843-855.

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