基于边界扫描技术的测试系统的研究与应用
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摘要
边界扫描技术作为一种标准的数字电路测试及可测试性设计方法,它以特有的结构和检测方法克服了复杂数字电路板测试的技术障碍,能大大提高数字电路的可测试性。随着边界扫描芯片在电子设备中的大量应用,开发出实用的边界扫描测试系统,对于提高设备的可测试性、降低维护费用具有重要意义。
论文的主要工作是在对边界扫描技术进行深入研究的基础上,设计并实现了基于边界扫描技术的通用测试系统,并将该系统应用到数字电路的故障诊断中。论文首先简述了边界扫描技术的IEEE1149.1标准及其在板级测试中的一些应用,并在此基础上给出了边界扫描测试系统的功能需求和设计方案。然后详细介绍了边界扫描测试卡的设计和边界扫描测试软件的开发。测试卡采用CY7C68013作为USB接口芯片,选择GPIF主控模式实现速度达20MB/s的数据传输接口;采用FPGA实现边界扫描控制器,为测试系统提供最高可达24MHz的可调测试时钟及两条扫描链路。测试软件在Visual C++ 6.0环境下使用面向对象和Access数据库技术开发,可以根据测试算法自动生成测试向量,并完成对数字系统的测试和故障诊断,界面友好,操作方便。最后,使用边界扫描测试系统对一块完成可测性设计的电路板进行了完备性测试、互连测试和簇测试。
调试结果表明,边界扫描测试系统符合设计要求,具有测试速度快、即插即用、连接简单可靠等优点。在实际应用中,测试系统能够对电路板的呆滞、开路和短路故障进行有效的检测和诊断,达到了预期的效果。
With the development of intergrated circuit, it is difficult to test the complicated circuit quickly and efficaciously based on traditional test method. As a standard technique of test and Design-For-Testability for the circuit boards, Boundary-Scan technique can improve the testability and controllability of complex digital circuits effectively by means of embedding special boundary scan cells inside the circuits. As widely application of boundary scan chips, it is very important to develop a Boundary-Scan test system in order to enhance the testability, reduce the maintenance costs of the electronic equipment.
In this thesis, the Boundary Scan technique is discussed in detail and a general test system based on BST is also developed. Firstly, a primary conception on BST standard IEEE 1149.1 and some applications about BST in board test was introduced. As to be groundwork, the functional requairement and design scheme is provided. Then the thesis gives a detailed introduction to the design of boundary scan test card and the development of test software. The test card builds an interface with data rate of 20Mbytes/s using CY7C68013 as USB chip.The chip works in GPIF master mode. Its boundary scan test controller implemented by FPGA provides test clock reach 24MHz and two test channels. With the application of OOP and Access database under Visual C++ 6.0, the test software can auto-generate test vector by test algorithm. This software with friendly interface is convenient to be used. Finally, the control circuit board for fault wave recorder is designed based on DFT and tested by the system.
After tested, the test system meets the design demand and has some advantages such as high test rate, plug and play, easy connection, and so on. In application, the test system can test stuck-at faults, open faults and short faults on board, and achieves the anticipated target.
论文的主要工作是在对边界扫描技术进行深入研究的基础上,设计并实现了基于边界扫描技术的通用测试系统,并将该系统应用到数字电路的故障诊断中。论文首先简述了边界扫描技术的IEEE1149.1标准及其在板级测试中的一些应用,并在此基础上给出了边界扫描测试系统的功能需求和设计方案。然后详细介绍了边界扫描测试卡的设计和边界扫描测试软件的开发。测试卡采用CY7C68013作为USB接口芯片,选择GPIF主控模式实现速度达20MB/s的数据传输接口;采用FPGA实现边界扫描控制器,为测试系统提供最高可达24MHz的可调测试时钟及两条扫描链路。测试软件在Visual C++ 6.0环境下使用面向对象和Access数据库技术开发,可以根据测试算法自动生成测试向量,并完成对数字系统的测试和故障诊断,界面友好,操作方便。最后,使用边界扫描测试系统对一块完成可测性设计的电路板进行了完备性测试、互连测试和簇测试。
调试结果表明,边界扫描测试系统符合设计要求,具有测试速度快、即插即用、连接简单可靠等优点。在实际应用中,测试系统能够对电路板的呆滞、开路和短路故障进行有效的检测和诊断,达到了预期的效果。
With the development of intergrated circuit, it is difficult to test the complicated circuit quickly and efficaciously based on traditional test method. As a standard technique of test and Design-For-Testability for the circuit boards, Boundary-Scan technique can improve the testability and controllability of complex digital circuits effectively by means of embedding special boundary scan cells inside the circuits. As widely application of boundary scan chips, it is very important to develop a Boundary-Scan test system in order to enhance the testability, reduce the maintenance costs of the electronic equipment.
In this thesis, the Boundary Scan technique is discussed in detail and a general test system based on BST is also developed. Firstly, a primary conception on BST standard IEEE 1149.1 and some applications about BST in board test was introduced. As to be groundwork, the functional requairement and design scheme is provided. Then the thesis gives a detailed introduction to the design of boundary scan test card and the development of test software. The test card builds an interface with data rate of 20Mbytes/s using CY7C68013 as USB chip.The chip works in GPIF master mode. Its boundary scan test controller implemented by FPGA provides test clock reach 24MHz and two test channels. With the application of OOP and Access database under Visual C++ 6.0, the test software can auto-generate test vector by test algorithm. This software with friendly interface is convenient to be used. Finally, the control circuit board for fault wave recorder is designed based on DFT and tested by the system.
After tested, the test system meets the design demand and has some advantages such as high test rate, plug and play, easy connection, and so on. In application, the test system can test stuck-at faults, open faults and short faults on board, and achieves the anticipated target.
引文
[1]陈光禹、潘中良,可测性设计技术,北京,电子工业出版社,1997:1~6
[2] Kenneth P,Observation on the 1149.x family of standards,International Test Conference,1994
[3]温熙森、刘冠军、黎琼炜,基于边界扫描的板级BIT技术研究现状及发展趋势,国外计测,1999,19(3):38~41
[4] IEEE Std 1149.1,IEEE Standard Test Access Port and Boundary-Scan Architecture,IEEE Computer Society,2001
[5] IEEE Std 1149.5,IEEE Standard for Module Test and Maintenance Bus(MTM-Bus) protocol,IEEE Computer Society,1995,8
[6] IEEE Std 1149.4,IEEE Standard for a Mixed-Singnal Test Bus,IEEE Computer Society,1999,6
[7] IEEE Std 1149.6TM,IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks,IEEE Computer Society,2003,7
[8] IEEE Std 1149.1(JTAG)Testability Primer,Texas Instrument,1997
[9] IEEE 1149.1(JTAG)Boundary-Scan Testing in Altera Devices,Altera Corporation,2004,7
[10] Stephen Harrison、Peter Collins、Greg Noeninckx,The Implementation of IEEE Std 1149.1 Boundary Scan Test Strategy winthin a Cellular Infrastructure Production Environment,ITC INTERNATIONAL TEST CONFERENCE,2000:45~54
[11]胡政,边界扫描测试理论与方法研究,[博士学位论文],长沙,国防科技大学,1998
[12]牛春平,同时具备W-0和W-1对角独立性的多故障测试生成算法,微电子学与计算机,2005,22(1):54~57
[13]尚玉玲、颜学龙、雷加,遗传算法的板级边界扫描测试矢量优化及应用,计算机工程与应用,2004,20:205~207
[14] Najmi Jarwala、Chi W. Yau, A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects,International Test Conference,1989:63~70
[15] Wen Yi Feng、Fred J. Meyer、Fabrizio Lombardi,Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects,IEEE Transactions on Computer,2003,52(10):1259~1270
[16] Y. Zorian,Preliminary Outline of IEEE P1500 Scalable Architecture for Testing Embedded Cores,New York,IEEE Computer Society,1999
[17]游方,边界扫描测试仪系统软件研究与开发,[硕士学位论文],长沙,国防科技大学,1999
[18]张华,基于微机的边界扫描测试仪器的设计与实现,[硕士学位论文],武汉,华中科技大学,2002
[19]谭细金,基于LASAR和边界扫描的故障诊断系统设计,[硕士学位论文],成都,电子科技大学,2004
[20]雷绍充、邵志标、梁峰,VLSI测试方法学和可测性设计,北京,电子工业出版社,2005:146~179
[21]杨士元,数字系统的故障诊断与可靠性设计,北京,清华大学出版社,2000:195~214
[22]王宁、李桂祥、张尊泉,边界扫描器件BSDL描述在测试中的应用,半导体技术,2003,28(10):42~45
[23] Ajmi.Jarwala、Chi.W.Yau,Achieving Board-Level BIST Using the Boundary-Scan Master,International Test Conference,1991:649~657
[24] Robert.W. Bar、Chen-Huan Chiang、Edward.L.Wallace,End-to-End for Boards and Systems Using Boundary Scan,ITC International Test Conference,IEEE,2000:585~592
[25] Frans de Jong,Boundary Scan Used at Board Level,IEEE International Test Conference,1990:235~241
[26]王宁、李桂祥、杨江平,边界扫描测试结构完备性诊断策略,半导体技术,2003,28(9):22~24
[27]王孜、刘洪民、吴德馨,边界扫描测试技术,半导体技术,2002,30(9):17~29
[28] Hansen P,Testing Conventional Logic and Memory Cluster using BoundaryScan Devices as Virtual ATE Channels,Proc.of Intl,Test Conf.,1989:200~209
[29] Yongjoon Kim、Hyun-don Kim、Sungho Kang,A New Maximal DiagnosisAlgorithm for Interconnect Test,IEEE,2004:532~537
[30] P. Goel、M.T.McMahon,Electornic Chip In-place Test, International Test Conference, 1982:83~90
[31] P .T .Wagner,Interconnect:Testing with Boundary Scan,International Test Conference,1987:52~57
[32] A. Hassan、J Rajski、V. K.Agarwal,Testing and Diagnosis of Interconnects using Boundary Scan Architecture,International Test Conference,1988:126~137
[33] Asset-interTech, Inc.,Serial vector format specification,www.asset-intertech.com/support/
[34] Cypress,EZ-USB FX2 Manual Technical Reference,2001
[35] Texas Instruments,PowerPAD Thermally Enhanced Package,1997,11
[36] Altera Corporation,Serial Configuration Devices (EPCS1 & EPCS4),2003,3
[37] Maxim,Max3378 Data Sheet,2003
[38]钱峰,EZ-USB FX2单片机原理、编程及应用,北京,北京航空航天大学出版社,2006:171~340
[39] Ben Bennetts,Guidelines for Board DFT Based on Boundary Scan,ASSET InterTech,2002
[40] David Bell、Scott Chen,TMS320C6000:Board Design for JTAG,Texas Instrument Application Report,2002
[41]刘明云、李桂祥、张贤志,基于边界扫描的板级动态扫描链路设计策略,现代雷达,2005,27(1):66~70
[42]虞皆侠,基于嵌入式TCP/IP协议栈的电力录波主控系统的研制,[硕士学位论文],南京,南京航空航天大学,2007
[43]夏宇闻,Verilog数字系统设计教程,北京,北京航空航天大学出版社,2003:129~145。
[44] J.F.Wakerly,数字设计原理与实践(林生,金京林,葛红等译),北京,机械工业出版社,2003:611~636
[45]王诚、吴继华、范丽珍,Altera FPGA/CPLD设计(基础篇),北京,人民邮电出版社,2005:117~138
[46]刘韬、楼兴华,FPGA数字电子系统设计与开发实例导航,北京,人民邮电出版社, 2005:51~83
[2] Kenneth P,Observation on the 1149.x family of standards,International Test Conference,1994
[3]温熙森、刘冠军、黎琼炜,基于边界扫描的板级BIT技术研究现状及发展趋势,国外计测,1999,19(3):38~41
[4] IEEE Std 1149.1,IEEE Standard Test Access Port and Boundary-Scan Architecture,IEEE Computer Society,2001
[5] IEEE Std 1149.5,IEEE Standard for Module Test and Maintenance Bus(MTM-Bus) protocol,IEEE Computer Society,1995,8
[6] IEEE Std 1149.4,IEEE Standard for a Mixed-Singnal Test Bus,IEEE Computer Society,1999,6
[7] IEEE Std 1149.6TM,IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks,IEEE Computer Society,2003,7
[8] IEEE Std 1149.1(JTAG)Testability Primer,Texas Instrument,1997
[9] IEEE 1149.1(JTAG)Boundary-Scan Testing in Altera Devices,Altera Corporation,2004,7
[10] Stephen Harrison、Peter Collins、Greg Noeninckx,The Implementation of IEEE Std 1149.1 Boundary Scan Test Strategy winthin a Cellular Infrastructure Production Environment,ITC INTERNATIONAL TEST CONFERENCE,2000:45~54
[11]胡政,边界扫描测试理论与方法研究,[博士学位论文],长沙,国防科技大学,1998
[12]牛春平,同时具备W-0和W-1对角独立性的多故障测试生成算法,微电子学与计算机,2005,22(1):54~57
[13]尚玉玲、颜学龙、雷加,遗传算法的板级边界扫描测试矢量优化及应用,计算机工程与应用,2004,20:205~207
[14] Najmi Jarwala、Chi W. Yau, A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects,International Test Conference,1989:63~70
[15] Wen Yi Feng、Fred J. Meyer、Fabrizio Lombardi,Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects,IEEE Transactions on Computer,2003,52(10):1259~1270
[16] Y. Zorian,Preliminary Outline of IEEE P1500 Scalable Architecture for Testing Embedded Cores,New York,IEEE Computer Society,1999
[17]游方,边界扫描测试仪系统软件研究与开发,[硕士学位论文],长沙,国防科技大学,1999
[18]张华,基于微机的边界扫描测试仪器的设计与实现,[硕士学位论文],武汉,华中科技大学,2002
[19]谭细金,基于LASAR和边界扫描的故障诊断系统设计,[硕士学位论文],成都,电子科技大学,2004
[20]雷绍充、邵志标、梁峰,VLSI测试方法学和可测性设计,北京,电子工业出版社,2005:146~179
[21]杨士元,数字系统的故障诊断与可靠性设计,北京,清华大学出版社,2000:195~214
[22]王宁、李桂祥、张尊泉,边界扫描器件BSDL描述在测试中的应用,半导体技术,2003,28(10):42~45
[23] Ajmi.Jarwala、Chi.W.Yau,Achieving Board-Level BIST Using the Boundary-Scan Master,International Test Conference,1991:649~657
[24] Robert.W. Bar、Chen-Huan Chiang、Edward.L.Wallace,End-to-End for Boards and Systems Using Boundary Scan,ITC International Test Conference,IEEE,2000:585~592
[25] Frans de Jong,Boundary Scan Used at Board Level,IEEE International Test Conference,1990:235~241
[26]王宁、李桂祥、杨江平,边界扫描测试结构完备性诊断策略,半导体技术,2003,28(9):22~24
[27]王孜、刘洪民、吴德馨,边界扫描测试技术,半导体技术,2002,30(9):17~29
[28] Hansen P,Testing Conventional Logic and Memory Cluster using BoundaryScan Devices as Virtual ATE Channels,Proc.of Intl,Test Conf.,1989:200~209
[29] Yongjoon Kim、Hyun-don Kim、Sungho Kang,A New Maximal DiagnosisAlgorithm for Interconnect Test,IEEE,2004:532~537
[30] P. Goel、M.T.McMahon,Electornic Chip In-place Test, International Test Conference, 1982:83~90
[31] P .T .Wagner,Interconnect:Testing with Boundary Scan,International Test Conference,1987:52~57
[32] A. Hassan、J Rajski、V. K.Agarwal,Testing and Diagnosis of Interconnects using Boundary Scan Architecture,International Test Conference,1988:126~137
[33] Asset-interTech, Inc.,Serial vector format specification,www.asset-intertech.com/support/
[34] Cypress,EZ-USB FX2 Manual Technical Reference,2001
[35] Texas Instruments,PowerPAD Thermally Enhanced Package,1997,11
[36] Altera Corporation,Serial Configuration Devices (EPCS1 & EPCS4),2003,3
[37] Maxim,Max3378 Data Sheet,2003
[38]钱峰,EZ-USB FX2单片机原理、编程及应用,北京,北京航空航天大学出版社,2006:171~340
[39] Ben Bennetts,Guidelines for Board DFT Based on Boundary Scan,ASSET InterTech,2002
[40] David Bell、Scott Chen,TMS320C6000:Board Design for JTAG,Texas Instrument Application Report,2002
[41]刘明云、李桂祥、张贤志,基于边界扫描的板级动态扫描链路设计策略,现代雷达,2005,27(1):66~70
[42]虞皆侠,基于嵌入式TCP/IP协议栈的电力录波主控系统的研制,[硕士学位论文],南京,南京航空航天大学,2007
[43]夏宇闻,Verilog数字系统设计教程,北京,北京航空航天大学出版社,2003:129~145。
[44] J.F.Wakerly,数字设计原理与实践(林生,金京林,葛红等译),北京,机械工业出版社,2003:611~636
[45]王诚、吴继华、范丽珍,Altera FPGA/CPLD设计(基础篇),北京,人民邮电出版社,2005:117~138
[46]刘韬、楼兴华,FPGA数字电子系统设计与开发实例导航,北京,人民邮电出版社, 2005:51~83
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