Σ-Δ小数频率合成器中关键模块的设计
摘要
本文基于3G通讯标准TD-SCDMA的要求,完成了Σ-Δ小数频率合成器中关键模块的设计,其中包括电路设计与仿真(采用Cadence公司的spectre),版图设计及验证(采用Cadence公司的virtuoso和Mentor公司的calibre)。该频率合成器的频率变化范围为1830MHz--1980MHz,参考时钟频率为19.68MHz。
设计中采用了自顶向下的设计方法,从系统级开始研究,逐步过渡到晶体管级的模块设计。首先,根据项目指标确定各模块的结构;其次,在确定了参数之后,对每个模块进行了详细的设计与模拟,包括鉴频鉴相器、电荷泵、环路滤波器和压控振荡器;根据模拟结果对参数进行优化;取得了满意的结果;然后,将各个模块同数字部分组合成为系统,采用UMC 0.13um RF CMOS工艺完成了版图的设计及验证工作。
本文重点设计了一款鉴频鉴相器,该鉴频鉴相器在传统鉴频鉴相器的基础上,将复位单元与延迟单元分开,这样为了消除死区在复位信号后加一延时τ而产生的输入信号的上升沿数据丢失现象将得以避免。进而不会输出错误信息,使环路速度提高。
本文还介绍了TD-SCDMA标准以及该标准对射频接收发机中本振信号设计提出的要求。
该频率合成器一旦实现,完全可以应用于TD-SCDMA基站和TD-SCDMA手机中,对即将到来的3G基站和手机中的频率合成器的设计具有一定的指导意义和参考价值。
The design ofΣ-Δmodulation Franctional-N Synthesizer is based on the requirement of TD-SCDMA. We complete the design and simulation of the circuit (with Cadence spectre), as well as the layout and verification of the circuit (with Cadence virtuoso and Mentor calibre). The frequency of this synthesizer turns from 1830MHz to 1980MHz. The reference frequency is 19.68MHz.
The design method of Top to Down is used, which is from the system level design ofΣ-Δmodulation Franctional-N Synthesizer to the transistor level design of each block. Firstly, the structures of each block are built according to the design requirement. Secondly, after each block’s specification is decided, detailed design and simulation of these blocks are completed including Phase Frequency Detector (PFD), Charge Pump, Loop Filter (LPF) and Voltage Controlled Oscillator (VCO), then the loop parameters are optimized, each block have obtained the design specifications. Thirdly, the circuit consisted with the digital part is achieved. Finally, layout and verification of the circuit are completed in UMC 0.13um RF CMOS process.
This paper is focused on the research of the PFD, the PFD is configured to separate the reset part and the delay part independently, the input signal edge data, which arrive during an added delay to remove dead-zone, are not lost and do not output the wrong information, resulting in faster locking property.
Then, the standard of TD-SCDMA is introduced in this paper, with its requirements to the design of RF Local Oscillator.
Once the design is accomplished, this frequency synthesizer can be applied to the TD-SCDMA base station and TD-SCDMA cell phone, and is instructive for the frequency synthesizer of the incoming 3G..
设计中采用了自顶向下的设计方法,从系统级开始研究,逐步过渡到晶体管级的模块设计。首先,根据项目指标确定各模块的结构;其次,在确定了参数之后,对每个模块进行了详细的设计与模拟,包括鉴频鉴相器、电荷泵、环路滤波器和压控振荡器;根据模拟结果对参数进行优化;取得了满意的结果;然后,将各个模块同数字部分组合成为系统,采用UMC 0.13um RF CMOS工艺完成了版图的设计及验证工作。
本文重点设计了一款鉴频鉴相器,该鉴频鉴相器在传统鉴频鉴相器的基础上,将复位单元与延迟单元分开,这样为了消除死区在复位信号后加一延时τ而产生的输入信号的上升沿数据丢失现象将得以避免。进而不会输出错误信息,使环路速度提高。
本文还介绍了TD-SCDMA标准以及该标准对射频接收发机中本振信号设计提出的要求。
该频率合成器一旦实现,完全可以应用于TD-SCDMA基站和TD-SCDMA手机中,对即将到来的3G基站和手机中的频率合成器的设计具有一定的指导意义和参考价值。
The design ofΣ-Δmodulation Franctional-N Synthesizer is based on the requirement of TD-SCDMA. We complete the design and simulation of the circuit (with Cadence spectre), as well as the layout and verification of the circuit (with Cadence virtuoso and Mentor calibre). The frequency of this synthesizer turns from 1830MHz to 1980MHz. The reference frequency is 19.68MHz.
The design method of Top to Down is used, which is from the system level design ofΣ-Δmodulation Franctional-N Synthesizer to the transistor level design of each block. Firstly, the structures of each block are built according to the design requirement. Secondly, after each block’s specification is decided, detailed design and simulation of these blocks are completed including Phase Frequency Detector (PFD), Charge Pump, Loop Filter (LPF) and Voltage Controlled Oscillator (VCO), then the loop parameters are optimized, each block have obtained the design specifications. Thirdly, the circuit consisted with the digital part is achieved. Finally, layout and verification of the circuit are completed in UMC 0.13um RF CMOS process.
This paper is focused on the research of the PFD, the PFD is configured to separate the reset part and the delay part independently, the input signal edge data, which arrive during an added delay to remove dead-zone, are not lost and do not output the wrong information, resulting in faster locking property.
Then, the standard of TD-SCDMA is introduced in this paper, with its requirements to the design of RF Local Oscillator.
Once the design is accomplished, this frequency synthesizer can be applied to the TD-SCDMA base station and TD-SCDMA cell phone, and is instructive for the frequency synthesizer of the incoming 3G..
引文
[1] 戴逸民,频率合成与锁相技术,中国科技大学出版社,1995
[2] R. E. Best, Phase-Locked Loops Design, Simulation, and Applications, The McGraw-Hill Companies, Inc. 2003
[3] B. D. Muer, M. Steyaert, CMOS Fractional-N Synthesizers, Kluwer Academic Publishers, Boston, 2003
[4] Hong Jo Ahn, A frequency synthesizer for multi-standard wireless applications, Ph. D., The Ohio University, 2003
[5] Chung-Yu Wu, Chih-Yuan Hsieh and Wei-Ming Chen, A 1-V 2.4-GHz CMOS frequency synthesizer with current-match charge pump, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9, 2004, pp433-436
[6] Mohamad El-Hage, Fei Yuan, Architectures and design considerations of CMOS charge pumps for phase-locked loops,IEEE Electrical and Computer Engineering,vol. 1, pp. 223 – 226,May 2003
[7] W. Rhee, Design of high performance CMOS charge pumps in phase locked loop, Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol.1, May 1999, pp545-548
[8] P. Larsson, A 2~1600-MHz CMOS clock recovery PLL with low Vdd capacity, IEEE J. Solid-State Circuits, vol.34, pp.1951-1960, Dec. 1999
[9] M. Johnson, E. Hudson, A variable delay line PLL for CPU processor synchronization, IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988
[10] A. Hadjizada, J. Fenk, E. Goetz, TV and TVSAT mixer-oscillator PLL ICs IEEE Trans. Consumer Electronics, vol. 41, pp. 942-945, Aug. 1995
[11] L. Lin, Design techniques for high performance integrated frequency synthesizers for multi-standard wireless communication applications , Ph.D. dissertation, University of California at Berkeley, CA, Dec. 2000
[12] J. Craninckx ,M. Steyaert, A fully integrated CMOS DCS-1800 frequency synthesizer, IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998
[13] Y. Koo, H. Huh, Y. Cho, A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual path loop filter for PCS- and cellular-CDMA wireless systems, IEEE J. Solid-State Circuits, vol. 37, pp. 536-542, May 2002
[14] T. Kan, G. Leung, H. Luong, 2-V, 1.8-GHz fully integrated CMOS dual-loop frequency synthesizer, IEEE J. Solid-State Circuits, vol. 37, pp. 1012-1020, Aug. 2002
[15] A. Maxim, B. Scott, E. Schneider, A low-jitter 125-1250-MHz process-independent and ripple-poleless CMOS PLL based on a sample-reset loop filter, IEEE J. Solid-State Circuits, vol. 36, pp. 1673-1683, Nov. 2001
[16] P. Larsson, An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5Gb/s optical communication, in Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 74-75, 434
[17] T. Lee and B. Razavi, A stabilization technique for phase-locked frequency synthesizer, in Proc. 2001 Symp. VLSI Circuits, Kyoto, Japan, June 2001, pp. 39-42
[18] M. Perrott, T. Tewksbury, G. Sodini, A 27-mW CMOS fractional-N frequency synthesizer using digital compensation for 2.5-Mb/s GFSK modulation, IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997
[19] D. R. McMahil , C. Sodini, A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated frequency synthesizer, IEEE J. Solid-State Circuits, vol. 37, pp. 18-26, Jan. 2002 Σ?Δ
[20] E. Vittoz, M. Degrauwe, S. Bitz, High-performance crystal oscillator: Theory and Application, IEEE J. Solid-State Circuits, vol. 23, no. 3, pp. 774-783, June 1988
[21] Q. Huang, Phase noise to carrier ratio in LC oscillators, IEEE Transactions on Circuits and Systems, vol. 47, no. 7, pp. 965-980, July 2000
[22] J.T. Santos , R. G.. Meyer, A one-pin crystal oscillator for VLSI circuits, IEEE J. Solid-State Circuits, vol. 19, no. 2, pp. 228-236, Apr. 1984
[23] B. Razavi, A study of phase noise in CMOS oscillators, IEEE J. Solid-State Circuits, vol. 31, no.3, pp. 331-343, Mar. 1996
[24] C. H. Park, B. Kim, A low-noise, 900MHz VCO in 0.6um CMOS, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 586-591, May. 1999
[25] R. Senani, B. A. Kumar, Linearly tunable Wien bridge oscillator realized with operation transconductance amplifiers, Electronics Letters, vol.25, no.1, pp.19-21, Jan. 1989
[26] Keliu Shu, A 2.4-GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase-Switching Prescaler and Loop Capacitance Multiplier, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866-874, June. 2003
[27] Ping Wah Wong, ROBERT M.GRAY, Two-Stage Sigma-Delta Modulation, IEEE Transactions on acoustics speech and signal processing, vol. 38, no. 11, Nov. 1990
[28] Kay Das, A Look at China’s TD-SCDMA and the European UTRA-FDD Standard for 3G, Asia Pacific STMicroelectronics
[29] Kun-Seok Lee, Byeong-Ha Park, Han-il Lee, Phase frequency detectors for fast frequency acquisition in zero-dead-zone CPPLLs for mobile communication systems, System-Lsi Division, Korea, pp. 525-528
[30] B. D. Muer, M. Steyaert, CMOS Fractional-N Synthesizers, Kluwer Academic Publishers, Boston, 2003
[31] J. Rogers, J. Macedo, C. Plett, The effect of varactor nonlinearity on the phase noise of completely integrated VCOs, IEEE J. Solid-State Circuits, vol. 35, pp. 1360-1367, Sept. 2000
[32] C. Lo, H. Luong, A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications, IEEE J. Solid-State Circuits, vol. 37, pp. 459-470, Apr. 2002
[33] K. O, Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies, IEEE J. Solid-State Circuits, vol. 33, pp. 1249-1252, Aug. 1998
[34] C. Saint, J. Saint, IC Mask Design—essential layout techniques, McGraw- Hill Education (Asia) Co. 2003
[2] R. E. Best, Phase-Locked Loops Design, Simulation, and Applications, The McGraw-Hill Companies, Inc. 2003
[3] B. D. Muer, M. Steyaert, CMOS Fractional-N Synthesizers, Kluwer Academic Publishers, Boston, 2003
[4] Hong Jo Ahn, A frequency synthesizer for multi-standard wireless applications, Ph. D., The Ohio University, 2003
[5] Chung-Yu Wu, Chih-Yuan Hsieh and Wei-Ming Chen, A 1-V 2.4-GHz CMOS frequency synthesizer with current-match charge pump, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9, 2004, pp433-436
[6] Mohamad El-Hage, Fei Yuan, Architectures and design considerations of CMOS charge pumps for phase-locked loops,IEEE Electrical and Computer Engineering,vol. 1, pp. 223 – 226,May 2003
[7] W. Rhee, Design of high performance CMOS charge pumps in phase locked loop, Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol.1, May 1999, pp545-548
[8] P. Larsson, A 2~1600-MHz CMOS clock recovery PLL with low Vdd capacity, IEEE J. Solid-State Circuits, vol.34, pp.1951-1960, Dec. 1999
[9] M. Johnson, E. Hudson, A variable delay line PLL for CPU processor synchronization, IEEE J. Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988
[10] A. Hadjizada, J. Fenk, E. Goetz, TV and TVSAT mixer-oscillator PLL ICs IEEE Trans. Consumer Electronics, vol. 41, pp. 942-945, Aug. 1995
[11] L. Lin, Design techniques for high performance integrated frequency synthesizers for multi-standard wireless communication applications , Ph.D. dissertation, University of California at Berkeley, CA, Dec. 2000
[12] J. Craninckx ,M. Steyaert, A fully integrated CMOS DCS-1800 frequency synthesizer, IEEE J. Solid-State Circuits, vol. 33, pp. 2054-2065, Dec. 1998
[13] Y. Koo, H. Huh, Y. Cho, A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual path loop filter for PCS- and cellular-CDMA wireless systems, IEEE J. Solid-State Circuits, vol. 37, pp. 536-542, May 2002
[14] T. Kan, G. Leung, H. Luong, 2-V, 1.8-GHz fully integrated CMOS dual-loop frequency synthesizer, IEEE J. Solid-State Circuits, vol. 37, pp. 1012-1020, Aug. 2002
[15] A. Maxim, B. Scott, E. Schneider, A low-jitter 125-1250-MHz process-independent and ripple-poleless CMOS PLL based on a sample-reset loop filter, IEEE J. Solid-State Circuits, vol. 36, pp. 1673-1683, Nov. 2001
[16] P. Larsson, An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5Gb/s optical communication, in Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2001, pp. 74-75, 434
[17] T. Lee and B. Razavi, A stabilization technique for phase-locked frequency synthesizer, in Proc. 2001 Symp. VLSI Circuits, Kyoto, Japan, June 2001, pp. 39-42
[18] M. Perrott, T. Tewksbury, G. Sodini, A 27-mW CMOS fractional-N frequency synthesizer using digital compensation for 2.5-Mb/s GFSK modulation, IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997
[19] D. R. McMahil , C. Sodini, A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated frequency synthesizer, IEEE J. Solid-State Circuits, vol. 37, pp. 18-26, Jan. 2002 Σ?Δ
[20] E. Vittoz, M. Degrauwe, S. Bitz, High-performance crystal oscillator: Theory and Application, IEEE J. Solid-State Circuits, vol. 23, no. 3, pp. 774-783, June 1988
[21] Q. Huang, Phase noise to carrier ratio in LC oscillators, IEEE Transactions on Circuits and Systems, vol. 47, no. 7, pp. 965-980, July 2000
[22] J.T. Santos , R. G.. Meyer, A one-pin crystal oscillator for VLSI circuits, IEEE J. Solid-State Circuits, vol. 19, no. 2, pp. 228-236, Apr. 1984
[23] B. Razavi, A study of phase noise in CMOS oscillators, IEEE J. Solid-State Circuits, vol. 31, no.3, pp. 331-343, Mar. 1996
[24] C. H. Park, B. Kim, A low-noise, 900MHz VCO in 0.6um CMOS, IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 586-591, May. 1999
[25] R. Senani, B. A. Kumar, Linearly tunable Wien bridge oscillator realized with operation transconductance amplifiers, Electronics Letters, vol.25, no.1, pp.19-21, Jan. 1989
[26] Keliu Shu, A 2.4-GHz Monolithic Fractional-N Frequency Synthesizer With Robust Phase-Switching Prescaler and Loop Capacitance Multiplier, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866-874, June. 2003
[27] Ping Wah Wong, ROBERT M.GRAY, Two-Stage Sigma-Delta Modulation, IEEE Transactions on acoustics speech and signal processing, vol. 38, no. 11, Nov. 1990
[28] Kay Das, A Look at China’s TD-SCDMA and the European UTRA-FDD Standard for 3G, Asia Pacific STMicroelectronics
[29] Kun-Seok Lee, Byeong-Ha Park, Han-il Lee, Phase frequency detectors for fast frequency acquisition in zero-dead-zone CPPLLs for mobile communication systems, System-Lsi Division, Korea, pp. 525-528
[30] B. D. Muer, M. Steyaert, CMOS Fractional-N Synthesizers, Kluwer Academic Publishers, Boston, 2003
[31] J. Rogers, J. Macedo, C. Plett, The effect of varactor nonlinearity on the phase noise of completely integrated VCOs, IEEE J. Solid-State Circuits, vol. 35, pp. 1360-1367, Sept. 2000
[32] C. Lo, H. Luong, A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications, IEEE J. Solid-State Circuits, vol. 37, pp. 459-470, Apr. 2002
[33] K. O, Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies, IEEE J. Solid-State Circuits, vol. 33, pp. 1249-1252, Aug. 1998
[34] C. Saint, J. Saint, IC Mask Design—essential layout techniques, McGraw- Hill Education (Asia) Co. 2003