基于ZYNQ的千兆以太网接口读出模块ZYNQBee的研制
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- 英文论文题名：Design of ZYNQBee Readout Module With Giga Bit Ethernet Based On ZYNQ
- 论文作者：薛涛 ; 曾鸣 ; 梁卫平 ; 龚光华 ; 李荐民 ; 潘维斌
- 英文论文作者：Xue Tao ; Zeng Ming ; Liang Weiping ; Gong Guanghua ; Li Jianmin ; Pan Weibin ; Dept.of Tsinghua University ; Beijing Chemical Defended Institute
- 年：2014
- 作者机构：清华大学工程物理系;北京防化研究院;
- 论文关键词：ZYNQ ; XC7Z010 ; 千兆以太网 ; 嵌入式Linux ; ZYNQBee
- 英文论文关键词：ZYNQ ; XC7Z010 ; Giga Ethernet ; Embedded Linux ; ZYNQBee
- 会议召开时间：2014-08-13
- 会议录名称：第十七届全国核电子学与核探测技术学术年会论文集
- 语种：中文
- 分类号：TP393.11;TP334.7
- 学会代码：HDZX
- 会议名称：第十七届全国核电子学与核探测技术学术年会
- 会议地点：中国甘肃兰州
- 主办单位：中国电子学会、中国核学会核电子学与核探测技术分会
- 学会名称：中国电子学会核电子学与核探测技术分会
- 页数：4
- 文件大小：735k
- 原文格式：D
- 会议级别：全国
摘要
ZYNQ是全新架构的现场可编程阵列FPGA和高性能双核ARM Cortex-A9处理器的综合体,而核电子学领域的数据读出一直是影响整个数据采集系统的关键,从传统的处理器加上FPGA的双芯片解决方案到目前的ZYNQ单芯片解决方案,不仅能够有效的减小电子学硬件的尺寸和功耗,还能非常大的提高FPGA和处理器之间的有效带宽,为整个读出电子学带来了新的发展。本文阐述了基于ZYNQ XC7Z010单芯片的读出模块的研制细节,包括整个系统架构和传统架构对比,新架构的硬件设计细节和难点以及性能。另外还包括了DDR3SDRAM布线的关键问题的解决,千兆以太网接口以及嵌入式Linux的移植等。
ZYNQ is the new all programmable SoC architecture of FPGA with dual-core high performance ARM Cortex-A9 processors from Xilinx. It's very suite for nuclear electronics readout. With the new architecture of ZYNQ, the embedded open source Linux with TCP/IP stack and the real time high throughput logic based on VHDL can be combined to run in a single ARM + FPGA chip with lower profile, lower power and highest performance. It's very differently from the classic architecture with two chips, one processor plus one FPGA. This paper will introduce how about the architecture of the readout module and how the new module can archive higher performance than the classic one.
ZYNQ is the new all programmable SoC architecture of FPGA with dual-core high performance ARM Cortex-A9 processors from Xilinx. It's very suite for nuclear electronics readout. With the new architecture of ZYNQ, the embedded open source Linux with TCP/IP stack and the real time high throughput logic based on VHDL can be combined to run in a single ARM + FPGA chip with lower profile, lower power and highest performance. It's very differently from the classic architecture with two chips, one processor plus one FPGA. This paper will introduce how about the architecture of the readout module and how the new module can archive higher performance than the classic one.
引文
[1]Zynq-7000 All Programmable SoCOverview DS190 www.xilinx.com.
[2]Data Sheet of TPS62130 www.ti.com.
[3]wiki.xilinx.com.
[2]Data Sheet of TPS62130 www.ti.com.
[3]wiki.xilinx.com.