一种自动生成Wallace树形乘法器Verilog源代码方法
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摘要
乘法器是计算机系统中央处理单元、数字信号处理器、浮点运算器等数字系统的基本部件,Wallace树型乘法器是一种广泛采用的高速乘法器设计方案。在使用Verlog语言设计乘法器的过程中,由于Wallace树型乘法器的中间项目多,在源代码的输入过程中容易产生输入错误。随着乘法器的输入位数增加,Verilog源代码的数量会急剧增加,因此采用手工输入Verilog源代码的方法效率不高。在一些具体的设计项目中,需要实现操作数数据位数不同的Wallace树型乘法器。针对Wallace树型乘法器的Verilog源代码设计提出改进,设计了一个自动生成Verilog代码的应用程序,可自动生成8×8、24×24、24×26、24×28、26×24和26×26位Wallace树型乘法器,采用仿真软件对生成的Verilog代码进行了测试,解决了人工输入Verilog代码时容易出错的问题,提高了设计效率。
Multipliers are basic components in the central processing unit,digital signal processor,floating point processing unit, and other digital systems. The Wallace tree structure is common in the scheme of high-speed multipliers. Because there are many intermediate items in a Wallace tree,some errors may occur when designer inputs the Verilog source codes. As the number of operands' digits increases,the lines of source codes increase dramatically,so manually inputting source codes is an inefficient method. In some specific design projects,there are necessary to implement Wallace tree with different data widths. An efficient method that can automatically generate Wallace tree multiplier is presented in this paper. Instead of inputting the source codes by designer,the Verilog source codes for Wallace tree multiplier are proposed to be generated by an application program. This application supports the 8 × 8,24× 24,24 × 26,24 × 28,26 × 24,and 26 × 26 bits operands. The generated Verilog codes have been tested by simulation. This method prunes the bugs because of manual inputting source codes,and improves the efficiency of design.
Multipliers are basic components in the central processing unit,digital signal processor,floating point processing unit, and other digital systems. The Wallace tree structure is common in the scheme of high-speed multipliers. Because there are many intermediate items in a Wallace tree,some errors may occur when designer inputs the Verilog source codes. As the number of operands' digits increases,the lines of source codes increase dramatically,so manually inputting source codes is an inefficient method. In some specific design projects,there are necessary to implement Wallace tree with different data widths. An efficient method that can automatically generate Wallace tree multiplier is presented in this paper. Instead of inputting the source codes by designer,the Verilog source codes for Wallace tree multiplier are proposed to be generated by an application program. This application supports the 8 × 8,24× 24,24 × 26,24 × 28,26 × 24,and 26 × 26 bits operands. The generated Verilog codes have been tested by simulation. This method prunes the bugs because of manual inputting source codes,and improves the efficiency of design.
引文
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[5]Jalil Fadavi-Ardekani.Mx N Booth encoded multiplier generator using optimized Wallace trees[J].IEEE Transactions on Very Large Scale Integration System,1993,1(2):120-125.
[6]Niichi Itoh,Yuka Naemura,Hiroshi Makino,et al.A 600-MHz 5454-bit multiplier with rectangular-styled wallace tree[J].IEEE Journal of Solid-State Circuits,2001,36(2):249-257.
[7]Sa’ed Abed1,Bassam Jamil Mohd,Zaid Al-bayati,et al.Low power wallace multiplier design based on wide counters[J].International Journal of Circuit Theory and Applications,2012,40(11):1175-1185.
[8]Arvind Chakrapani,Elanchezian T,Karthikeyan G,et al.A low complexity splitter based parallel multiplier for DSP applications[J].Proceedings of the National Academy of Sciences,India Section A:Physical Sciences,2015,85(2):277-281.
[9]Bharathan Kala,Ramachandran Seshasayanan.An optimized embedded adder for digital signal processing applications[J].Turkish Journal of Electrical Engineering&Computer Sciences,2016,24(6):5224-5237.
[10]Anubhuti Mittal,Ashutosh Nandi,Disha Yadav.Comparative study of 16-order FIR filter design using different multiplication techniques[J].IET Circuits,Devices&Systems,2017,11(3):196-200.
[11]Jiang Xianyang,Xiao Peng,Qiu Meikang,et al.Performance effects of pipeline architecture on an FPGA-based binary 32 floating point multiplier[J].Microprocessors and Microsystems,2017,37(8):1183-1191.
[12]Bahram Rashidi,Sayed Masoud Sayedi.A high speed multiplexer based fine grain pipelined architecture for digital fuzzy logic controllers[J].International Journal of Electronics,2015,102(12):1997-2015.
[13]Liu Weiqiang,Qian Liangyu,Wang Chenghua,et al.Design of approximate radix-4 booth multipliers for error-tolerant computing[J].IEEE Transactions on Computers,2017,66(8):1435-1441.
[14]Ricardo Jasinski.Effective coding with VHDL:Principles and best practice[M].Cambridge:The MIT Press,2016:7-8.
[15]Donald Thomas,Philip Moorby.The Verilog hardware description language[M].Fifth Edition.New York:Springer,2008.
[16]李亚民.计算机原理与设计-Verilog HDL版[M].北京:清华大学出版社,2011.
[2]Behrooz Parhami.Computer arithmetic[M].Second Edition.New York:Oxford University Press,2010.
[3]LU Mi.Arithmetic and logic in computer systems[M].Hoboken:John Wiley&Sons,2004.
[4]Gensuke Goto,Tomio Sato,Masao Nakajima,et al.A 54×54-b regularly structured tree multiplier[J].IEEE Journal of Solid-State Circuits,1992,27(9):1229-1236.
[5]Jalil Fadavi-Ardekani.Mx N Booth encoded multiplier generator using optimized Wallace trees[J].IEEE Transactions on Very Large Scale Integration System,1993,1(2):120-125.
[6]Niichi Itoh,Yuka Naemura,Hiroshi Makino,et al.A 600-MHz 5454-bit multiplier with rectangular-styled wallace tree[J].IEEE Journal of Solid-State Circuits,2001,36(2):249-257.
[7]Sa’ed Abed1,Bassam Jamil Mohd,Zaid Al-bayati,et al.Low power wallace multiplier design based on wide counters[J].International Journal of Circuit Theory and Applications,2012,40(11):1175-1185.
[8]Arvind Chakrapani,Elanchezian T,Karthikeyan G,et al.A low complexity splitter based parallel multiplier for DSP applications[J].Proceedings of the National Academy of Sciences,India Section A:Physical Sciences,2015,85(2):277-281.
[9]Bharathan Kala,Ramachandran Seshasayanan.An optimized embedded adder for digital signal processing applications[J].Turkish Journal of Electrical Engineering&Computer Sciences,2016,24(6):5224-5237.
[10]Anubhuti Mittal,Ashutosh Nandi,Disha Yadav.Comparative study of 16-order FIR filter design using different multiplication techniques[J].IET Circuits,Devices&Systems,2017,11(3):196-200.
[11]Jiang Xianyang,Xiao Peng,Qiu Meikang,et al.Performance effects of pipeline architecture on an FPGA-based binary 32 floating point multiplier[J].Microprocessors and Microsystems,2017,37(8):1183-1191.
[12]Bahram Rashidi,Sayed Masoud Sayedi.A high speed multiplexer based fine grain pipelined architecture for digital fuzzy logic controllers[J].International Journal of Electronics,2015,102(12):1997-2015.
[13]Liu Weiqiang,Qian Liangyu,Wang Chenghua,et al.Design of approximate radix-4 booth multipliers for error-tolerant computing[J].IEEE Transactions on Computers,2017,66(8):1435-1441.
[14]Ricardo Jasinski.Effective coding with VHDL:Principles and best practice[M].Cambridge:The MIT Press,2016:7-8.
[15]Donald Thomas,Philip Moorby.The Verilog hardware description language[M].Fifth Edition.New York:Springer,2008.
[16]李亚民.计算机原理与设计-Verilog HDL版[M].北京:清华大学出版社,2011.