比较分析法在Verilog HDL中的应用研究
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摘要
Verilog HDL是电子设计主流硬件的描述语言之一,在该硬件描述语言中存在大量类似语句。文章提出采用比较分析法对Verilog HDL进行教学,并以Verilog HDL中的两种条件语句:case语句和if语句为例,在语句格式、应用范围、占用资源三方面对两种语句进行对比分析。分析表明,case语句在可读性方面要优于if语句,if语句的使用范围要大于case语句,对于同样的设计,case语句占用逻辑资源要大于if语句。比较分析法可以帮助学员分清概念,提高分析水平,获得规律性认识,快速掌握Verilog HDL。
Verilog HDL is one of the mainstream electronic design hardware description language,which have many similar statements.This paper proposes a comparative analysis method for Verilog HDL teaching.The method takes two conditional statements:case statement and if statement in Verilog HDL as an example:,compares two statements in three aspects:sentence format,application scope and resource occupation.The analysis shows that the case statement is better than the if statement in readability,and the if statement is more widely used than the case statement.For the same design,the case statement takes up more logical resources than the if statement.The comparative analysis method can help students to distinguish the concept,improve the level of analysis,get regular knowledge,and quickly grasp the Verilog HDL.
Verilog HDL is one of the mainstream electronic design hardware description language,which have many similar statements.This paper proposes a comparative analysis method for Verilog HDL teaching.The method takes two conditional statements:case statement and if statement in Verilog HDL as an example:,compares two statements in three aspects:sentence format,application scope and resource occupation.The analysis shows that the case statement is better than the if statement in readability,and the if statement is more widely used than the case statement.For the same design,the case statement takes up more logical resources than the if statement.The comparative analysis method can help students to distinguish the concept,improve the level of analysis,get regular knowledge,and quickly grasp the Verilog HDL.
引文
[1]潘松,陈龙,黄继业.EDA技术与Verilog HDL(第2版)[M].清华大学出版社,2010.
[2]王鹏,陈新武,陈咏恩等.面向应用型本科教育的FPGA课程教学探讨[J].实验技术与管理,2016,33(3):185-188.
[3](美)巴斯克著.Verilog HDL入门(第3版)[M].夏宇闻等译.北京航空航天大学出版社,2008.
[4]李红革,李峭,何锋.Veri Log硬件描述语言与设计[M].北京航空航天大学出版社,2017.
[5](加)斯蒂芬·布朗(Stephen Brown),(加)斯万克·瓦拉纳西(Zvonko Vranesic)著.数字逻辑基础与Verilog设计[M].吴建辉等译.机械工业出版社,2016.
[6]赵天翔,何金枝.以Verilog HDL为重点的数字逻辑课程教学改革与实践[J].电脑知识与技术,2016,12(35):177-178.
[7]李俊一,牛萍娟.基于Verilog HDL设计的多功能数字钟[J].微计算机信息,2006,22(11):79-81.
[8]郭家荣.项目教学法在Verilog HDL程序设计教学中的应用[J].教育现代化,2016,10(30):226-227.
[2]王鹏,陈新武,陈咏恩等.面向应用型本科教育的FPGA课程教学探讨[J].实验技术与管理,2016,33(3):185-188.
[3](美)巴斯克著.Verilog HDL入门(第3版)[M].夏宇闻等译.北京航空航天大学出版社,2008.
[4]李红革,李峭,何锋.Veri Log硬件描述语言与设计[M].北京航空航天大学出版社,2017.
[5](加)斯蒂芬·布朗(Stephen Brown),(加)斯万克·瓦拉纳西(Zvonko Vranesic)著.数字逻辑基础与Verilog设计[M].吴建辉等译.机械工业出版社,2016.
[6]赵天翔,何金枝.以Verilog HDL为重点的数字逻辑课程教学改革与实践[J].电脑知识与技术,2016,12(35):177-178.
[7]李俊一,牛萍娟.基于Verilog HDL设计的多功能数字钟[J].微计算机信息,2006,22(11):79-81.
[8]郭家荣.项目教学法在Verilog HDL程序设计教学中的应用[J].教育现代化,2016,10(30):226-227.