SiC MOSFET器件封装和测试平台的杂散电感提取
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摘要
SiC MOSFET器件优异的性能使其逐渐被应用于高压高频高效变换器中,然而其器件封装和回路杂散电感在高压高频环境下严重影响并限制了其自身性能和潜力。为了准确提取器件封装和测试平台杂散电感,首先建立了考虑所有杂散参数影响的开关瞬态宽频电路等效模型,分析了器件封装电感和测试平台回路杂散电感对SiC MOSFET所受电气应力的影响。然后基于端口的概念,在宽频范围内利用Aligent4294A阻抗分析仪等测量工具对功率回路的阻抗特性进行测量,并采用RLC串联模型,在MATLAB中对测量数据进行拟合,从而获取回路杂散电感参数。采用相同的方法对SiC MOSFET TO封装器件3个端子两两进行测量和拟合,并获取封装的杂散电感。最后将该方法提取的封装电感值和数据手册中提供的电感值进行对比,其最大误差仅为3 nH,而回路电感值和实验结果对比误差仅为8.9 nH。结果表明所提出的杂散电感提取方法可以用于器件封装及测试平台的杂散电感的提取。
The excellent performance of silicon carbide(SiC) MOSFET is gradually applied to high-voltage, high-frequency, and high-efficiency converters. However, device package and loop stray inductance affect and limit the performance and potential of SiC MOSFET. Consequently, we establish an equivalent circuit model of switching transient under the influence of parasitic parameters, and analyze the influences of the packaging inductance and the loop stray inductance of the test platform on the electrical stress of the silicon carbide MOSFET. Then, based on the concept of port, the impedance characteristics of the power loop is measured in the wide-band range by using Aligent 4294 A impedance analyzer, and the value of loop stray inductance parameter can be obtained with RLC series model to fit the measurement data in MATLAB. Based on the same method, three terminals of TO package silicon carbide MOSFET are measured and fitted, and the stray inductance of the package is obtained. Finally, the maximum error between the inductance value of the package and the inductance value provided in the datasheet is only 3 nH, and the error between the inductance value of the loop and the experimental result is 8.9 nH. The results show that the proposed stray inductance extraction method can be used to extract the stray inductance of the device package and test platform.
The excellent performance of silicon carbide(SiC) MOSFET is gradually applied to high-voltage, high-frequency, and high-efficiency converters. However, device package and loop stray inductance affect and limit the performance and potential of SiC MOSFET. Consequently, we establish an equivalent circuit model of switching transient under the influence of parasitic parameters, and analyze the influences of the packaging inductance and the loop stray inductance of the test platform on the electrical stress of the silicon carbide MOSFET. Then, based on the concept of port, the impedance characteristics of the power loop is measured in the wide-band range by using Aligent 4294 A impedance analyzer, and the value of loop stray inductance parameter can be obtained with RLC series model to fit the measurement data in MATLAB. Based on the same method, three terminals of TO package silicon carbide MOSFET are measured and fitted, and the stray inductance of the package is obtained. Finally, the maximum error between the inductance value of the package and the inductance value provided in the datasheet is only 3 nH, and the error between the inductance value of the loop and the experimental result is 8.9 nH. The results show that the proposed stray inductance extraction method can be used to extract the stray inductance of the device package and test platform.
引文
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[19]LIU T,NING R,WONG T T Y,et al.A new characterization technique for extracting parasitic inductances of fast switching power MOSFETs using two-port vector network analyzer[C]∥2017 29th International Symposium on Power Semiconductor Devices and IC's(ISPSD).Sapporo,Japan:IEEE,2017:403-406.
[20]唐新灵,崔翔,赵志斌,等.压接式IGBT动态测试平台杂散电感的提取[J].中国电机工程学报,2017,37(2):652-662.TANG Xinling,CUI Xiang,ZHAO Zhibin,et al.Extraction of stray inductance in press pack IGBTs’dynamic testing platform[J].Proceedings of the CSEE,2017,37(2):652-662.
[21]WANG J,ZHAO T,LI J,et al.Characterization,modeling,and application of 10-kV SiC MOSFET[J].IEEE Transactions on Electron Devices,2008,55(8):1798-1806.
[2]杨媛,文阳,李国玉.大功率IGBT模块及驱动电路综述[J].高电压技术,2018,44(10):3207-3220.YANG Yuan,WEN Yang,LI Guoyu.Review on high-power IGBTmodule and drive circuit[J].High Voltage Engineering,2018,44(10):3207-3220.
[3]MATSUNAMI H.Current SiC technology for power electronic devices beyond Si[J].Microelectronic Engineering,2006,83(1):2-4.
[4]LAGIER T,LADOUX P,DWORAKOWSKI P.Potential of silicon carbide MOSFETs in the DC/DC converters for future HVDC offshore wind farms[J].High Voltage,2017,2(4):233-243.
[5]DAS M K,CALLANAN R,CAPELL D C,et al.State of the art 10kVNMOS transistors[C]∥International Symposium on Power Semiconductor Devices and IC’s.Oralando,USA:IEEE,2008:253-255.
[6]LIU T,NING R,WONG T T Y,et al.Modeling and analysis of Si CMOSFET switching oscillations[J].IEEE Journal of Emerging and Selected Topics in Power Electronics,2016,4(3):747-756.
[7]GONG X,JOSIFOVI?I,FERREIRA J A.Modeling and reduction of conducted EMI of inverters with SiC JFETs on insulated metal substrate[J].IEEE Transactions on Power Electronics,2013,28(7):3138-3146.
[8]柯俊吉,赵志斌,魏昌俊,等.寄生电感对SiC MOSFET开关特性的影响[J].半导体技术,2017,42(3):194-199.KE Junji,ZHAO Zhibin,WEI Changjun,et al.Effect of the parasitic inductance on SiC MOSFET switching characteristics[J].Semiconductor Technology,2017,42(3):194-199.
[9]范春丽,余成龙,龙觉敏,等.寄生参数对SiC MOSFET开关特性的影响[J].上海电机学院学报,2015,18(4):191-200.FAN Chunli,YU Chenglong,LONG Juemin,et al.Simulation of parasitic parameters influence on SiC MOSFET switching performance[J].Journal of Shanghai Dianji University,2015,18(4):191-200.
[10]LI H,MUNK-NIELSEN S.Detail study of SiC MOSFET switching characteristics[C]∥IEEE,International Symposium on Power Electronics for Distributed Generation Systems.Galway,Ireland:IEEE,2014:1-5.
[11]ANTHON A,HERNANDEZ J C,ZHANG Z,et al.Switching investigations on a SiC MOSFET in a TO-247 package[C]∥IECON2014-Conference of the IEEE Industrial Electronics Society.Texas,USA:IEEE,2014:1854-1860.
[12]GUO S,ZHANG L,LEI Y,et al.3.38 MHz operation of 1.2kV SiCMOSFET with integrated ultra-fast gate drive[C]∥2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications(WiPDA).Virginia,USA:IEEE,2015:390-395.
[13]LEMMON A,BANERJEE S,MATOCHA K,et al.Analysis of packaging impedance on performance of SiC MOSFETs[C]∥PCIMEurope 2016-International Exhibition and Conference for Power Electronics.Nuremberg,Germany:VDE,2016:984-991.
[14]LEMMON A,GRAVES R.Parasitic extraction procedure for silicon carbide power modules[C]∥2015 IEEE International Workshop on Integrated Power Packaging(IWIPP).Chicago,USA:IEEE,2015:91-94.
[15]XING K,LEE F C,BOROYEVICH D.Extraction of parasitics within wire-bond IGBT modules[C]∥1998 Applied Power Electronics Conference and Exposition.Kuala Lumpur,Malaysia:IEEE,1998:497-503.
[16]LIU Z,HUANG X,LEE F C,et al.Package parasitic inductance extraction and simulation model development for the high-voltage cascode Ga N HEMT[J].IEEE Transactions on Power Electronics,2014,29(4):1977-1985.
[17]ZHU H,HEFNER A R,LAI J S.Characterization of power electronics system interconnect parasitics using time domain reflectometry[J].IEEE Transactions on Power Electronics,1999,14(4):622-628.
[18]LIU T,NING R,WONG T T Y,et al.Equivalent circuit models and model validation of SiC MOSFET oscillation phenomenon[C]∥2016IEEE Energy Conversion Congress and Exposition(ECCE).Milwaukee,USA:IEEE,2016:1-8.
[19]LIU T,NING R,WONG T T Y,et al.A new characterization technique for extracting parasitic inductances of fast switching power MOSFETs using two-port vector network analyzer[C]∥2017 29th International Symposium on Power Semiconductor Devices and IC's(ISPSD).Sapporo,Japan:IEEE,2017:403-406.
[20]唐新灵,崔翔,赵志斌,等.压接式IGBT动态测试平台杂散电感的提取[J].中国电机工程学报,2017,37(2):652-662.TANG Xinling,CUI Xiang,ZHAO Zhibin,et al.Extraction of stray inductance in press pack IGBTs’dynamic testing platform[J].Proceedings of the CSEE,2017,37(2):652-662.
[21]WANG J,ZHAO T,LI J,et al.Characterization,modeling,and application of 10-kV SiC MOSFET[J].IEEE Transactions on Electron Devices,2008,55(8):1798-1806.
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