基于三值文字运算的碳纳米场效应晶体管SRAM设计
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摘要
通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信号理论设计文字运算电路;然后采用文字0、文字1和文字2非运算电路实现三值SRAM的功能,利用传输门控制反馈回路降低三值写操作的动态功耗;最后实验验证,所设计的电路逻辑功能正确且与传统交叉耦合SRAM相比写速度提高49.2%。
Based on the analysis of the literal circuit and ternary memorizer, a ternary SRAM design method is proposed, which integrates with literal circuit and the CNFET. Firstly, the literal circuit is designed by literal circuit truth table and switch-signal theory. According to literal circuit, the ternary SRAM cell is achieved. Moreover, the technique of transmission gate control feedback loop is used to reduce dynamic power during write operation. The experiment result shows that the proposed circuit has proper functionality. Comparing with cross-coupling structure SRAM, the designed circuit improves about 49. 2 % in writing speed.
Based on the analysis of the literal circuit and ternary memorizer, a ternary SRAM design method is proposed, which integrates with literal circuit and the CNFET. Firstly, the literal circuit is designed by literal circuit truth table and switch-signal theory. According to literal circuit, the ternary SRAM cell is achieved. Moreover, the technique of transmission gate control feedback loop is used to reduce dynamic power during write operation. The experiment result shows that the proposed circuit has proper functionality. Comparing with cross-coupling structure SRAM, the designed circuit improves about 49. 2 % in writing speed.
引文
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[10]Stanford Nanoelectronics Lab.Stanford CNFET model and Schottky barrier CNFET model[EB/OL].[2015-12-18].http://nano.stanford.edu/model.php?id=23.
[11]GHANATGHESTANI M M,PEDRAM H,GHAVAMI B.Design of a low-Standby power and high-Speed ternary memory cell based on carbon nanotube field-effect transistor[J].Journal of Computational&Theoretical Nanoscience,2015,12(12):5457-5462.
[12]SRINIVASAN P,BHAT A S,MEROTIYA S L,et al.Design and performance evaluation of a low transistor ternary CNTFET SRAM cell[C].International Conference on Electronic Design,Computer Networks&Automated Verification.IEEE,2015:38-43.
[2]LIN S,KIM Y B,LOMBARDI F.Design of a CNTFETbased SRAM cell by dual-chirality selection[J].IEEE Transactions on Nanotechnology,2010,9(1):30-37.
[3]郑雪松.基于绝热多米诺逻辑的多值时序电路研究[D].宁波:宁波大学,2014.
[4]董晨.粒子群优化的超大规模集成电路全局布线策略[D].武汉:武汉大学,2011.
[5]LIN S,KIM B,LOMBARDI F.Design of a ternary memory cell using CNTFETs[J].IEEE Transactions on Nanotechnology,2012,11(5):1019-1025.
[6]KAMAR Z,NEPAL K.Noise margin-optimized ternary CMOS SRAM delay and sizing characteristics[J].Midwest Symposium on Circuits&Systems,2010,12(8):801-804.
[7]MUROTIYA S L,GUPTA A.A novel design of ternary full adder using CNTFETs[J].Arabian Journal for Science&Engineering,2014,39(11):7839-7846.
[8]吴训威.多值逻辑电路设计原理[M].杭州:杭州大学出版社,1994.
[9]杨乾坤,汪鹏君,郑雪松.三值绝热多米诺文字运算电路开关级设计[J].新能源进展,2012,17(4):36-40.
[10]Stanford Nanoelectronics Lab.Stanford CNFET model and Schottky barrier CNFET model[EB/OL].[2015-12-18].http://nano.stanford.edu/model.php?id=23.
[11]GHANATGHESTANI M M,PEDRAM H,GHAVAMI B.Design of a low-Standby power and high-Speed ternary memory cell based on carbon nanotube field-effect transistor[J].Journal of Computational&Theoretical Nanoscience,2015,12(12):5457-5462.
[12]SRINIVASAN P,BHAT A S,MEROTIYA S L,et al.Design and performance evaluation of a low transistor ternary CNTFET SRAM cell[C].International Conference on Electronic Design,Computer Networks&Automated Verification.IEEE,2015:38-43.